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Fri, 06 Mar 2026 09:12:34 -0800 (PST) From: Anirudh Srinivasan Date: Fri, 06 Mar 2026 11:12:18 -0600 Subject: [PATCH v8 2/3] reset: tenstorrent: Add reset controller for Atlantis Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-atlantis-clocks-v8-2-6c9b14a4aa8e@oss.tenstorrent.com> References: <20260306-atlantis-clocks-v8-0-6c9b14a4aa8e@oss.tenstorrent.com> In-Reply-To: <20260306-atlantis-clocks-v8-0-6c9b14a4aa8e@oss.tenstorrent.com> To: Drew Fustini , Joel Stanley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Anirudh Srinivasan , Philipp Zabel Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, joel@jms.id.au, fustini@kernel.org, mpe@kernel.org, mpe@oss.tenstorrent.com, npiggin@oss.tenstorrent.com, agross@kernel.org, agross@oss.tenstorrent.com, bmasney@redhat.com, Krzysztof Kozlowski X-Mailer: b4 0.14.3 Adds Atlantis Reset Controller driver, which shares the same regmap as prcm ( clock controller). This version of the reset controller driver covers resets from the RCPU prcm. Reviewed-by: Philipp Zabel Acked-by: Philipp Zabel Signed-off-by: Anirudh Srinivasan Reviewed-by: Drew Fustini --- MAINTAINERS | 1 + drivers/reset/Kconfig | 11 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-tenstorrent-atlantis.c | 173 +++++++++++++++++++++++++= ++++ 4 files changed, 186 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 40c179c8de1e..493d007d3c65 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22812,6 +22812,7 @@ T: git https://github.com/tenstorrent/linux.git F: Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.= yaml F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml F: arch/riscv/boot/dts/tenstorrent/ +F: drivers/reset/reset-tenstorrent-atlantis.c F: include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h =20 RISC-V THEAD SoC SUPPORT diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 7ce151f6a7e4..85ee9da809ee 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -315,6 +315,17 @@ config RESET_SUNXI help This enables the reset driver for Allwinner SoCs. =20 +config RESET_TENSTORRENT_ATLANTIS + tristate "Tenstorrent atlantis reset driver" + depends on ARCH_TENSTORRENT || COMPILE_TEST + select AUXILIARY_BUS + default ARCH_TENSTORRENT + help + This enables the driver for the reset controller + present in the Tenstorrent Atlantis SoC. + Enable this option to be able to use hardware + resets on Atalantis based systems. + config RESET_TH1520 tristate "T-HEAD TH1520 reset controller" depends on ARCH_THEAD || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index fc0cc99f8514..7c086baeb02a 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_RESET_SIMPLE) +=3D reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) +=3D reset-socfpga.o obj-$(CONFIG_RESET_SUNPLUS) +=3D reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) +=3D reset-sunxi.o +obj-$(CONFIG_RESET_TENSTORRENT_ATLANTIS) +=3D reset-tenstorrent-atlantis.o obj-$(CONFIG_RESET_TH1520) +=3D reset-th1520.o obj-$(CONFIG_RESET_TI_SCI) +=3D reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) +=3D reset-ti-syscon.o diff --git a/drivers/reset/reset-tenstorrent-atlantis.c b/drivers/reset/res= et-tenstorrent-atlantis.c new file mode 100644 index 000000000000..ab8be52fdd5e --- /dev/null +++ b/drivers/reset/reset-tenstorrent-atlantis.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Tenstorrent Atlantis PRCM Reset Driver + * + * Copyright (c) 2026 Tenstorrent + */ + +#include +#include +#include +#include + +/* RCPU Reset Register Offsets */ +#define RCPU_BLK_RST_REG 0x001c +#define LSIO_BLK_RST_REG 0x0020 +#define HSIO_BLK_RST_REG 0x000c +#define PCIE_SUBS_RST_REG 0x0000 +#define MM_RSTN_REG 0x0014 + +struct atlantis_reset_data { + u8 bit; + u16 reg; + bool active_low; +}; + +struct atlantis_reset_controller_data { + const struct atlantis_reset_data *reset_data; + size_t count; +}; + +struct atlantis_reset_controller { + struct reset_controller_dev rcdev; + const struct atlantis_reset_controller_data *data; + struct regmap *regmap; +}; + +static inline struct atlantis_reset_controller * +to_atlantis_reset_controller(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct atlantis_reset_controller, rcdev); +} + +#define RESET_DATA(_reg, _bit, _active_low) \ + { \ + .bit =3D _bit, .reg =3D _reg, .active_low =3D _active_low, \ + } + +static const struct atlantis_reset_data atlantis_rcpu_resets[] =3D { + [RST_SMNDMA0] =3D RESET_DATA(RCPU_BLK_RST_REG, 0, true), + [RST_SMNDMA1] =3D RESET_DATA(RCPU_BLK_RST_REG, 1, true), + [RST_WDT0] =3D RESET_DATA(RCPU_BLK_RST_REG, 2, true), + [RST_WDT1] =3D RESET_DATA(RCPU_BLK_RST_REG, 3, true), + [RST_TMR] =3D RESET_DATA(RCPU_BLK_RST_REG, 4, true), + [RST_PVTC] =3D RESET_DATA(RCPU_BLK_RST_REG, 12, true), + [RST_PMU] =3D RESET_DATA(RCPU_BLK_RST_REG, 13, true), + [RST_MAILBOX] =3D RESET_DATA(RCPU_BLK_RST_REG, 14, true), + [RST_SPACC] =3D RESET_DATA(RCPU_BLK_RST_REG, 26, true), + [RST_OTP] =3D RESET_DATA(RCPU_BLK_RST_REG, 28, true), + [RST_TRNG] =3D RESET_DATA(RCPU_BLK_RST_REG, 29, true), + [RST_CRC] =3D RESET_DATA(RCPU_BLK_RST_REG, 30, true), + [RST_QSPI] =3D RESET_DATA(LSIO_BLK_RST_REG, 0, true), + [RST_I2C0] =3D RESET_DATA(LSIO_BLK_RST_REG, 1, true), + [RST_I2C1] =3D RESET_DATA(LSIO_BLK_RST_REG, 2, true), + [RST_I2C2] =3D RESET_DATA(LSIO_BLK_RST_REG, 3, true), + [RST_I2C3] =3D RESET_DATA(LSIO_BLK_RST_REG, 4, true), + [RST_I2C4] =3D RESET_DATA(LSIO_BLK_RST_REG, 5, true), + [RST_UART0] =3D RESET_DATA(LSIO_BLK_RST_REG, 6, true), + [RST_UART1] =3D RESET_DATA(LSIO_BLK_RST_REG, 7, true), + [RST_UART2] =3D RESET_DATA(LSIO_BLK_RST_REG, 8, true), + [RST_UART3] =3D RESET_DATA(LSIO_BLK_RST_REG, 9, true), + [RST_UART4] =3D RESET_DATA(LSIO_BLK_RST_REG, 10, true), + [RST_SPI0] =3D RESET_DATA(LSIO_BLK_RST_REG, 11, true), + [RST_SPI1] =3D RESET_DATA(LSIO_BLK_RST_REG, 12, true), + [RST_SPI2] =3D RESET_DATA(LSIO_BLK_RST_REG, 13, true), + [RST_SPI3] =3D RESET_DATA(LSIO_BLK_RST_REG, 14, true), + [RST_GPIO] =3D RESET_DATA(LSIO_BLK_RST_REG, 15, true), + [RST_CAN0] =3D RESET_DATA(LSIO_BLK_RST_REG, 17, true), + [RST_CAN1] =3D RESET_DATA(LSIO_BLK_RST_REG, 18, true), + [RST_I2S0] =3D RESET_DATA(LSIO_BLK_RST_REG, 19, true), + [RST_I2S1] =3D RESET_DATA(LSIO_BLK_RST_REG, 20, true), + +}; + +static const struct atlantis_reset_controller_data atlantis_rcpu_reset_dat= a =3D { + .reset_data =3D atlantis_rcpu_resets, + .count =3D ARRAY_SIZE(atlantis_rcpu_resets), +}; + +static int atlantis_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + unsigned int val; + struct atlantis_reset_controller *rst =3D + to_atlantis_reset_controller(rcdev); + const struct atlantis_reset_data *data =3D &rst->data->reset_data[id]; + unsigned int mask =3D BIT(data->bit); + struct regmap *regmap =3D rst->regmap; + + if (data->active_low ^ assert) + val =3D mask; + else + val =3D 0; + + return regmap_update_bits(regmap, data->reg, mask, val); +} + +static int atlantis_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return atlantis_reset_update(rcdev, id, true); +} + +static int atlantis_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return atlantis_reset_update(rcdev, id, false); +} + +static const struct reset_control_ops atlantis_reset_control_ops =3D { + .assert =3D atlantis_reset_assert, + .deassert =3D atlantis_reset_deassert, +}; + +static int +atlantis_reset_controller_register(struct device *dev, + struct atlantis_reset_controller *controller) +{ + struct reset_controller_dev *rcdev =3D &controller->rcdev; + + rcdev->ops =3D &atlantis_reset_control_ops; + rcdev->owner =3D THIS_MODULE; + rcdev->of_node =3D dev->of_node; + rcdev->nr_resets =3D controller->data->count; + + return devm_reset_controller_register(dev, &controller->rcdev); +} +static int atlantis_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct atlantis_reset_controller *controller; + struct device *dev =3D &adev->dev; + struct regmap *regmap; + + regmap =3D dev_get_regmap(dev->parent, NULL); + if (!regmap) + return -ENODEV; + + controller =3D devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); + if (!controller) + return -ENOMEM; + controller->data =3D + (const struct atlantis_reset_controller_data *)id->driver_data; + controller->regmap =3D regmap; + + return atlantis_reset_controller_register(dev, controller); +} + +static const struct auxiliary_device_id atlantis_reset_ids[] =3D { + { .name =3D "atlantis_prcm.rcpu-reset", + .driver_data =3D (kernel_ulong_t)&atlantis_rcpu_reset_data }, + {}, +}; +MODULE_DEVICE_TABLE(auxiliary, atlantis_reset_ids); + +static struct auxiliary_driver atlantis_reset_driver =3D { + .probe =3D atlantis_reset_probe, + .id_table =3D atlantis_reset_ids, +}; +module_auxiliary_driver(atlantis_reset_driver); + +MODULE_AUTHOR("Anirudh Srinivasan "); +MODULE_DESCRIPTION("Atlantis PRCM reset controller driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0