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Thu, 5 Mar 2026 11:09:39 -0800 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [PATCH 2/2] gpu: nova-core: add fwctl driver for firmware control interface Date: Thu, 5 Mar 2026 19:09:36 +0000 Message-ID: <20260305190936.398590-3-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260305190936.398590-1-zhiw@nvidia.com> References: <20260305190936.398590-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B1:EE_|SJ0PR12MB6928:EE_ X-MS-Office365-Filtering-Correlation-Id: b1670129-09b4-4392-bf12-08de7aeaccbc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700016|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: VinNu5Zn+AMppdudrTo1cfzrmBhp6ASc3BzUWtFiczCXnQXOINADa47R0xvHuAfF8od3eBi4FtoJNVoGH2FGs/tkDZhCGp7i03NaVzJtXSJw56wcCCOH8wlvBctZEfgSzkX82uiVEmTlu7rlYHkZzSkiR6rgLHF3LqgwKiowGd2nn9rHCPHLRwR8YBmcKhyDA1s6NFsAOjmB8oPkZVvRsHjXZwk7H3R1W0zc3AU0Nlv8LNqlYvenXaPHwieZZ/idN9gOO5f1o89gOrYXVKo63Bzo20cBsnfVH3V7G1/Q17hZVv2o/dUShXePgJq67hpvFx9CpmROO3kzH0jtHqDo/rCcN702asIiOwSePivP+mRzZK3CE8j8ibxyf7ol9GsSdG0LKtcglf/urcl09eErpPAcwKRJXx9t/xQzYRf1Y3UoWNfcQM1Oal8psJo2SnUb6wKoH/PRuULf2Y+bgubucU+goEi5TamEm5LVoYj5+IkUDXfLvbo7qaQj0Qod1oVtDUDCCAejQrs+R88VfmLPQ6RIZgdx+4H9ybl8IoI+MOb9INHkO4ZyLGtS6su3i0a4F8I82krZ+tbx5ZEMa5qe0HkozNpHgg8HFcOTkfU0R39/uZvLFyzPZP82nqIr8jRMiDTb21eDOONaD4kut+81el5A1ghLJzmuhVJc5Wsm9sOWi0RMJZcQpXXS68dw6GZKvf70U4iOQdtshYZ+mj3crtqenn5cAcFPETWsn64hpJtY/+jssi9ke2F9Iclz/0CTksC9g0Soh5QlMJyRAoym3Q== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(36860700016)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; 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charset="utf-8" Add a fwctl driver that provides an infrastructure for userspace to issue firmware commands to the GSP. New commands can be added by extending RmControlMsgFunction and the fwctl command dispatch table. As a first user, add FWCTL_CMD_NOVA_CORE_UPLOAD_VGPU_TYPE, which uploads vGPU type definitions to the GSP. It is a required step before any vGPU can be created. Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/fwctl.rs | 99 +++++++++++++++++++ drivers/gpu/nova-core/gpu.rs | 4 +- drivers/gpu/nova-core/gsp.rs | 25 ++++- drivers/gpu/nova-core/gsp/boot.rs | 6 +- .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 1 + drivers/gpu/nova-core/gsp/fw/rm.rs | 5 + drivers/gpu/nova-core/gsp/rm/commands.rs | 4 +- drivers/gpu/nova-core/nova_core.rs | 2 + include/uapi/fwctl/fwctl.h | 1 + include/uapi/fwctl/nova-core.h | 52 ++++++++++ rust/kernel/fwctl.rs | 2 + rust/uapi/uapi_helper.h | 1 + 12 files changed, 193 insertions(+), 9 deletions(-) create mode 100644 drivers/gpu/nova-core/fwctl.rs create mode 100644 include/uapi/fwctl/nova-core.h diff --git a/drivers/gpu/nova-core/fwctl.rs b/drivers/gpu/nova-core/fwctl.rs new file mode 100644 index 000000000000..9ec147a815db --- /dev/null +++ b/drivers/gpu/nova-core/fwctl.rs @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::{ + fwctl::{ + self, + DeviceType, + FwRpcResponse, + Operations, + RpcScope, // + }, + prelude::*, + transmute::{AsBytes, FromBytes}, + uapi, // +}; + +use crate::{ + driver::NovaCore, + gsp::{ + RmControlMsgFunction, + rm::commands::send_rm_control, // + }, +}; + +/// Byte-serializable wrapper for [`uapi::fwctl_rpc_nova_core_request_hdr`= ]. +#[repr(transparent)] +struct FwctlNovaCoreReqHdr(uapi::fwctl_rpc_nova_core_request_hdr); + +// SAFETY: All fields are plain `__u32` with no padding. +unsafe impl FromBytes for FwctlNovaCoreReqHdr {} + +/// Byte-serializable wrapper for [`uapi::fwctl_rpc_nova_core_resp_hdr`]. +#[repr(transparent)] +struct FwctlNovaCoreRespHdr(uapi::fwctl_rpc_nova_core_resp_hdr); + +// SAFETY: All fields are plain `__u32` with no padding. +unsafe impl AsBytes for FwctlNovaCoreRespHdr {} + +/// Per-FD fwctl user context and operations for nova-core. +pub(crate) struct NovaCoreFwCtl; + +impl Operations for NovaCoreFwCtl { + type DeviceData =3D (); + + const DEVICE_TYPE: DeviceType =3D DeviceType::NovaCore; + + fn open(_device: &fwctl::Device) -> Result, Error> { + Ok(Ok(NovaCoreFwCtl)) + } + + fn fw_rpc( + _this: &Self, + device: &fwctl::Device, + scope: RpcScope, + rpc_in: &mut [u8], + ) -> Result { + let hdr_size =3D size_of::(); + + if rpc_in.len() < hdr_size { + return Err(EINVAL); + } + + if scope !=3D RpcScope::Configuration { + return Err(EPERM); + } + + let (hdr, _) =3D FwctlNovaCoreReqHdr::from_bytes_prefix(rpc_in).ok= _or(EINVAL)?; + let cmd =3D hdr.0.cmd; + + let rm_cmd =3D match cmd { + uapi::fwctl_cmd_nova_core_FWCTL_CMD_NOVA_CORE_UPLOAD_VGPU_TYPE= =3D> { + RmControlMsgFunction::VgpuMgrInternalPgpuAddVgpuType + } + _ =3D> return Err(EINVAL), + }; + + let parent =3D device.parent(); + let data =3D parent.drvdata::()?; + let bar =3D data.gpu.bar.as_ref().access(parent)?; + + let params =3D &rpc_in[hdr_size..]; + let reply_params =3D send_rm_control( + &data.gpu.gsp.cmdq, + bar, + data.gpu.gsp.h_client, + data.gpu.gsp.h_subdevice, + rm_cmd, + params, + )?; + + let resp_hdr =3D FwctlNovaCoreRespHdr(uapi::fwctl_rpc_nova_core_re= sp_hdr { + mctp_header: 0, + nvdm_header: 0, + }); + let mut out =3D KVec::new(); + out.extend_from_slice(resp_hdr.as_bytes(), GFP_KERNEL)?; + out.extend_from_slice(&reply_params, GFP_KERNEL)?; + Ok(FwRpcResponse::NewBuffer(out)) + } +} diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 60c85fffaeaf..7965ce37eb08 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -241,7 +241,7 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Resul= t { pub(crate) struct Gpu { spec: Spec, /// MMIO mapping of PCI BAR 0 - bar: Arc>, + pub(crate) bar: Arc>, /// System memory page required for flushing all pending GPU-side memo= ry writes done through /// PCIE into system memory, via sysmembar (A GPU-initiated HW memory-= barrier operation). sysmem_flush: SysmemFlush, @@ -251,7 +251,7 @@ pub(crate) struct Gpu { sec2_falcon: Falcon, /// GSP runtime data. Temporarily an empty placeholder. #[pin] - gsp: Gsp, + pub(crate) gsp: Gsp, } =20 impl Gpu { diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 1a1c4e9808ac..77eb30010c2f 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -4,11 +4,13 @@ =20 use kernel::{ device, + devres::Devres, dma::{ CoherentAllocation, DmaAddress, // }, dma_write, + fwctl, pci, prelude::*, transmute::AsBytes, // @@ -21,15 +23,19 @@ mod sequencer; =20 pub(crate) use fw::{ + rm::RmControlMsgFunction, GspFwWprMeta, LibosParams, // }; =20 use crate::{ - gsp::cmdq::Cmdq, - gsp::fw::{ - GspArgumentsPadded, - LibosMemoryRegionInitArgument, // + fwctl::NovaCoreFwCtl, + gsp::{ + cmdq::Cmdq, + fw::{ + GspArgumentsPadded, + LibosMemoryRegionInitArgument, // + }, }, num, }; @@ -117,6 +123,12 @@ pub(crate) struct Gsp { pub(crate) cmdq: Cmdq, /// RM arguments. rmargs: CoherentAllocation, + /// Cached RM internal client handle from GSP static info. + pub(crate) h_client: u32, + /// Cached RM internal subdevice handle from GSP static info. + pub(crate) h_subdevice: u32, + /// fwctl registration for userspace RM control. + fwctl: Pin>>>, } =20 impl Gsp { @@ -125,6 +137,8 @@ pub(crate) fn new(pdev: &pci::Device) ->= impl PinInit::new(pdev.as_= ref(), Ok(()))?; + Ok(try_pin_init!(Self { libos: CoherentAllocation::= ::alloc_coherent( dev, @@ -140,6 +154,9 @@ pub(crate) fn new(pdev: &pci::Device) ->= impl PinInit, + mut self: Pin<&mut Self>, pdev: &pci::Device, bar: &Bar0, chipset: Chipset, @@ -221,6 +221,10 @@ pub(crate) fn boot( =20 // Obtain and display basic GPU information. let info =3D commands::get_gsp_info(&self.cmdq, bar)?; + // SAFETY: h_client and h_subdevice are not structurally pinned. + let this =3D unsafe { self.as_mut().get_unchecked_mut() }; + this.h_client =3D info.h_client(); + this.h_subdevice =3D info.h_subdevice(); match info.gpu_name() { Ok(name) =3D> dev_info!(pdev, "GPU name: {}\n", name), Err(e) =3D> dev_warn!(pdev, "GPU name unavailable: {:?}\n", e), diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gp= u/nova-core/gsp/fw/r570_144/bindings.rs index 354ee2cfa295..b5b16451a507 100644 --- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs +++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs @@ -45,6 +45,7 @@ fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::= core::fmt::Result { pub const REGISTRY_TABLE_ENTRY_TYPE_DWORD: u32 =3D 1; pub const GSP_MSG_QUEUE_ELEMENT_SIZE_MAX: u32 =3D 65536; pub const NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE: u32 =3D 5452702= 80; +pub const NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE: u32 =3D 54= 5275907; pub type __u8 =3D ffi::c_uchar; pub type __u16 =3D ffi::c_ushort; pub type __u32 =3D ffi::c_uint; diff --git a/drivers/gpu/nova-core/gsp/fw/rm.rs b/drivers/gpu/nova-core/gsp= /fw/rm.rs index 9f1e3546d39d..c0b6e90ee135 100644 --- a/drivers/gpu/nova-core/gsp/fw/rm.rs +++ b/drivers/gpu/nova-core/gsp/fw/rm.rs @@ -19,6 +19,8 @@ pub(crate) enum RmControlMsgFunction { /// Get the CE fault method buffer size. CeGetFaultMethodBufferSize =3D bindings::NV2080_CTRL_CMD_CE_GET_FAULT_= METHOD_BUFFER_SIZE, + /// Upload vGPU type definitions to GSP. + VgpuMgrInternalPgpuAddVgpuType =3D bindings::NV2080_CTRL_CMD_VGPU_MGR_= INTERNAL_PGPU_ADD_VGPU_TYPE, } =20 impl TryFrom for RmControlMsgFunction { @@ -29,6 +31,9 @@ fn try_from(value: u32) -> Result { bindings::NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE =3D>= { Ok(Self::CeGetFaultMethodBufferSize) } + bindings::NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE= =3D> { + Ok(Self::VgpuMgrInternalPgpuAddVgpuType) + } _ =3D> Err(EINVAL), } } diff --git a/drivers/gpu/nova-core/gsp/rm/commands.rs b/drivers/gpu/nova-co= re/gsp/rm/commands.rs index 1d045e6f1afb..02670899d2bc 100644 --- a/drivers/gpu/nova-core/gsp/rm/commands.rs +++ b/drivers/gpu/nova-core/gsp/rm/commands.rs @@ -98,7 +98,7 @@ fn read( } =20 /// Sends an RM control command, checks the reply status, and returns the = raw parameter bytes. -fn send_rm_control( +pub(crate) fn send_rm_control( cmdq: &Cmdq, bar: &Bar0, h_client: u32, @@ -106,7 +106,7 @@ fn send_rm_control( cmd: RmControlMsgFunction, params: &[u8], ) -> Result> { - let reply =3D cmdq.send_sync_command(bar, RmControl::new(h_client, h_o= bject, cmd, params))?; + let reply =3D cmdq.send_command(bar, RmControl::new(h_client, h_object= , cmd, params))?; =20 Result::from(reply.status)?; =20 diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index b5caf1044697..863dc041272c 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -10,6 +10,7 @@ mod falcon; mod fb; mod firmware; +mod fwctl; mod gfw; mod gpu; mod gsp; @@ -27,6 +28,7 @@ description: "Nova Core GPU driver", license: "GPL v2", firmware: [], + imports_ns: ["FWCTL"], } =20 kernel::module_firmware!(firmware::ModInfoBuilder); diff --git a/include/uapi/fwctl/fwctl.h b/include/uapi/fwctl/fwctl.h index 716ac0eee42d..f6289fbf3062 100644 --- a/include/uapi/fwctl/fwctl.h +++ b/include/uapi/fwctl/fwctl.h @@ -45,6 +45,7 @@ enum fwctl_device_type { FWCTL_DEVICE_TYPE_MLX5 =3D 1, FWCTL_DEVICE_TYPE_CXL =3D 2, FWCTL_DEVICE_TYPE_PDS =3D 4, + FWCTL_DEVICE_TYPE_NOVA_CORE =3D 5, }; =20 /** diff --git a/include/uapi/fwctl/nova-core.h b/include/uapi/fwctl/nova-core.h new file mode 100644 index 000000000000..3f1d94b44ec8 --- /dev/null +++ b/include/uapi/fwctl/nova-core.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES + * + * nova-core fwctl device specific definitions. + * + * The device_type for this file is FWCTL_DEVICE_TYPE_NOVA_CORE. + */ +#ifndef _UAPI_FWCTL_NOVA_CORE_H +#define _UAPI_FWCTL_NOVA_CORE_H + +#include + +/** + * enum fwctl_cmd_nova_core - Firmware command identifiers + * @FWCTL_CMD_NOVA_CORE_UPLOAD_VGPU_TYPE: Upload vGPU type definitions to = GSP. + * Payload is NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS. + */ +enum fwctl_cmd_nova_core { + FWCTL_CMD_NOVA_CORE_UPLOAD_VGPU_TYPE =3D 0, +}; + +/** + * struct fwctl_rpc_nova_core_request_hdr - ioctl(FWCTL_RPC) input header + * @cmd: Command identifier from &enum fwctl_cmd_nova_core. + * @mctp_header: MCTP transport header (packed u32). + * @nvdm_header: NVDM vendor-defined message header (packed u32). + * + * Placed at &struct fwctl_rpc.in with total length &struct fwctl_rpc.in_l= en. + * The access scope is specified through &struct fwctl_rpc.scope. + * Followed by command-specific input parameters. + */ +struct fwctl_rpc_nova_core_request_hdr { + __u32 mctp_header; + __u32 nvdm_header; + __u32 cmd; +}; + +/** + * struct fwctl_rpc_nova_core_resp_hdr - ioctl(FWCTL_RPC) output header + * @mctp_header: MCTP transport header (packed u32). + * @nvdm_header: NVDM vendor-defined message header (packed u32). + * + * Placed at &struct fwctl_rpc.out with total length &struct fwctl_rpc.out= _len. + * Followed by command-specific output parameters. + */ +struct fwctl_rpc_nova_core_resp_hdr { + __u32 mctp_header; + __u32 nvdm_header; +}; + +#endif diff --git a/rust/kernel/fwctl.rs b/rust/kernel/fwctl.rs index bbced4761e0c..345e96144028 100644 --- a/rust/kernel/fwctl.rs +++ b/rust/kernel/fwctl.rs @@ -34,6 +34,8 @@ pub enum DeviceType { Cxl =3D bindings::fwctl_device_type_FWCTL_DEVICE_TYPE_CXL, /// AMD/Pensando PDS device. Pds =3D bindings::fwctl_device_type_FWCTL_DEVICE_TYPE_PDS, + /// NVIDIA Nova Core GPU device. + NovaCore =3D bindings::fwctl_device_type_FWCTL_DEVICE_TYPE_NOVA_CORE, } =20 impl From for u32 { diff --git a/rust/uapi/uapi_helper.h b/rust/uapi/uapi_helper.h index 06d7d1a2e8da..df3309afc055 100644 --- a/rust/uapi/uapi_helper.h +++ b/rust/uapi/uapi_helper.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include --=20 2.51.0