From nobody Thu Apr 9 23:25:14 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1339037C930 for ; Thu, 5 Mar 2026 10:02:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772704936; cv=none; b=YIHxAAEUIPUklcMXHYh9ix8xULRVW+xyzJAB8+bnJhfP/zCNfqKIXkOmBDDU9s/6qcvxnjfhpRSW6ajnejJjA0Igd9+XQTnNMvUh/iEbIHGPb6i+aQ1+LCyihWxrbBU5jMBOWxehLunigpO5ruCBfl/trqHQDjaeQocAA5b/XVI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772704936; c=relaxed/simple; bh=82jHg/C84we0ggMOiWeHcRKzXN+cdC4vj8XTNcKMh+Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I+/o7xRhW1ZPi8ecYFSeeCRdxIZ5LLVnj4vXZ9tm4eTr7Y4t9SlebzfJVwf5xrktoKYsQSzl8GqenypaIAhCZHJn1d0+MFyeP7q/yqTP11UF7AZX8MuqF6jUt31gZ8SxvoeWfmDmMXYj9cxmxpdxHYBtww7ra6Yjj3U47uo/r5Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Zghiv2yo; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Zghiv2yo" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 0A8E1C40416; Thu, 5 Mar 2026 10:02:25 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 821595FDEB; Thu, 5 Mar 2026 10:02:06 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 3C67410369782; Thu, 5 Mar 2026 11:02:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772704924; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=1fl+dYL251xXhtusEZ7b8g0kjCughX2VCuIW1qgsL2Q=; b=Zghiv2yoEfOauiKl+7OTiaMkunISYRUhHzMXxmuaIzAGpGxApG7CiDMXvPQ5zHnHZ0rom4 8eqbL/QkYOOvaoUtnF4N1Fr/sJHS7nKFaIUVvfCqfOD1dbOigohz9hABMKrYbU9L3kvL0k Id31ptliJ7YLUKThNetmyQxFWFGz+BL5geqUHPrFgRlOwQFeyROwr1gpFXdFPuP7pwqhxI /d0e9cEYiVySQzWnyNhiyM4mJEx1PDdZnGbmufZ7N9psPVpm3oRqegxMRXb/YoxxrRsWrt 88TMVNqFuWcgnU5/x+8nZ0UUMzwGTWotg9Q3SVvDHhviKRZTcqs6NMExh1Mjpg== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Wentao Liang , Maxime Ripard , Boris Brezillon , Thomas Petazzoni , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v2 1/6] mtd: rawnand: sunxi: sunxi_nand_ooblayout_free code clarification Date: Thu, 5 Mar 2026 11:01:32 +0100 Message-ID: <20260305100137.2558423-2-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260305100137.2558423-1-richard.genoud@bootlin.com> References: <20260305100137.2558423-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The available length is really USER_DATA_LEN - 2 instead of just 2 (the user data length minus the BBM length) USER_DATA_LEN being 4, that doesn't change anything now, but if USER_DATA_LEN changes, it will. Signed-off-by: Richard Genoud Reviewed-by: Chen-Yu Tsai --- drivers/mtd/nand/raw/sunxi_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index e66adfcca7cd..915f1240546f 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -1755,12 +1755,12 @@ static int sunxi_nand_ooblayout_free(struct mtd_inf= o *mtd, int section, =20 /* * The first 2 bytes are used for BB markers, hence we - * only have 2 bytes available in the first user data + * only have USER_DATA_SZ - 2 bytes available in the first user data * section. */ if (!section && ecc->engine_type =3D=3D NAND_ECC_ENGINE_TYPE_ON_HOST) { oobregion->offset =3D 2; - oobregion->length =3D 2; + oobregion->length =3D USER_DATA_SZ - 2; =20 return 0; } From nobody Thu Apr 9 23:25:14 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 352D037CD21 for ; Thu, 5 Mar 2026 10:02:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772704939; cv=none; b=BzqA8pYr/WmaIfN7KIz1qRQs+UGgVmdf55nx3hQHeRNIxzKwvbgSsfM4KlAb24z5Y1sfxpVx/iRah83jgh/gi6Si9xXGu5icY2GJc4OphS5tHXQTaBlAEeelRcB1scBSTozyEfY3Sj/quKO6gI9OzVIyRxBSG7lZt6DmsnYf204= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772704939; c=relaxed/simple; bh=DJAzBHsTjBw4oM+pSBR4bqr3HXDHu7NQIDcmq6+PG/s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MJyysztPW122qCcvhM6W5hY9XojkreLrCtq6qiL5rQyqC0nFjU/tF1Uc0kbvNo9FE7fwM3l/OtWkGABQ6s/CSISVXV04mmAK4Zshk1mqL3qgd5T9n/uS0/mj7UVHiWS2OSRFt+ByNWtpvv8na2iuHwAZDC2xf+F4IJlvBtchtTQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=lBilC751; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="lBilC751" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 256701A2CDC; Thu, 5 Mar 2026 10:02:08 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id EE8F75FDEB; Thu, 5 Mar 2026 10:02:07 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B2B37103683FF; Thu, 5 Mar 2026 11:02:05 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772704927; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=cDyw0VT/gRD0S6ZYgJzuggHzvkdYaJdJvFIQKhQJvv0=; b=lBilC751rjznANkYaxxbdfu4vosOyLn5O8oxsGdjQqYN5hInWOVO2qKi/yggbFucjrpJqB 58SL80VfxsI64nvR+fVgVX0wbKI8mczC+Ra+aPZla98kkxCNPDABwg+PH5H5CMXcWM+E2v qIKZeRILxUCgT6czPcAMSVTHnn/FSyBVS4lZX4PCZnmX9KvtT/Mt7RHxT9S9fhVd9tS1qr Gt94UbJEex9MN51YOAlHidVt18dXo1J4YxWE1V539qh4DvWRHZijn4irJWdXkmorXcClb3 mUGX5w44in3hC4oCDJzXDxiUqHY838U22hoHKFaS77VAV3FLpVwj1Gx8HFjWMQ== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Wentao Liang , Maxime Ripard , Boris Brezillon , Thomas Petazzoni , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v2 2/6] mtd: rawnand: sunxi: fix sunxi_nfc_hw_ecc_read_extra_oob Date: Thu, 5 Mar 2026 11:01:33 +0100 Message-ID: <20260305100137.2558423-3-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260305100137.2558423-1-richard.genoud@bootlin.com> References: <20260305100137.2558423-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" When dumping the OOB, the bytes at the end where actually copied from the beginning of the OOB instead of current_offset. That leads to something like: OOB: ff ff ff ff ff ff ff ff ea 19 00 3a 83 db aa 8d OOB: 99 09 c8 9a 90 36 35 7d aa 15 13 07 3d 97 b2 a4 OOB: a8 bb 19 b3 07 e9 f6 25 52 d7 1a 23 e2 7e 0a e4 OOB: 52 8a 09 d2 1a 86 3d cf b4 99 43 13 d3 90 33 0b OOB: ff ff ff ff ff ff ff ff ea 19 00 3a 83 db aa 8d OOB: 99 09 c8 9a 90 36 35 7d aa 15 13 07 3d 97 b2 a4 OOB: a8 bb 19 b3 07 e9 f6 25 52 d7 1a 23 e2 7e 0a e4 OOB: 52 8a 09 d2 1a 86 3d cf b4 99 43 13 d3 90 33 0b instead of: OOB: ff ff ff ff ff ff ff ff ea 19 00 3a 83 db aa 8d OOB: 99 09 c8 9a 90 36 35 7d aa 15 13 07 3d 97 b2 a4 OOB: a8 bb 19 b3 07 e9 f6 25 52 d7 1a 23 e2 7e 0a e4 OOB: 52 8a 09 d2 1a 86 3d cf b4 99 43 13 d3 90 33 0b OOB: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff (example with BCH16, user data [8,0], no scrambling) *cur_off (offset from the beginning of the page) was compared to offset (offset from the beginning of the OOB), and then, the nand_change_read_column_op() sets the current position to the beginning of the OOB instead of OOB+offset Fixes: 15d6f118285f ("mtd: rawnand: sunxi: Stop supporting ECC_HW_SYNDROME = mode") Reviewed-by: Jernej Skrabec Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 915f1240546f..8af449e548d4 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -1048,9 +1048,9 @@ static void sunxi_nfc_hw_ecc_read_extra_oob(struct na= nd_chip *nand, if (len <=3D 0) return; =20 - if (!cur_off || *cur_off !=3D offset) - nand_change_read_column_op(nand, mtd->writesize, NULL, 0, - false); + if (!cur_off || *cur_off !=3D (offset + mtd->writesize)) + nand_change_read_column_op(nand, mtd->writesize + offset, + NULL, 0, false); =20 if (!randomize) sunxi_nfc_read_buf(nand, oob + offset, len); From nobody Thu Apr 9 23:25:14 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A86D3793DF for ; Thu, 5 Mar 2026 10:02:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772704938; cv=none; b=TWPzU1OMRJk/05VRZ97/IaMIgUGawz2VDkv5x5sya10klSXZvJTDM3IcD6YT/NpAcntr6NWf+fu2s1mTGzmy/DWnp6JHbs3o0Hkbf2stQZXeJZGjCSg4ylMSWIUWxYNhZsoLHXaa16tMi1fJnRSV9fi8azIKZD1ypMbjpaN4gpA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772704938; c=relaxed/simple; bh=JzsspTfi7nLlIjSkc4v1Viy+3rVefLUJ9ySnZdDCcxo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BkEHC67sYNjrF9ckpq18UgYVlBbBGPywy6ALxXIkmso9Ruaokl0VC226G3WtXMOkQ0YSGhLZe/omMXNPtTl77afdf27vd/PWa9MlDOnjv9Mwyu39BUKcEMJhLPEz9tTLlWaaghsPR2GoSYRkor6OayV55VyA+ak50UVAqNt1CpE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=iqXobXzi; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="iqXobXzi" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 28617C40419; Thu, 5 Mar 2026 10:02:28 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id A060D5FDEB; Thu, 5 Mar 2026 10:02:09 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 63BD010369865; Thu, 5 Mar 2026 11:02:07 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772704928; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=EFWtYCwuiTAqb7Iuhvh3esPyqysUJUFJvc16hy8gPX4=; b=iqXobXziyhbydna86VZHaBVfu8irXfP5fDZee0I30F7kKXcfJ6hSBPac2+UjdRn0JEK6Om E/Cpjd/Z3V9MN3btieZCRIi7EoaBpRVAbhH6RWoPixSboFc516gPbqVx9b4VbKbmGRyPLM tAiVC5yIWphevXdQZ47J+UsnsmMnGsbSRxOIB/NQxPOy0Iy4hs2MHkjAq2VLki3falVFDz dZiCM8QNunDfN38dj1SujD2fvZScPzIHNrq1/MMy7pro7Bgu7JDcr9+yhYVIcm17VmkNPk sbDxIPH76BrjMrRnLs4Z0EeXFywE1diLz75JQa2OWh00LafGichJqpI7U4pqrw== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Wentao Liang , Maxime Ripard , Boris Brezillon , Thomas Petazzoni , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v2 3/6] mtd: rawnand: sunxi: do not count BBM bytes twice Date: Thu, 5 Mar 2026 11:01:34 +0100 Message-ID: <20260305100137.2558423-4-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260305100137.2558423-1-richard.genoud@bootlin.com> References: <20260305100137.2558423-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" BBM is part of USER_DATA section, so we should remove it twice This was working ok because we are on the safe size, advertising that there was 2 bytes less available than in reality. But we can't change old platforms, since it may lead to a different ECC strength, so, introduce a legacy flag for old platforms, and switch the new platforms to the correct count. Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 8af449e548d4..d126dc18ef27 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -275,6 +275,8 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @has_ecc_block_512: If the ECC can handle 512B or only 1024B chuncks * @has_ecc_clk: If the controller needs an ECC clock. * @has_mbus_clk: If the controller needs a mbus clock. + * @legacy_max_strength:If the maximize strength function was off by 2 byt= es + * NB: this should not be used in new controllers * @reg_io_data: I/O data register * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register @@ -304,6 +306,7 @@ struct sunxi_nfc_caps { bool has_ecc_block_512; bool has_ecc_clk; bool has_mbus_clk; + bool legacy_max_strength; unsigned int reg_io_data; unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; @@ -1805,10 +1808,22 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_= chip *nand, ecc->size =3D 1024; nsectors =3D mtd->writesize / ecc->size; =20 - /* Reserve 2 bytes for the BBM */ - bytes =3D (mtd->oobsize - 2) / nsectors; + /* + * The 2 BBM bytes should not be removed from the grand total, + * because they are part of the USER_DATA_SZ. + * But we can't modify that for older platform since it may + * result in a stronger ECC at the end, and break the + * compatibility. + */ + if (nfc->caps->legacy_max_strength) + bytes =3D (mtd->oobsize - 2) / nsectors; + else + bytes =3D mtd->oobsize / nsectors; =20 - /* 4 non-ECC bytes are added before each ECC bytes section */ + /* + * USER_DATA_SZ non-ECC bytes are added before each ECC bytes + * section, they contain the 2 BBM bytes + */ bytes -=3D USER_DATA_SZ; =20 /* and bytes has to be even. */ @@ -2373,6 +2388,7 @@ static const u8 sunxi_user_data_len_h6[] =3D { =20 static const struct sunxi_nfc_caps sunxi_nfc_a10_caps =3D { .has_ecc_block_512 =3D true, + .legacy_max_strength =3D true, .reg_io_data =3D NFC_REG_A10_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, @@ -2394,6 +2410,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { static const struct sunxi_nfc_caps sunxi_nfc_a23_caps =3D { .has_mdma =3D true, .has_ecc_block_512 =3D true, + .legacy_max_strength =3D true, .reg_io_data =3D NFC_REG_A23_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, From nobody Thu Apr 9 23:25:14 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29EC537CD50 for ; Thu, 5 Mar 2026 10:02:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772704939; cv=none; b=YYqf1vgyP9lz1o392hjZHoKleCn8so36A3zBH61YzDoAMza+0ll9ho8x4P/NSZA4EPl4r5NbRKPW2UXMct6PPbu/4ysVDeNgN7NaH3kBmxN+0oMey/vevp1U8kbdhPKBzwpbxVe3t5+3kX8rTT7oQrhfv+3wu1PXE6ABh6UXEhU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772704939; c=relaxed/simple; bh=KbWkE0xerrbCBpcn8lkbOUzzTCyNgP404+chNGHcVv8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kzdSxK2OWHNsUildxZX0gyKFjqevEHOdHtJUJS7PQ7Xn64JAM6nzR0YseMg3jpswDYiGwaK4na8arDMR8UM7EdxUXjEMRreulIoFLilUjaeASbQzsnQRu8pFsSigTKct6zxkY9g4xxfIA6JDEaO149XinoudW6ANSBDkSdWkpB4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ue+w5GLA; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ue+w5GLA" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 78FCA4E42575; Thu, 5 Mar 2026 10:02:11 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5053C5FDEB; Thu, 5 Mar 2026 10:02:11 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 04C6E10369782; Thu, 5 Mar 2026 11:02:08 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772704930; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=1UvyLJ/S/s7R/v2QWzX78RjV1H2TGB5loF5BsnWForU=; b=ue+w5GLAg4LDAFO5YzVna2E32vLhpSejLV+0w3WEzh3QePeJMczFzDUMeHp5UxQWeBwPfA a63ic1P9NsA+u1jyry0zIzVZnlkr5t7q9zb9um3ow7VbOvCK6cssAIgafPJ5C4zm0ufnXA ZZx4u8RgdKWgSTDacKsgRhbq7c3LRGHJAMdpuNsZ6xm6TLVIMAlMrYp5wI608XtBG4B0Vh wBgR3GmG7toAXQ40OzBCeQEmEiQA08+UoX+wCCy50SYHtND0+Bw/0vtqGeEwWSrJbxBcZD 9A+rW3t7e/x5/yjt7QcKKKT+rIALqZR65eGTJQuLdCe8jTtMuHw7kDqgyeD6yw== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Wentao Liang , Maxime Ripard , Boris Brezillon , Thomas Petazzoni , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v2 4/6] mtd: rawnand: sunxi: replace hard coded value by a define - take2 Date: Thu, 5 Mar 2026 11:01:35 +0100 Message-ID: <20260305100137.2558423-5-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260305100137.2558423-1-richard.genoud@bootlin.com> References: <20260305100137.2558423-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The user data length (4) has been replaced almost all over the file, but 2 places were forgotten. The user data is placed before the ECC, for each step. So, in sunxi_nfc_hw_ecc_read_extra_oob(), the offset of the user data in OOB is indeed ((ecc->bytes + USER_DATA_SZ) * ecc->steps); And in sunxi_nand_ooblayout_ecc(), the offset of the ECC chunk in OOB is the same offset plus the current user data size: section * (ecc->bytes + USER_DATA_SZ) + USER_DATA_SZ; Reviewed-by: Jernej Skrabec Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index d126dc18ef27..0b0b5349f446 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -1045,7 +1045,7 @@ static void sunxi_nfc_hw_ecc_read_extra_oob(struct na= nd_chip *nand, { struct mtd_info *mtd =3D nand_to_mtd(nand); struct nand_ecc_ctrl *ecc =3D &nand->ecc; - int offset =3D ((ecc->bytes + 4) * ecc->steps); + int offset =3D ((ecc->bytes + USER_DATA_SZ) * ecc->steps); int len =3D mtd->oobsize - offset; =20 if (len <=3D 0) @@ -1741,7 +1741,7 @@ static int sunxi_nand_ooblayout_ecc(struct mtd_info *= mtd, int section, if (section >=3D ecc->steps) return -ERANGE; =20 - oobregion->offset =3D section * (ecc->bytes + USER_DATA_SZ) + 4; + oobregion->offset =3D section * (ecc->bytes + USER_DATA_SZ) + USER_DATA_S= Z; oobregion->length =3D ecc->bytes; =20 return 0; From nobody Thu Apr 9 23:25:14 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B97F37C931 for ; Thu, 5 Mar 2026 10:02:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772704937; cv=none; b=pmHU2FZhOe8aplD19ziw+VCaRVZHUHmodl5cS2OPuvDyMe84qFJg3BjHx8rVJO9HhUTCc1JTLUcYkBaX6+cl8LL8LCO+zoYroKHxYlIz6cUMX/spBltDlSKt2+KaFS3jBlZdXidwFgvz2TqpGXqbsna7IQG6Z0Obt1Bsnp+t5Ss= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772704937; c=relaxed/simple; bh=3+6zQbR+SwjJUYI086wQhSWKl51UvmXsl0Eo6538vzc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bKJ60BjVz/ZOFP7wQHRXIxu3xTxzq/xxhbEKWILJT7wCy+6F5dteltgWyK/JOF4VlNE5VYfBdD57KLpAUUywapEvZ+dtj/XBpUCpfKLlnObli+XdOYaOUk5tqH3epND9wcuru38r8gF+MVf7MGs+IQLX8d9G6x4OZCu21NYx0gw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=1FKBsL23; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="1FKBsL23" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id EC06A1A2CE0; Thu, 5 Mar 2026 10:02:12 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id C197B5FDEB; Thu, 5 Mar 2026 10:02:12 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B965D1036982D; Thu, 5 Mar 2026 11:02:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772704932; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=AnFYOnDz1DIlRxk4/M2buM/Tm1miYn6Fq7SgPCkXfNo=; b=1FKBsL2331inTkV8Kk48WEXXfd459eenaglA6zOhQT1z6Aw1ERp6YTAxSDDXGeThAP2jvq DxnYWDKnPoLZQNtyCql4faC/O2YIkqVplm2KyEEHUTq2OLjqM4QCSEGmFI+/EjADj+MGed q9d1EIL21qlKydBUuBEjRJF+iFx7yhPU7drcLRZTM9uWqLpvQgIfu7HyIzu9t66cENYzUB Y7cv0XR8j90k5h/JLEpw8hhz0fySjPowqyqCB7C2jHu7+wdbel2VsQybv99EgLpLgT1Gbi VqjxliOElOoEbSwqgnvWI3EMcsjO3LF+xOtzh+wcpM84bex36BJbYIt/alY+sg== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Wentao Liang , Maxime Ripard , Boris Brezillon , Thomas Petazzoni , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v2 5/6] mtd: rawnand: sunxi: make the code mode self-explanatory Date: Thu, 5 Mar 2026 11:01:36 +0100 Message-ID: <20260305100137.2558423-6-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260305100137.2558423-1-richard.genoud@bootlin.com> References: <20260305100137.2558423-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" In sunxi_nfc_hw_ecc_{read,write}_chunk(), the ECC step was force to 0, the reason is not trivial to get when reading the code. The explanation is that, from the NAND flash controller perspective, we are indeed at step 0 for user data length and ECC errors. Just add a const value with an explanation to clarify things. Acked-by: Jernej Skrabec Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 0b0b5349f446..ca701c75cec5 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -963,6 +963,8 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip= *nand, u32 pattern_found; bool erased; int ret; + /* From the controller point of view, we are at step 0 */ + const int nfc_step =3D 0; =20 if (*cur_off !=3D data_off) nand_change_read_column_op(nand, data_off, NULL, 0, false); @@ -977,7 +979,7 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip= *nand, return ret; =20 sunxi_nfc_reset_user_data_len(nfc); - sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0); + sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, nfc_step); sunxi_nfc_randomizer_config(nand, page, false); sunxi_nfc_randomizer_enable(nand); writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP, @@ -993,10 +995,9 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chi= p *nand, pattern_found =3D readl(nfc->regs + nfc->caps->reg_pat_found); pattern_found =3D field_get(NFC_ECC_PAT_FOUND_MSK(nfc), pattern_found); =20 - ret =3D sunxi_nfc_hw_ecc_correct(nand, data, oob_required ? oob : NULL, 0, - readl(nfc->regs + NFC_REG_ECC_ST), - pattern_found, - &erased); + ret =3D sunxi_nfc_hw_ecc_correct(nand, data, oob_required ? oob : NULL, + nfc_step, readl(nfc->regs + NFC_REG_ECC_ST), + pattern_found, &erased); if (erased) return 1; =20 @@ -1029,7 +1030,7 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_ch= ip *nand, sunxi_nfc_randomizer_read_buf(nand, oob, ecc->bytes + USER_DATA_SZ, true, page); =20 - sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, 0, + sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, nfc_step, bbm, page); } } @@ -1207,6 +1208,8 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct nand_c= hip *nand, struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); struct nand_ecc_ctrl *ecc =3D &nand->ecc; int ret; + /* From the controller point of view, we are at step 0 */ + const int nfc_step =3D 0; =20 if (data_off !=3D *cur_off) nand_change_write_column_op(nand, data_off, NULL, 0, false); @@ -1223,8 +1226,8 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct nand_c= hip *nand, sunxi_nfc_randomizer_config(nand, page, false); sunxi_nfc_randomizer_enable(nand); sunxi_nfc_reset_user_data_len(nfc); - sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0); - sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, 0, bbm, page); + sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, nfc_step); + sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, nfc_step, bbm, page); =20 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR | NFC_ECC_OP, From nobody Thu Apr 9 23:25:14 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD48C37BE8C for ; Thu, 5 Mar 2026 10:02:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772704939; cv=none; b=lpKUJNJ8BMJzu0trvzWC7PfTdKkkPnBcBnEyaFtX9GCPnLgVh+PTfOa4wicfJSy6OTpTe08dwaKcNfbtpeJR389uCCCibFrcJDQGagR/si0UotY+t3aG+ja1ZrWUOqHuHMnCtciDOl8z5ov4j2EhTeILHQJa4ULv2NY7Y2RT4Ms= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772704939; c=relaxed/simple; bh=wpZFCv+doUQJfQ4HmKOXbnxxcHxST4cjB+GFrexBkDk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=vDRxfLHmPHb4RHcRpMZQssPbZ5zJUGHKfuynVIOAtnOauVqp4Uj++fQ9ltqKy9GnzQpdxfjX9SgQqsULD+bmZl2WzN1IDSxYt2OYAn5dVcpaLhbycT1D9KHHWoJGg3J8zaVFVfL7K+H8drER78rSfIUlorAqBDrpaAjDTBhuRpg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=0PjLMCUH; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="0PjLMCUH" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id D7D53C40410; Thu, 5 Mar 2026 10:02:32 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5A21E5FDEB; Thu, 5 Mar 2026 10:02:14 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 43D91103683FF; Thu, 5 Mar 2026 11:02:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772704933; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=MvGTELR6r/IbA/GTuIxyD6z3TIzHyCHMgbJTsPWBO4A=; b=0PjLMCUHGUZKuU6zee4InzomjA2awglXNA9hOQyg/KFgcVkmZ+lCo3ZCHRrLCEcR0CUmUV PcVYot6tHXtUY4w8fi8ryK2XpypSJd3aj3B7G4L59GLKsYs9G6vHNF20uxrGkDlMWYHMQB QnZQ0p7Iv/9QxIpe6svM55r/Zlg0Dzn00LyGATG4u2L1HAZjGtOJ9Gy42gnQ+/HqnJePZG rasP+JgfLQMJkg8swTeCpyu89Bm0yNLHJ7FFawEhEVffdBTB3NMrA38/JREOEFTDMb8+PN L2YaCUtDtz3+tACXIOCysqhr+uMwoVgS7NtgUb/J1MCfJe1t6vni0I6N8iY/PA== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Wentao Liang , Maxime Ripard , Boris Brezillon , Thomas Petazzoni , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v2 6/6] mtd: rawnand: sunxi: introduce variable user data length Date: Thu, 5 Mar 2026 11:01:37 +0100 Message-ID: <20260305100137.2558423-7-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260305100137.2558423-1-richard.genoud@bootlin.com> References: <20260305100137.2558423-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" In Allwinner SoCs, user data can be added in OOB before each ECC data. For older SoCs like A10, the user data size was the size of a register (4 bytes) and was mandatory before each ECC step. So, the A10 OOB Layout is: [4Bytes USER_DATA_STEP0] [ECC_STEP0 bytes] [4bytes USER_DATA_STEP1] [ECC_STEP1 bytes] ... NB: the BBM is stored at the beginning of the USER_DATA_STEP0. Now, for H6/H616 NAND flash controller, this user data can have a different size for each step. And the vendor has chosen a different layout from the one on A10, using 8 bytes for step 0 and nothing for further steps: [8bytes USER_DATA_STEP0] [ECC_STEP0 bytes] [ECC_STEP1 bytes]... (Still with BBM stored at the beginning of the USER_DATA_STEP0) In order to be compatible with this layout, the current one for H6/H616 has to be changed. Fixes: 88fd4e4deae8 ("mtd: rawnand: sunxi: Add support for H616 nand contro= ller") Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 267 ++++++++++++++++++++++-------- 1 file changed, 201 insertions(+), 66 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index ca701c75cec5..ad4788987b17 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -207,17 +207,6 @@ =20 #define NFC_MAX_CS 7 =20 -/* - * On A10/A23, this is the size of the NDFC User Data Register, containing= the - * mandatory user data bytes following the ECC for each ECC step. - * Thus, for each ECC step, we need the ECC bytes + USER_DATA_SZ. - * Those bits are currently unsused, and kept as default value 0xffffffff. - * - * On H6/H616, this size became configurable, from 0 bytes to 32, via the - * USER_DATA_LEN registers. - */ -#define USER_DATA_SZ 4 - /** * struct sunxi_nand_chip_sel - stores information related to NAND Chip Se= lect * @@ -300,6 +289,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * bytes to write * @nuser_data_tab: Size of @user_data_len_tab * @sram_size: Size of the NAND controller SRAM + * @user_data_len Function returning the user data length for a step */ struct sunxi_nfc_caps { bool has_mdma; @@ -326,6 +316,7 @@ struct sunxi_nfc_caps { unsigned int nuser_data_tab; unsigned int max_ecc_steps; int sram_size; + unsigned int (*user_data_len)(int step); }; =20 /** @@ -824,11 +815,40 @@ static inline u32 sunxi_nfc_buf_to_user_data(const u8= *buf) } =20 static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct nand_chip *nand, u8= *oob, - int step, bool bbm, int page) + int step, bool bbm, int page, + unsigned int user_data_sz) { struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); + u32 user_data; =20 - sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(nfc, step)= ), oob); + if (!nfc->caps->reg_user_data_len) { + /* + * For A10, the user data for step n is in the nth + * REG_USER_DATA + */ + user_data =3D readl(nfc->regs + NFC_REG_USER_DATA(nfc, step)); + sunxi_nfc_user_data_to_buf(user_data, oob); + } else { + /* + * For H6 NAND controller, the user data for all steps is + * contained in 32 user data registers, but not at a specific + * offset for each step, they are just concatenated. + */ + unsigned int user_data_off =3D 0; + unsigned int reg_off; + u8 *ptr =3D oob; + unsigned int i; + + for (i =3D 0; i < step; i++) + user_data_off +=3D nfc->caps->user_data_len(i); + + user_data_off /=3D 4; + for (i =3D 0; i < user_data_sz / 4; i++, ptr +=3D 4) { + reg_off =3D NFC_REG_USER_DATA(nfc, user_data_off + i); + user_data =3D readl(nfc->regs + reg_off); + sunxi_nfc_user_data_to_buf(user_data, ptr); + } + } =20 /* De-randomize the Bad Block Marker. */ if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) @@ -887,17 +907,45 @@ static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struc= t nand_chip *nand, bool bbm, int page) { struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); - u8 user_data[USER_DATA_SZ]; + unsigned int user_data_sz =3D nfc->caps->user_data_len(step); + u8 *user_data =3D NULL; =20 /* Randomize the Bad Block Marker. */ if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) { - memcpy(user_data, oob, sizeof(user_data)); + user_data =3D kmalloc(user_data_sz, GFP_KERNEL); + memcpy(user_data, oob, user_data_sz); sunxi_nfc_randomize_bbm(nand, page, user_data); oob =3D user_data; } =20 - writel(sunxi_nfc_buf_to_user_data(oob), - nfc->regs + NFC_REG_USER_DATA(nfc, step)); + if (!nfc->caps->reg_user_data_len) { + /* + * For A10, the user data for step n is in the nth + * REG_USER_DATA + */ + writel(sunxi_nfc_buf_to_user_data(oob), + nfc->regs + NFC_REG_USER_DATA(nfc, step)); + } else { + /* + * For H6 NAND controller, the user data for all steps is + * contained in 32 user data registers, but not at a specific + * offset for each step, they are just concatenated. + */ + unsigned int user_data_off =3D 0; + const u8 *ptr =3D oob; + unsigned int i; + + for (i =3D 0; i < step; i++) + user_data_off +=3D nfc->caps->user_data_len(i); + + user_data_off /=3D 4; + for (i =3D 0; i < user_data_sz / 4; i++, ptr +=3D 4) { + writel(sunxi_nfc_buf_to_user_data(ptr), + nfc->regs + NFC_REG_USER_DATA(nfc, user_data_off + i)); + } + } + + kfree(user_data); } =20 static void sunxi_nfc_hw_ecc_update_stats(struct nand_chip *nand, @@ -918,6 +966,7 @@ static int sunxi_nfc_hw_ecc_correct(struct nand_chip *n= and, u8 *data, u8 *oob, bool *erased) { struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); + unsigned int user_data_sz =3D nfc->caps->user_data_len(step); struct nand_ecc_ctrl *ecc =3D &nand->ecc; u32 tmp; =20 @@ -940,7 +989,7 @@ static int sunxi_nfc_hw_ecc_correct(struct nand_chip *n= and, u8 *data, u8 *oob, memset(data, pattern, ecc->size); =20 if (oob) - memset(oob, pattern, ecc->bytes + USER_DATA_SZ); + memset(oob, pattern, ecc->bytes + user_data_sz); =20 return 0; } @@ -955,12 +1004,14 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_c= hip *nand, u8 *oob, int oob_off, int *cur_off, unsigned int *max_bitflips, - bool bbm, bool oob_required, int page) + int step, bool oob_required, int page) { struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); + unsigned int user_data_sz =3D nfc->caps->user_data_len(step); struct nand_ecc_ctrl *ecc =3D &nand->ecc; int raw_mode =3D 0; u32 pattern_found; + bool bbm =3D !step; bool erased; int ret; /* From the controller point of view, we are at step 0 */ @@ -978,8 +1029,7 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chi= p *nand, if (ret) return ret; =20 - sunxi_nfc_reset_user_data_len(nfc); - sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, nfc_step); + sunxi_nfc_set_user_data_len(nfc, user_data_sz, nfc_step); sunxi_nfc_randomizer_config(nand, page, false); sunxi_nfc_randomizer_enable(nand); writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP, @@ -990,7 +1040,7 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chi= p *nand, if (ret) return ret; =20 - *cur_off =3D oob_off + ecc->bytes + USER_DATA_SZ; + *cur_off =3D oob_off + ecc->bytes + user_data_sz; =20 pattern_found =3D readl(nfc->regs + nfc->caps->reg_pat_found); pattern_found =3D field_get(NFC_ECC_PAT_FOUND_MSK(nfc), pattern_found); @@ -1014,10 +1064,10 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_= chip *nand, ecc->size); =20 nand_change_read_column_op(nand, oob_off, oob, - ecc->bytes + USER_DATA_SZ, false); + ecc->bytes + user_data_sz, false); =20 ret =3D nand_check_erased_ecc_chunk(data, ecc->size, oob, - ecc->bytes + USER_DATA_SZ, + ecc->bytes + user_data_sz, NULL, 0, ecc->strength); if (ret >=3D 0) raw_mode =3D 1; @@ -1027,11 +1077,11 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_= chip *nand, if (oob_required) { nand_change_read_column_op(nand, oob_off, NULL, 0, false); - sunxi_nfc_randomizer_read_buf(nand, oob, ecc->bytes + USER_DATA_SZ, + sunxi_nfc_randomizer_read_buf(nand, oob, ecc->bytes + user_data_sz, true, page); =20 sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, nfc_step, - bbm, page); + bbm, page, user_data_sz); } } =20 @@ -1040,13 +1090,41 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_= chip *nand, return raw_mode; } =20 +/* + * Returns the offset of the OOB for each step. + * (it includes the user data before the ECC data.) + */ +static int sunxi_get_oob_offset(struct sunxi_nfc *nfc, + struct nand_ecc_ctrl *ecc, int step) +{ + int ecc_off =3D step * ecc->bytes; + int i; + + for (i =3D 0; i < step; i++) + ecc_off +=3D nfc->caps->user_data_len(i); + + return ecc_off; +} + +/* + * Returns the offset of the ECC for each step. + * So, it's the same as sunxi_get_oob_offset(), + * but it skips the next user data. + */ +static int sunxi_get_ecc_offset(struct sunxi_nfc *nfc, + struct nand_ecc_ctrl *ecc, int step) +{ + return sunxi_get_oob_offset(nfc, ecc, step) + nfc->caps->user_data_len(st= ep); +} + static void sunxi_nfc_hw_ecc_read_extra_oob(struct nand_chip *nand, u8 *oob, int *cur_off, bool randomize, int page) { + struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); struct mtd_info *mtd =3D nand_to_mtd(nand); struct nand_ecc_ctrl *ecc =3D &nand->ecc; - int offset =3D ((ecc->bytes + USER_DATA_SZ) * ecc->steps); + int offset =3D sunxi_get_oob_offset(nfc, ecc, ecc->steps); int len =3D mtd->oobsize - offset; =20 if (len <=3D 0) @@ -1090,7 +1168,8 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct na= nd_chip *nand, uint8_t *buf =20 sunxi_nfc_hw_ecc_enable(nand); sunxi_nfc_reset_user_data_len(nfc); - sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0); + for (i =3D 0; i < nchunks; i++) + sunxi_nfc_set_user_data_len(nfc, nfc->caps->user_data_len(i), i); sunxi_nfc_randomizer_config(nand, page, false); sunxi_nfc_randomizer_enable(nand); =20 @@ -1125,7 +1204,8 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct na= nd_chip *nand, uint8_t *buf =20 for (i =3D 0; i < nchunks; i++) { int data_off =3D i * ecc->size; - int oob_off =3D i * (ecc->bytes + USER_DATA_SZ); + unsigned int user_data_sz =3D nfc->caps->user_data_len(i); + int oob_off =3D sunxi_get_oob_offset(nfc, ecc, i); u8 *data =3D buf + data_off; u8 *oob =3D nand->oob_poi + oob_off; bool erased; @@ -1143,10 +1223,10 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct = nand_chip *nand, uint8_t *buf /* TODO: use DMA to retrieve OOB */ nand_change_read_column_op(nand, mtd->writesize + oob_off, - oob, ecc->bytes + USER_DATA_SZ, false); + oob, ecc->bytes + user_data_sz, false); =20 - sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, i, - !i, page); + sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, i, !i, + page, user_data_sz); } =20 if (erased) @@ -1158,7 +1238,8 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct na= nd_chip *nand, uint8_t *buf if (status & NFC_ECC_ERR_MSK(nfc)) { for (i =3D 0; i < nchunks; i++) { int data_off =3D i * ecc->size; - int oob_off =3D i * (ecc->bytes + USER_DATA_SZ); + unsigned int user_data_sz =3D nfc->caps->user_data_len(i); + int oob_off =3D sunxi_get_oob_offset(nfc, ecc, i); u8 *data =3D buf + data_off; u8 *oob =3D nand->oob_poi + oob_off; =20 @@ -1178,10 +1259,10 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct = nand_chip *nand, uint8_t *buf /* TODO: use DMA to retrieve OOB */ nand_change_read_column_op(nand, mtd->writesize + oob_off, - oob, ecc->bytes + USER_DATA_SZ, false); + oob, ecc->bytes + user_data_sz, false); =20 ret =3D nand_check_erased_ecc_chunk(data, ecc->size, oob, - ecc->bytes + USER_DATA_SZ, + ecc->bytes + user_data_sz, NULL, 0, ecc->strength); if (ret >=3D 0) @@ -1202,11 +1283,13 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct = nand_chip *nand, uint8_t *buf static int sunxi_nfc_hw_ecc_write_chunk(struct nand_chip *nand, const u8 *data, int data_off, const u8 *oob, int oob_off, - int *cur_off, bool bbm, + int *cur_off, int step, int page) { struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); + unsigned int user_data_sz =3D nfc->caps->user_data_len(step); struct nand_ecc_ctrl *ecc =3D &nand->ecc; + bool bbm =3D !step; int ret; /* From the controller point of view, we are at step 0 */ const int nfc_step =3D 0; @@ -1225,8 +1308,7 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct nand_c= hip *nand, =20 sunxi_nfc_randomizer_config(nand, page, false); sunxi_nfc_randomizer_enable(nand); - sunxi_nfc_reset_user_data_len(nfc); - sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, nfc_step); + sunxi_nfc_set_user_data_len(nfc, user_data_sz, nfc_step); sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, nfc_step, bbm, page); =20 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | @@ -1238,7 +1320,7 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct nand_c= hip *nand, if (ret) return ret; =20 - *cur_off =3D oob_off + ecc->bytes + USER_DATA_SZ; + *cur_off =3D oob_off + ecc->bytes + user_data_sz; =20 return 0; } @@ -1249,7 +1331,8 @@ static void sunxi_nfc_hw_ecc_write_extra_oob(struct n= and_chip *nand, { struct mtd_info *mtd =3D nand_to_mtd(nand); struct nand_ecc_ctrl *ecc =3D &nand->ecc; - int offset =3D ((ecc->bytes + USER_DATA_SZ) * ecc->steps); + struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); + int offset =3D sunxi_get_oob_offset(nfc, ecc, ecc->steps); int len =3D mtd->oobsize - offset; =20 if (len <=3D 0) @@ -1268,6 +1351,7 @@ static void sunxi_nfc_hw_ecc_write_extra_oob(struct n= and_chip *nand, static int sunxi_nfc_hw_ecc_read_page(struct nand_chip *nand, uint8_t *buf, int oob_required, int page) { + struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); struct mtd_info *mtd =3D nand_to_mtd(nand); struct nand_ecc_ctrl *ecc =3D &nand->ecc; unsigned int max_bitflips =3D 0; @@ -1280,16 +1364,17 @@ static int sunxi_nfc_hw_ecc_read_page(struct nand_c= hip *nand, uint8_t *buf, =20 sunxi_nfc_hw_ecc_enable(nand); =20 + sunxi_nfc_reset_user_data_len(nfc); for (i =3D 0; i < ecc->steps; i++) { int data_off =3D i * ecc->size; - int oob_off =3D i * (ecc->bytes + USER_DATA_SZ); + int oob_off =3D sunxi_get_oob_offset(nfc, ecc, i); u8 *data =3D buf + data_off; u8 *oob =3D nand->oob_poi + oob_off; =20 ret =3D sunxi_nfc_hw_ecc_read_chunk(nand, data, data_off, oob, oob_off + mtd->writesize, &cur_off, &max_bitflips, - !i, oob_required, page); + i, oob_required, page); if (ret < 0) return ret; else if (ret) @@ -1327,6 +1412,7 @@ static int sunxi_nfc_hw_ecc_read_subpage(struct nand_= chip *nand, u32 data_offs, u32 readlen, u8 *bufpoi, int page) { + struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); struct mtd_info *mtd =3D nand_to_mtd(nand); struct nand_ecc_ctrl *ecc =3D &nand->ecc; int ret, i, cur_off =3D 0; @@ -1338,17 +1424,18 @@ static int sunxi_nfc_hw_ecc_read_subpage(struct nan= d_chip *nand, =20 sunxi_nfc_hw_ecc_enable(nand); =20 + sunxi_nfc_reset_user_data_len(nfc); for (i =3D data_offs / ecc->size; i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) { int data_off =3D i * ecc->size; - int oob_off =3D i * (ecc->bytes + USER_DATA_SZ); + int oob_off =3D sunxi_get_oob_offset(nfc, ecc, i); u8 *data =3D bufpoi + data_off; u8 *oob =3D nand->oob_poi + oob_off; =20 ret =3D sunxi_nfc_hw_ecc_read_chunk(nand, data, data_off, oob, oob_off + mtd->writesize, - &cur_off, &max_bitflips, !i, + &cur_off, &max_bitflips, i, false, page); if (ret < 0) return ret; @@ -1383,6 +1470,7 @@ static int sunxi_nfc_hw_ecc_write_page(struct nand_ch= ip *nand, const uint8_t *buf, int oob_required, int page) { + struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); struct mtd_info *mtd =3D nand_to_mtd(nand); struct nand_ecc_ctrl *ecc =3D &nand->ecc; int ret, i, cur_off =3D 0; @@ -1393,15 +1481,16 @@ static int sunxi_nfc_hw_ecc_write_page(struct nand_= chip *nand, =20 sunxi_nfc_hw_ecc_enable(nand); =20 + sunxi_nfc_reset_user_data_len(nfc); for (i =3D 0; i < ecc->steps; i++) { int data_off =3D i * ecc->size; - int oob_off =3D i * (ecc->bytes + USER_DATA_SZ); + int oob_off =3D sunxi_get_oob_offset(nfc, ecc, i); const u8 *data =3D buf + data_off; const u8 *oob =3D nand->oob_poi + oob_off; =20 ret =3D sunxi_nfc_hw_ecc_write_chunk(nand, data, data_off, oob, oob_off + mtd->writesize, - &cur_off, !i, page); + &cur_off, i, page); if (ret) return ret; } @@ -1420,6 +1509,7 @@ static int sunxi_nfc_hw_ecc_write_subpage(struct nand= _chip *nand, const u8 *buf, int oob_required, int page) { + struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); struct mtd_info *mtd =3D nand_to_mtd(nand); struct nand_ecc_ctrl *ecc =3D &nand->ecc; int ret, i, cur_off =3D 0; @@ -1430,16 +1520,17 @@ static int sunxi_nfc_hw_ecc_write_subpage(struct na= nd_chip *nand, =20 sunxi_nfc_hw_ecc_enable(nand); =20 + sunxi_nfc_reset_user_data_len(nfc); for (i =3D data_offs / ecc->size; i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) { int data_off =3D i * ecc->size; - int oob_off =3D i * (ecc->bytes + USER_DATA_SZ); + int oob_off =3D sunxi_get_oob_offset(nfc, ecc, i); const u8 *data =3D buf + data_off; const u8 *oob =3D nand->oob_poi + oob_off; =20 ret =3D sunxi_nfc_hw_ecc_write_chunk(nand, data, data_off, oob, oob_off + mtd->writesize, - &cur_off, !i, page); + &cur_off, i, page); if (ret) return ret; } @@ -1473,10 +1564,12 @@ static int sunxi_nfc_hw_ecc_write_page_dma(struct n= and_chip *nand, =20 sunxi_nfc_reset_user_data_len(nfc); for (i =3D 0; i < ecc->steps; i++) { - const u8 *oob =3D nand->oob_poi + (i * (ecc->bytes + USER_DATA_SZ)); + unsigned int user_data_sz =3D nfc->caps->user_data_len(i); + int oob_off =3D sunxi_get_oob_offset(nfc, ecc, i); + const u8 *oob =3D nand->oob_poi + oob_off; =20 sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, i, !i, page); - sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, i); + sunxi_nfc_set_user_data_len(nfc, user_data_sz, i); } =20 nand_prog_page_begin_op(nand, page, 0, NULL, 0); @@ -1740,11 +1833,12 @@ static int sunxi_nand_ooblayout_ecc(struct mtd_info= *mtd, int section, { struct nand_chip *nand =3D mtd_to_nand(mtd); struct nand_ecc_ctrl *ecc =3D &nand->ecc; + struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); =20 if (section >=3D ecc->steps) return -ERANGE; =20 - oobregion->offset =3D section * (ecc->bytes + USER_DATA_SZ) + USER_DATA_S= Z; + oobregion->offset =3D sunxi_get_ecc_offset(nfc, ecc, section); oobregion->length =3D ecc->bytes; =20 return 0; @@ -1755,18 +1849,20 @@ static int sunxi_nand_ooblayout_free(struct mtd_inf= o *mtd, int section, { struct nand_chip *nand =3D mtd_to_nand(mtd); struct nand_ecc_ctrl *ecc =3D &nand->ecc; + struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); + unsigned int user_data_sz =3D nfc->caps->user_data_len(section); =20 if (section > ecc->steps) return -ERANGE; =20 /* * The first 2 bytes are used for BB markers, hence we - * only have USER_DATA_SZ - 2 bytes available in the first user data + * only have user_data_sz - 2 bytes available in the first user data * section. */ if (!section && ecc->engine_type =3D=3D NAND_ECC_ENGINE_TYPE_ON_HOST) { oobregion->offset =3D 2; - oobregion->length =3D USER_DATA_SZ - 2; + oobregion->length =3D user_data_sz - 2; =20 return 0; } @@ -1778,10 +1874,10 @@ static int sunxi_nand_ooblayout_free(struct mtd_inf= o *mtd, int section, if (section =3D=3D ecc->steps && ecc->engine_type =3D=3D NAND_ECC_ENGINE_= TYPE_ON_HOST) return -ERANGE; =20 - oobregion->offset =3D section * (ecc->bytes + USER_DATA_SZ); + oobregion->offset =3D sunxi_get_ecc_offset(nfc, ecc, section); =20 if (section < ecc->steps) - oobregion->length =3D USER_DATA_SZ; + oobregion->length =3D user_data_sz; else oobregion->length =3D mtd->oobsize - oobregion->offset; =20 @@ -1802,14 +1898,18 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_= chip *nand, const u8 *strengths =3D nfc->caps->ecc_strengths; struct mtd_info *mtd =3D nand_to_mtd(nand); struct nand_device *nanddev =3D mtd_to_nanddev(mtd); + int total_user_data_sz =3D 0; int nsectors; int i; =20 - if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) { - int bytes; + ecc->size =3D 1024; + nsectors =3D mtd->writesize / ecc->size; =20 - ecc->size =3D 1024; - nsectors =3D mtd->writesize / ecc->size; + for (i =3D 0; i < nsectors; i++) + total_user_data_sz +=3D nfc->caps->user_data_len(i); + + if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) { + int bytes =3D mtd->oobsize; =20 /* * The 2 BBM bytes should not be removed from the grand total, @@ -1819,15 +1919,15 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_= chip *nand, * compatibility. */ if (nfc->caps->legacy_max_strength) - bytes =3D (mtd->oobsize - 2) / nsectors; - else - bytes =3D mtd->oobsize / nsectors; + bytes -=3D 2; + + bytes -=3D total_user_data_sz; =20 /* - * USER_DATA_SZ non-ECC bytes are added before each ECC bytes - * section, they contain the 2 BBM bytes + * Once all user data has been subtracted, the rest can be used + * for ECC bytes */ - bytes -=3D USER_DATA_SZ; + bytes /=3D nsectors; =20 /* and bytes has to be even. */ if (bytes % 2) @@ -1880,7 +1980,7 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_ch= ip *nand, =20 nsectors =3D mtd->writesize / ecc->size; =20 - if (mtd->oobsize < ((ecc->bytes + USER_DATA_SZ) * nsectors)) + if (mtd->oobsize < (ecc->bytes * nsectors + total_user_data_sz)) return -EINVAL; =20 ecc->read_oob =3D sunxi_nfc_hw_ecc_read_oob; @@ -2377,6 +2477,38 @@ static void sunxi_nfc_remove(struct platform_device = *pdev) dma_release_channel(nfc->dmac); } =20 +static unsigned int sunxi_user_data_len_h616(int step) +{ + /* + * On H6/H616, the user data size became configurable, + * from 0 bytes to 32, via the USER_DATA_LEN registers. + * + * In H616 vendor image, the user data length is 8 byte on step 0 + * (that includes the BBM) and 0 bytes for the rest. + * So the OOB layout is: + * [BBM] [BBM] [6bytes USER_DATA_STEP0] [ECC_STEP0 bytes] [ECC_STEP1 byte= s]... + */ + if (step =3D=3D 0) + return 8; + return 0; +} + +static unsigned int sunxi_user_data_len_a10(int step) +{ + /* + * On A10/A23, this is the size of the NDFC User Data Register, + * containing the mandatory user data bytes preceding the ECC for each + * ECC step (and including the BBM) + * Thus, for each ECC step, we need USER_DATA_SZ + ECC bytes. + * + * So the layout is: + * [BBM] [BBM] [2Bytes USER_DATA_STEP0] [ECC_STEP0 bytes] + * [4bytes USER_DATA_STEP1] [ECC_step1 bytes]... + */ + + return 4; +} + static const u8 sunxi_ecc_strengths_a10[] =3D { 16, 24, 28, 32, 40, 48, 56, 60, 64 }; @@ -2408,6 +2540,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), .max_ecc_steps =3D 16, .sram_size =3D 1024, + .user_data_len =3D &sunxi_user_data_len_a10, }; =20 static const struct sunxi_nfc_caps sunxi_nfc_a23_caps =3D { @@ -2430,6 +2563,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), .max_ecc_steps =3D 16, .sram_size =3D 1024, + .user_data_len =3D &sunxi_user_data_len_a10, }; =20 static const struct sunxi_nfc_caps sunxi_nfc_h616_caps =3D { @@ -2454,6 +2588,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_h616_cap= s =3D { .nuser_data_tab =3D ARRAY_SIZE(sunxi_user_data_len_h6), .max_ecc_steps =3D 32, .sram_size =3D 8192, + .user_data_len =3D &sunxi_user_data_len_h616, }; =20 static const struct of_device_id sunxi_nfc_ids[] =3D {