From nobody Sun Apr 5 13:04:58 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCBD8378D70 for ; Thu, 5 Mar 2026 09:20:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772702436; cv=none; b=ke0RjFYzG3IiEoLA5NxobnYTiJw2bqugFm7x4LeOp/uKHOTjgLD2ghZB780zV8eCj07zPRHhMhcYji4Sw4AZlgvnw+/tQwTWV8U/TKM7Mx8OAz1+OX4I9uZ+49+oqHrV0b7MByRFzWgT+HOqZdnf7awoKWUjn+A17+kr2MkAx2w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772702436; c=relaxed/simple; bh=ccFBjF/h8va7hVwllGTVGR1Ya7n+6b8hVuozzzTpGYo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LXkSdube39qgL4KVgTWAI9K48vFDKHkCvbTr1gB7lHKMA7JkpiT0sPCWbJEoW88KgxXcN7fAsqp9b12teXwANf3anWZFFgOV7V8SJ4pKcs0KE+bvw865kd2yN/x4xpEBDRIDRc5t72lXnQE7BK6b0nkSMplQkbTPQKdtnIvXWso= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=v4UrZIht; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="v4UrZIht" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 87FB31A2CD8; Thu, 5 Mar 2026 09:20:33 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5DF935FDEB; Thu, 5 Mar 2026 09:20:33 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D807C1036984A; Thu, 5 Mar 2026 10:20:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772702431; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=o7thUj1C+8yEK0Fw3YtleNg2pFyzAQb0ZErKMz2sR4s=; b=v4UrZIhtXiVeHJCZwM6PdQQg65XRhfWodJuE/SU1rJC5ZxKbj2A4LPo9Zy2S4Ud85qYHLY Ye+NhvLXdVvT/6D2svH2oBJ/TP9IX2KF7/S5qE9BakDNvRlZHRWTqVqw/ATzji0olqrZ8a hYW8wR15eFLiLpldB11CTS47hrdTQKkksRxfamPI7M+iiFlC4WS6t28j0UwrFCjHRje6WQ 58/3c7G5yegzVt22W8rpeG523JTM5ifgv+XmJQjA7oRb3KoNAEE31S2D+x2qEvz+ej9kSx BzaixTgOYKwQDoJbnlGMNwc/spVyVc7dxP/Z3mgN+C5X3jPMb8mzt+E3589/Og== From: Richard Genoud To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel Cc: Paul Kocialkowski , Thomas Petazzoni , John Stultz , Joao Schim , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v4 3/4] arm64: dts: allwinner: h616: add PWM controller Date: Thu, 5 Mar 2026 10:19:58 +0100 Message-ID: <20260305091959.2530374-4-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260305091959.2530374-1-richard.genoud@bootlin.com> References: <20260305091959.2530374-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The H616 has a PWM controller that can provide PWM signals, but also plain clocks. Add the PWM controller node and pins in the device tree. Tested-by: John Stultz Signed-off-by: Richard Genoud --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-h616.dtsi index 8d1110c14bad..1c7628a6e4bb 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -236,6 +236,17 @@ watchdog: watchdog@30090a0 { clocks =3D <&osc24M>; }; =20 + pwm: pwm@300a000 { + compatible =3D "allwinner,sun50i-h616-pwm"; + reg =3D <0x0300a000 0x400>; + clocks =3D <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names =3D "mod", "bus"; + resets =3D <&ccu RST_BUS_PWM>; + #pwm-cells =3D <3>; + #clock-cells =3D <1>; + status =3D "disabled"; + }; + pio: pinctrl@300b000 { compatible =3D "allwinner,sun50i-h616-pinctrl"; reg =3D <0x0300b000 0x400>; @@ -340,6 +351,42 @@ nand_rb1_pin: nand-rb1-pin { bias-pull-up; }; =20 + /omit-if-no-ref/ + pwm0_pin: pwm0-pin { + pins =3D "PD28"; + function =3D "pwm0"; + }; + + /omit-if-no-ref/ + pwm1_pin: pwm1-pin { + pins =3D "PG19"; + function =3D "pwm1"; + }; + + /omit-if-no-ref/ + pwm2_pin: pwm2-pin { + pins =3D "PH2"; + function =3D "pwm2"; + }; + + /omit-if-no-ref/ + pwm3_pin: pwm3-pin { + pins =3D "PH0"; + function =3D "pwm3"; + }; + + /omit-if-no-ref/ + pwm4_pin: pwm4-pin { + pins =3D "PI14"; + function =3D "pwm4"; + }; + + /omit-if-no-ref/ + pwm5_pin: pwm5-pin { + pins =3D "PA12"; + function =3D "pwm5"; + }; + /omit-if-no-ref/ spi0_pins: spi0-pins { pins =3D "PC0", "PC2", "PC4";