From nobody Thu Apr 2 20:15:41 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27BF934D905; Thu, 26 Mar 2026 23:10:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774566602; cv=none; b=KstKr4IQnt7//Yx+eIVB/0Nno9/UqFIff3NLtON9I/y+fmIJnbPjBfkxOlK1AGBmh1R2iuAQBmOnC+veLtmEn9cqtjCkEDxcYviA4Ly94EjScFwvZyCaQgdyu/jWUBfkOYKHMyOPuJGW9niiiOXJ6yZ5dmAKsKcA5hxgxJrjW6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774566602; c=relaxed/simple; bh=eXpDdX/kQyDxNpLURS993lHyshWENbFjP5/yo5InZe4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Q+2I0DQ2zTViQkU8DzN83qCqzWeikg/DW4C4xv5I1q+NEKObIovzdj0/hevAJYe+sjGVi0ZCX1fNtskaUjkMDTCitfPCLazgXh9ErKgnNL46nCK3Xh16LCECMBM5BVPPHl+zu7iy9V08MyUG/mFBd/i/EjgT/BahRp3egpdBQqU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U8j48vEi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U8j48vEi" Received: by smtp.kernel.org (Postfix) with ESMTPS id E6FBEC2BCB4; Thu, 26 Mar 2026 23:10:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774566602; bh=eXpDdX/kQyDxNpLURS993lHyshWENbFjP5/yo5InZe4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=U8j48vEia8OjUp9LJq/MlCNJCdJon3/xmeEvf+74B8Hq5o1hW/QG3ACPTmS468Hgo ukZVEUBI2WdbjokSO47YGQU/vynYd/w8LwVAk+BWM19EiRnuh01eETTYf9BK9tgynL 31QocxATuaV1ADYV2qSNawXzcdEOQKPgRIGy7W4/s/Jzk//g47Kq9bsN076AHg+cnJ /urkgT9ziKviTxtqURsk1bQZXH3OMzgMBOL5GQkB71oLk3FJHs8w2ThrbHJ/2kCSmS q3zB0fhUtq65GIj+cGASFu5NOxAfTslOJybvJwThQWlBlC286mgiM/5YmwhXcn99uX 9/YU7Pv6uDHNQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD1A310AB832; Thu, 26 Mar 2026 23:10:01 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Fri, 27 Mar 2026 00:10:01 +0100 Subject: [PATCH v4 2/2] arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-rk3588-csi2rx-v4-2-81c6bcfefa63@collabora.com> References: <20260305-rk3588-csi2rx-v4-0-81c6bcfefa63@collabora.com> In-Reply-To: <20260305-rk3588-csi2rx-v4-0-81c6bcfefa63@collabora.com> To: Mauro Carvalho Chehab , Sakari Ailus , Laurent Pinchart , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Collabora Kernel Team Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774566600; l=2503; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=eOx/3+fLG0p1riU9lvyNxwYlp2uG1DyRr96Nkcj8cCQ=; b=WX8zJtXNZ2DzUtXeA4tPKCgGn9gURRKTTXJy4EnZHg02/gU9BpDfUKzEmvJ4l0W7muZvZiFXu nIM6waggZduCn/3ByzcK3qGtRpHGJjluQE3BqKaqqQ7XtxQT4YG1KZK X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 features six MIPI CSI-2 receiver units: - MIPI0: connected to MIPI DCPHY0 (not supported) - MIPI1: connected to MIPI DCPHY1 (not supported) - MIPI2: connected to MIPI DPHY0 - MIPI3: connected to MIPI DPHY0-1 (not supported) - MIPI4: connected to MIPI DPHY1 - MIPI5: connected to MIPI DPHY1-1 (not supported) As the MIPI DCPHYs as well as the split DPHY mode of the DPHYs are not yet supported, add only the device tree nodes for the MIPI2 and MIPI4 units. Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 52 +++++++++++++++++++++++= ++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 7fe9593d8c19..6c593b0255c3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1430,6 +1430,58 @@ av1d: video-codec@fdc70000 { resets =3D <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, = <&cru SRST_P_AV1_BIU>; }; =20 + csi2: csi@fdd30000 { + compatible =3D "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg =3D <0x0 0xfdd30000 0x0 0x10000>; + interrupts =3D , + ; + interrupt-names =3D "err1", "err2"; + clocks =3D <&cru PCLK_CSI_HOST_2>; + phys =3D <&csi_dphy0>; + power-domains =3D <&power RK3588_PD_VI>; + resets =3D <&cru SRST_P_CSI_HOST_2>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi2_in: port@0 { + reg =3D <0>; + }; + + csi2_out: port@1 { + reg =3D <1>; + }; + }; + }; + + csi4: csi@fdd50000 { + compatible =3D "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg =3D <0x0 0xfdd50000 0x0 0x10000>; + interrupts =3D , + ; + interrupt-names =3D "err1", "err2"; + clocks =3D <&cru PCLK_CSI_HOST_4>; + phys =3D <&csi_dphy1>; + power-domains =3D <&power RK3588_PD_VI>; + resets =3D <&cru SRST_P_CSI_HOST_4>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi4_in: port@0 { + reg =3D <0>; + }; + + csi4_out: port@1 { + reg =3D <1>; + }; + }; + }; + vop: vop@fdd90000 { compatible =3D "rockchip,rk3588-vop"; reg =3D <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; --=20 2.39.5