From nobody Tue Apr 7 12:55:32 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EA8934107F; Fri, 13 Mar 2026 11:08:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773400127; cv=none; b=fOQetWPJzuvEIoo8f6o/5OQGMNZGp4uFgDUNykbqVe5ubdZ3HCStLNZYi4gJqY4WD53SAhflaOSTT/FiFl0fdRt/adifwmOJ06IjzmbxXR+06YQj0CNTOM/TqkIE9po25CXS+ZSh7YD7L9sQiJb0/UMuxMtN0/rK+wXWLBjJpgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773400127; c=relaxed/simple; bh=eXpDdX/kQyDxNpLURS993lHyshWENbFjP5/yo5InZe4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MgRyqlTkdlKMPtwebsmWDgu5IOUGkF0Omc9gB9Hahqy8sKg54NKVZB3n2iYxHfLDXDocqQE25SPG7P/dvU5YRhgTuoUNmP4SumGX0NSLeJSLHQKeE8s0NCb6s1zTHBd0Sd/QtAmipgkehp4u8gTfp+L7+OVEsCQ8NegXFChdczA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dIw/Jz8v; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dIw/Jz8v" Received: by smtp.kernel.org (Postfix) with ESMTPS id 130B9C2BCB0; Fri, 13 Mar 2026 11:08:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773400127; bh=eXpDdX/kQyDxNpLURS993lHyshWENbFjP5/yo5InZe4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=dIw/Jz8vkWHaZ03tSMACJ28koZon8C9jZBYEtu3vvb2pGrszXb+zEWlPwfoMkHeqx Q8FcQPko2TaQqoVVC2Rt7zwW2dA5jwBPjhPmDcMlyoW68R9O+QUmrOVvtDfxTTCa74 MCYqznGBwf7+FoGX+yM2bkSM2Xu0RJ25XzA224KDQjMfc9vtemNMdnycRKyohM+Lfz KjKodbFhGmi/PLUPH6VKefAKzXO3q/LkyJJGKTImwksx3vJuQWwnVeh7cBa64xwF4i GCl7CtlU3lQ+ESTE41uCbDmV6ar6iQnCUdK3NS4mlQDTL5H2/yxtPCil6j8EOOWWyA vGQEMjpa66ipA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0108105F79B; Fri, 13 Mar 2026 11:08:46 +0000 (UTC) From: Michael Riesch via B4 Relay Date: Fri, 13 Mar 2026 12:08:46 +0100 Subject: [PATCH v2 2/2] arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-rk3588-csi2rx-v2-2-79d01b615486@collabora.com> References: <20260305-rk3588-csi2rx-v2-0-79d01b615486@collabora.com> In-Reply-To: <20260305-rk3588-csi2rx-v2-0-79d01b615486@collabora.com> To: Mauro Carvalho Chehab , Sakari Ailus , Laurent Pinchart , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Collabora Kernel Team Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773400125; l=2503; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=eOx/3+fLG0p1riU9lvyNxwYlp2uG1DyRr96Nkcj8cCQ=; b=BshxsPW1Cibi+TDccRt2CIth6qAE8y4UFkVD+cyVxXflClu9NLb4WcRYg42f68HGU7OWTkgsG bM4kOo8w75FAe3pq42OMJPJ1+IQCzI9sjUGtcKUufwktx3/ClQSEmNH X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com From: Michael Riesch The Rockchip RK3588 features six MIPI CSI-2 receiver units: - MIPI0: connected to MIPI DCPHY0 (not supported) - MIPI1: connected to MIPI DCPHY1 (not supported) - MIPI2: connected to MIPI DPHY0 - MIPI3: connected to MIPI DPHY0-1 (not supported) - MIPI4: connected to MIPI DPHY1 - MIPI5: connected to MIPI DPHY1-1 (not supported) As the MIPI DCPHYs as well as the split DPHY mode of the DPHYs are not yet supported, add only the device tree nodes for the MIPI2 and MIPI4 units. Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 52 +++++++++++++++++++++++= ++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 7fe9593d8c19..6c593b0255c3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1430,6 +1430,58 @@ av1d: video-codec@fdc70000 { resets =3D <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, = <&cru SRST_P_AV1_BIU>; }; =20 + csi2: csi@fdd30000 { + compatible =3D "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg =3D <0x0 0xfdd30000 0x0 0x10000>; + interrupts =3D , + ; + interrupt-names =3D "err1", "err2"; + clocks =3D <&cru PCLK_CSI_HOST_2>; + phys =3D <&csi_dphy0>; + power-domains =3D <&power RK3588_PD_VI>; + resets =3D <&cru SRST_P_CSI_HOST_2>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi2_in: port@0 { + reg =3D <0>; + }; + + csi2_out: port@1 { + reg =3D <1>; + }; + }; + }; + + csi4: csi@fdd50000 { + compatible =3D "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg =3D <0x0 0xfdd50000 0x0 0x10000>; + interrupts =3D , + ; + interrupt-names =3D "err1", "err2"; + clocks =3D <&cru PCLK_CSI_HOST_4>; + phys =3D <&csi_dphy1>; + power-domains =3D <&power RK3588_PD_VI>; + resets =3D <&cru SRST_P_CSI_HOST_4>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi4_in: port@0 { + reg =3D <0>; + }; + + csi4_out: port@1 { + reg =3D <1>; + }; + }; + }; + vop: vop@fdd90000 { compatible =3D "rockchip,rk3588-vop"; reg =3D <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; --=20 2.39.5