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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-507451cda0asm194096731cf.24.2026.03.05.02.17.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 02:17:19 -0800 (PST) From: Yongxing Mou Date: Thu, 05 Mar 2026 18:17:06 +0800 Subject: [PATCH v5 1/2] drm/msm/dpu: Update the intf_type of MST interfaces Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-mdss_catalog-v5-1-06678ac39ac7@oss.qualcomm.com> References: <20260305-mdss_catalog-v5-0-06678ac39ac7@oss.qualcomm.com> In-Reply-To: <20260305-mdss_catalog-v5-0-06678ac39ac7@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Mahadevan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou , Abhinav Kumar , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772705829; l=6579; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=7gkeiNxNKl6gMrOjBVvmFXUTc3giYW+5eNzAKZhEaVs=; b=A8H4tWgvmJewMNXWSG04jyIvgQM7r1m6IOYyhw9oxURvmv1BkwCmfPm2SSkPpj/roCAEB9c21 P9leAg1bb42Bpgzo3bJxNQZle/xESKkGn90+6OBaxOtuO7jZkqpAu5B X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDA4MiBTYWx0ZWRfX1fkTCXQrLber isdb0SdKjGH/lu0/yRBH516ZWdkSRFLMVB1f9azvEcDgnOo+F/j4QoO+BCXUBTYH3QYoJf41DkS 6mT+0zMARsOysAOEjE8Y2EjDIiS4fmP72W+ckB/sHb93ZEHJG/v15QyalgdUpJi9FbVl53PNMsZ pBwWALq88FX0+wkP7zUU5T1tTweThBILP0KkZIEjlzyWOXgHb2M6S8y+jB5Z+vZLSyskCpEWBkv O+04JehEiPaWpoOzjq2I2+icQjysYLXWLeh032G92tHdHJF2BdzeV8DX+oiDrV2/ve7lNxeBp+L 53yHw6zSGaFtqdHc2CxM73gCJYimBzKDpdkunouy8utY/AQnQiFaMFt6pCHKWNwUsqum45a08wH SI7v0IXG3VCSHdswpb9QavFwMX3pN94jK64qKRSCdYI8O02Mkb1dSSwGg03zudos/89kPFWBDeD SSAxIsp0rAWXEvFLvsQ== X-Proofpoint-GUID: dgfUndvv184qIG2UMc5GFsQGIJBZktuU X-Authority-Analysis: v=2.4 cv=SqydKfO0 c=1 sm=1 tr=0 ts=69a95831 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=4tyZmZgPP5sb52DUGSkA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: dgfUndvv184qIG2UMc5GFsQGIJBZktuU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-05_02,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 spamscore=0 suspectscore=0 impostorscore=0 adultscore=0 clxscore=1015 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603050082 From: Abhinav Kumar Interface type of MST interfaces is currently INTF_NONE when MST is not enabled. Update type to INTF_DP since will enable MST in the near future. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 6 +++--- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h index 13bb43ba67d3..a3b590cca21d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h @@ -426,7 +426,7 @@ static const struct dpu_intf_cfg glymur_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x400, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), @@ -458,7 +458,7 @@ static const struct dpu_intf_cfg glymur_intf[] =3D { }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x400, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), @@ -466,7 +466,7 @@ static const struct dpu_intf_cfg glymur_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x400, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 9f2bceca1789..89bc5b44f668 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -319,7 +319,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), @@ -351,7 +351,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_2, .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), @@ -359,7 +359,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 0f7b4a224e4c..6b24e9e84dec 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -347,7 +347,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), @@ -363,7 +363,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_6", .id =3D INTF_6, .base =3D 0x3A000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), @@ -371,7 +371,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), @@ -379,7 +379,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 52ff4baa668a..b35ad618ff63 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -335,7 +335,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), @@ -367,7 +367,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), @@ -375,7 +375,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), --=20 2.43.0