From nobody Thu Apr 9 21:53:47 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22B303822B7 for ; Thu, 5 Mar 2026 13:39:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772717987; cv=none; b=thKvHnJQ4OICJPNTiXC8MSuZAPKdbANOQYbIjntzO0nmrZga1x9bv9wX/5l4URvx7eYS38AYWHKznaqzvbDcydCVy3jgBwKNVM2aExwJSKZ52Ksm2hkhMLOQWaPhD9wpW54+ZG8buDlb82mSiHL0IAg5BffMGEqegpLzHKmkgvs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772717987; c=relaxed/simple; bh=mZOq4Lkgs8v8T9NZyyJHg91spf5S0MZ2S/xwswzDHPk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KajpDZksnlX1CMtGdt9cS+TTBNq4QegEwjaIOzAP7kh7NTIVst2RYdUR+PkuP/uKu6sCfnzgFSSFEtE1WQwbREbcDypTT4FgVZHGSOsFPMqd5iPu4aRO3hvLuQyDRTsLP2iih7zM7b2eaitaiR5IZWuBTtEMGCrUi/kZ39tGgoo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=acmHMOUx; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=XCrqvuiR; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="acmHMOUx"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="XCrqvuiR" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 625AFjBg935986 for ; Thu, 5 Mar 2026 13:39:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= XTXqn42rKWNP7ZScqGq5Fan9LitTyer6iA3RuPMR4Aw=; b=acmHMOUxk6Vmwrxu nPAUW7+QyCtoDJNBov2dsHZS7PszUOC2qlUXmSqaaF9wU0hFtIzEoiyqBAgrMGaH ewrbVdxKWvQCyAGrT5iJfY9QTWiFMahY8X5C1xKD+sQuzuJxGTI1vrlxyaFCHKm7 lNf+NgHPLDhqE0hypcuGLcRyhvjS/Qil6GIFBvWHOE2p0hCqXHaE5BLMd+ULzob3 YZ0M2f1hYv3QWYCYOjCAMjd4JcJyISSIp7+tNQCaGrQa9ym9onI874QUIdgZvpfH kVWnFbR6gNyS5iBK71fejvO5LsJwIRyuVbpVo/OufroARonOqRCJKUAj0UXqGXvc 7dLlIA== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cq04u27tt-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 05 Mar 2026 13:39:45 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-358e425c261so7154221a91.3 for ; Thu, 05 Mar 2026 05:39:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772717985; x=1773322785; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XTXqn42rKWNP7ZScqGq5Fan9LitTyer6iA3RuPMR4Aw=; b=XCrqvuiRF+eK+ZubgoGADxjLRGiGUBQcs82nv67sf6+DA3CuNMvsDBkGWQ9ayixJ7U Mk/37itewdWslQO7DX5fWrlgQaMXR+EFzsX/7uiTFxyH/YquuzYREY4grOPJiXpj1Q/A JAbVxjyKdETKWPq3FnBoAc3G+qFsMcpIyl3gQjahFTysDuHa0uWkXCxmpdmmyswJjmT2 PnYQ51/hbGlYcXhSUcV0t+ZkXCKyaz/PacHH2YlowXlFex8aAjVf6XDFO6+DQyoexnFz DkZ/6bjU2vbTM261sQTzn+Msg17OkEJHXZfykte2r4444lAf5agqi/cQFHxl9IkXgBPA HkzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772717985; x=1773322785; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=XTXqn42rKWNP7ZScqGq5Fan9LitTyer6iA3RuPMR4Aw=; b=JxBtUY5ymmhmRgdzwMHFf3PcNW7ig6CU7AMJUpTg6RqVSI/i6pxhKXFGVMIL2a/B2b QT0pS1a/P8uoTh4W7rmPnpDT/o/qJnZcq9MnhKUth7GghduRsP1osAgytlnM4L6cjj/d E8AO7H51LsnSwIQjTPQniUCyH2Iflcgs9uh73/XWSSCr9wjeKIHA6Vf/vFrd2cMHNmnO wVAMmBh82KnT7nF4AavREklDBC9a+HblaCbrf5avqh/o1FNWqy/taupZB9u3f9XhoyQc AYin52Xv4aN0get29KCURGMgFsURt5ZAURIiAw3gJf3zmkKLNGk2OoDZJfUfk/L53RqU TbCA== X-Forwarded-Encrypted: i=1; AJvYcCWOIp1/6KblOux7KH9hgLwD6rMxr4Sa/R41q5XLwBpQVwHbQkRvnUfeFpUEr5qIvueG2zFhSvVbrEOAeSY=@vger.kernel.org X-Gm-Message-State: AOJu0YwBdWnOmc2AhuopjMXKsjT7r3jIeJzSPTUDjUuNRutjjfSMS82U UUGSiA2I65d31El/EXbUUk260Kn416tjPptJSOh+rOvosHsBQf06OSGxef/QHxmghsqkEafgvAE XyJT40r8Rdj51PURh6h3tnSBTI8pvGrCgKLTfuOBU6fA8Wq8+8F5aZS0ZDkKc3c+3Gz8= X-Gm-Gg: ATEYQzyY7e17IXbhK4J/w5sSuX10e81Lmw9k3p94lSZFNcRABsU7++NAxj6xy1Exl0N momEdtHgprzsnuaWo44pzWo5q40CTLjrLnLvQDg6zFl6xqStSg2+u9KJ3eT1T6t5h7ncW+yjtcN 4qmRymZK0rrt552E4RrW2VKW8Y4lr3IHbuSV23gT74hWwGHg0lffj+MOWz+wfqBoSMGVkEyK8x/ 4/nORw+vmnt1JgjLf29nQ3le0ggtUlGjEL04dzjh+ivLSD6D/KqMbuOFTa7lGmRtkmgqjb0d9TL ZK3rZlbc3FEwYeGuxf0t6uYcuPJRBJTucxFOFH2kiRj9DmgCQZvcasrR9L5/AHSfMl10jBtolo6 tF73QJJUf0erhyis/rTOvB8k+1CRnZpfyK4eQFUVXWVDMMVMN5v6I5fkkgQ== X-Received: by 2002:a17:90b:3c46:b0:358:f04e:a617 with SMTP id 98e67ed59e1d1-359a69c764fmr5172634a91.10.1772717984825; Thu, 05 Mar 2026 05:39:44 -0800 (PST) X-Received: by 2002:a17:90b:3c46:b0:358:f04e:a617 with SMTP id 98e67ed59e1d1-359a69c764fmr5172604a91.10.1772717984256; Thu, 05 Mar 2026 05:39:44 -0800 (PST) Received: from hu-sushruts-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-359b2d5fe2dsm2195236a91.7.2026.03.05.05.39.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 05:39:43 -0800 (PST) From: Sushrut Shree Trivedi Date: Thu, 05 Mar 2026 19:09:31 +0530 Subject: [PATCH v4 1/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-industrial-mezzanine-pcie-v4-1-1f2c9d1344d7@oss.qualcomm.com> References: <20260305-industrial-mezzanine-pcie-v4-0-1f2c9d1344d7@oss.qualcomm.com> In-Reply-To: <20260305-industrial-mezzanine-pcie-v4-0-1f2c9d1344d7@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Sushrut Shree Trivedi , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772717976; l=4725; i=sushrut.trivedi@oss.qualcomm.com; s=20251127; h=from:subject:message-id; bh=mZOq4Lkgs8v8T9NZyyJHg91spf5S0MZ2S/xwswzDHPk=; b=D5UODKCQkBThJknAiBfl1IFg1qYZFJGLH+ZTRlRGe9beYCpcsI4tglSZr/GGAWroMOaNDUsaa H316RfKfpnBCmUv7O2pRJJyg+gnBiJaUURzeFXbEeH0gJ54UAKjWJZC X-Developer-Key: i=sushrut.trivedi@oss.qualcomm.com; a=ed25519; pk=OrUHTxBaSg1oY3CtCictJ5A4bDMNLRZS1S+QfD9pdjw= X-Proofpoint-GUID: xFxZBLmsMzv59ujDFmPEvNT0twG77Rkj X-Authority-Analysis: v=2.4 cv=eqTSD4pX c=1 sm=1 tr=0 ts=69a987a1 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=RBLAtJqH_bkH6XPhXP4A:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-ORIG-GUID: xFxZBLmsMzv59ujDFmPEvNT0twG77Rkj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDEwOSBTYWx0ZWRfXw7IjFHu9rYYI qVCUEkE6938QSCvfrluGiCoeDxTe12xNAsK5DHUJpUAWWhuZtBsU4c+17lDrS1mrfYj339UJZy9 nOzTZXRodxZuQB51kj0X2DArgEFqWLj9L8Ln35i5FHsoSReZiCc5XKRPP/oyIRoo3vXgJSAiVFm +6NT9iC2gSX81uOPVhjS3bd95NImht8bj7WRq4gy35l2FaKE8AFcGYec3E4/ZRtKrUC0oJ3DcDD X7RZBc5vb6qLXs/7hP+lOaKxWFxrOuoaO/UW0/y1SNDi57gPU38HTov3+lC6rTFSKMUKGHW59i6 Id5EBOWb0J0actjlne7btRxfs0trXUpCZfUFeJN6jHeZTXSRORjTOfluKWSCUZs/tXZ1FMbauyE W3mGTUWJwtHk4tWopOcNyXqKeMBqBpQuAFwKTvhF4Xe3hvHYqkrwxOrzHR+uaXpxl7+qbhqlLXC Oh9oMhqt9SV/Cr/qTlQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-05_04,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603050109 Add a node for the TC9563 PCIe switch connected to PCIe0. The switch has three downstream ports.Two embedded Ethernet devices are present on one of the downstream ports. All the ports present in the node represent the downstream ports and embedded endpoints. Power to the TC9563 is supplied through two LDO regulators, which are on by default and are added as fixed regulators. TC9563 can be configured through I2C. Signed-off-by: Sushrut Shree Trivedi Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 159 +++++++++++++++++= ++++ 1 file changed, 159 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.= dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 619a42b5ef48..c58a9ad5c331 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -5,9 +5,33 @@ =20 /dts-v1/; /plugin/; +#include #include #include =20 +&{/} { + + vreg_0p9: regulator-vreg-0p9 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_0P9"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-vreg-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + &spi11 { #address-cells =3D <1>; #size-cells =3D <0>; @@ -19,3 +43,138 @@ st33htpm0: tpm@0 { spi-max-frequency =3D <20000000>; }; }; + +&pcie0 { + perst-gpios =3D <&tlmm 87 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; + pinctrl-names =3D "default"; + + iommu-map =3D <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>, + <0x208 &apps_smmu 0x1c04 0x1>, + <0x210 &apps_smmu 0x1c05 0x1>, + <0x218 &apps_smmu 0x1c06 0x1>, + <0x300 &apps_smmu 0x1c07 0x1>, + <0x400 &apps_smmu 0x1c08 0x1>, + <0x500 &apps_smmu 0x1c09 0x1>, + <0x501 &apps_smmu 0x1c10 0x1>; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l10c_0p88>; + vdda-pll-supply =3D <&vreg_l6b_1p2>; + + status =3D "okay"; +}; + +&pcie0_port { + #address-cells =3D <3>; + #size-cells =3D <2>; + + pcie@0,0 { + compatible =3D "pci1179,0623"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x2 0xff>; + + vddc-supply =3D <&vreg_0p9>; + vdd18-supply =3D <&vreg_1p8>; + vdd09-supply =3D <&vreg_0p9>; + vddio1-supply =3D <&vreg_1p8>; + vddio2-supply =3D <&vreg_1p8>; + vddio18-supply =3D <&vreg_1p8>; + + i2c-parent =3D <&i2c1 0x33>; + + resx-gpios =3D <&tlmm 78 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie0_tc9563_resx_n>; + pinctrl-names =3D "default"; + + pcie@1,0 { + reg =3D <0x20800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x3 0xff>; + }; + + pcie@2,0 { + reg =3D <0x21000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x4 0xff>; + }; + + pcie@3,0 { + reg =3D <0x21800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + bus-range =3D <0x5 0xff>; + + pci@0,0 { + reg =3D <0x50000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + + pci@0,1 { + reg =3D <0x50100 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + }; + + }; +}; + +&tlmm { + pcie0_tc9563_resx_n: pcie0-tc9563-resx-state { + pins =3D "gpio78"; + function =3D "gpio"; + bias-disable; + input-disable; + output-enable; + }; + + pcie0_reset_n: pcie0-reset-n-state { + pins =3D "gpio87"; + function =3D "gpio"; + drive-strength =3D <16>; + output-low; + bias-disable; + }; + + pcie0_clkreq_n: pcie0-clkreq-n-state { + pins =3D "gpio88"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + pcie0_wake_n: pcie0-wake-n-state { + pins =3D "gpio89"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + +}; --=20 2.25.1 From nobody Thu Apr 9 21:53:47 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A68537E2EE for ; Thu, 5 Mar 2026 13:39:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772717992; cv=none; b=oNzL4beJD5q6lp8L9E6VhArxLCepjosKSFrQEu87D4hCK0B4zUZjRIGQI88k+oZDezAeBhlS0TyLqQZ+zlz/PfQ+7+tTGN5CmPvtxsycq3/lXQirGdAzDFp+Qc4Xu8NCt8f35uxVb6OnGkxg1hKxsCg8KAYk4UgMAiS+/0tMvtk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772717992; c=relaxed/simple; bh=EKv8wOSJGRlhpeUGi+dyApwOnzSEKJGSXglpAxxJlcQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Dm1Bvz6z3ODnMpTO83fu9Q/Pw1AClAM9yoSrpu99OiEEM4+E6aCb8C1ymCpuO+ljo2HAPnxmnuE5VCMCloWq/hNXaN8YICNpstVtiZjQTxM4XoEOFnGqq02YjseJWjcNweYh5D6rTuQjso1/WB8Nv7C4zSdm8fByNmijxxENNtI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=NplH6MbA; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=hU12wpoc; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="NplH6MbA"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="hU12wpoc" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 625AFjwa936026 for ; Thu, 5 Mar 2026 13:39:49 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= xcpYEMXP4Nu8WtXRYSEcQ0DhOhHdqMNhLIC2zKaCrR4=; b=NplH6MbAbRtklWuA 9mGLvkyzqj7w0e80dmakLOFcrW4wQxiH+BNX6TiCBmnnwQyylj/6rFvZ2s9ZofNx expHyBvIPF287lqiBLknS0q0EHX8LewJsZBo04u8Nu41Uk2RHYUA/EMr/Qk6iWZo mIjrgJUHXQZx9J09rlzQ8VEG9bz3DzyPSbpBrXePiCTMTQhs2dfSYVEngTEkv6vu //3mRm+d6Oxahacf5dOY6//kJbLQXWXSFXKHWyFwwggcFHAP8LtCQVczewSsDZL0 biPx2rIC8IKAVlCVQUeBS/eVxNC3PDSJnM+7I1sOK3aF57l6DfFW73OU+KZEL0pE u9MXDg== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cq04u27u0-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 05 Mar 2026 13:39:49 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-354bc535546so6565102a91.3 for ; Thu, 05 Mar 2026 05:39:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772717989; x=1773322789; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xcpYEMXP4Nu8WtXRYSEcQ0DhOhHdqMNhLIC2zKaCrR4=; b=hU12wpocAT/43bTLXNMqrGyGBzcZqdqGdiZsC+WELnIwooOWrtMWXNAN9gA4XKaRqt X0FjFUV98pmCGKcLr6zgNlZs8zfxEwnvdIOdVQRltI3QFs7aep7TioCbhea37DjyBHSv 2TkLbr0CcNYjoR9JlruQoLmMO8K+1xxqFoQ5Gu25RrDwTXbNLo9hCS+IWHcDbepEWmV0 c/DmMc5Oy7JXiAMC0L67qOYEVZd4MaX7nF+eOFB9sVa736pSl/GmYZxXvS/jiqOR5wFi oGHZom4GxQxGDHEitX9kCdqUNU3DiaFTd9R2ER3dfhevJfbEPD2Ec3qZCKkGEuQ44y7d pqAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772717989; x=1773322789; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=xcpYEMXP4Nu8WtXRYSEcQ0DhOhHdqMNhLIC2zKaCrR4=; b=KQjbSX/3xCZb6/dWQ8SL6jD1TBoYmbxQOXdVKwv2c4kPpUnXBATSLvprepDRdYYcRn jhgGvVswMRpp8QMKQyDLmJchk58VfPfwSzUJA0ji4fR5ZYnfyNW+gykYQZFMtknB2Q4i bvoP8eo2fHUdQrkFI8kc1yLYgd/XFpDSov3OFgJzvQhpIx7pR4fFr79ewOl6fXoLWgLn qwwYJ19fQMHeoAjGt65WYZE7VPGJ8xp6lQJY5DOfSJ+iCCQnW2csM68p5jiUGz/0kYZb 8Kj/eq1U55m/piTAt+VkGGlne7Riw7HC+3LL0IK6oK6s9VAakVrjD7VydDZiqHHB0hVx aZsA== X-Forwarded-Encrypted: i=1; AJvYcCUmXted01dv2Zg8RfQeGD4Q2CIdFt/mRpDQIlQcIOeYHZPb/r3OVqMxKA+mvO7nhXBuHvCpVDI+AtmDwn4=@vger.kernel.org X-Gm-Message-State: AOJu0YwaEx1ACTaMCTFKFKVGt4oe0sr3WxUN7rebqzEgx6QVRXGf9BGJ R09AnIjz5J87HQ1pBhkQh27IFheVLIp996RCXwvytzZHzJrbVhwKaNQam+oUewmNLh4tWX7hyFB 6hQG6LQyGcC3+CgZKoxVSMH9T3HdxV2bhVESk8btHTQB6F8kFv/Mc8jqNEeuGSEOnWMI= X-Gm-Gg: ATEYQzybsyVGTcH9VQkht+qATdrS1vgjZWFOHAoMz7mygSBA9Mgk2okt+3HsJeE7u4Z uY4vtqJ06KAJ6HY57UnMdjb5dxiW69/WjQsRwDNc1ImbTerryw3gdlD+BODxFP4RXFfu3iNXdGK vG32yQ1ZfH+rnPOn1TeZDmTbP+5nneniF3OlbnMRePl5u5JwSOErlydUuGE/acA0JeK+00fVF3C fKRhdNYgmcK2xY8NYlIezfTX0Kus+TXrLobNVs2tEblxb9pBgXgcmWzTXRVRZoy7v09nu4ZgtTj ernGm52W+zQJ5Vvd+uq5+dey7u04Bgi4SuyI/qp272JF5beJbdLwaDbv0Pmxd73spaWLHN2l0Li HacisBaHEyzYamVT1feYI3KwQ0wUTqW26W1GCZ18xShKcK7yGclDPyudNNg== X-Received: by 2002:a17:90b:2c90:b0:359:8d70:c4ed with SMTP id 98e67ed59e1d1-359a69a26c1mr5088427a91.7.1772717988602; Thu, 05 Mar 2026 05:39:48 -0800 (PST) X-Received: by 2002:a17:90b:2c90:b0:359:8d70:c4ed with SMTP id 98e67ed59e1d1-359a69a26c1mr5088397a91.7.1772717988039; Thu, 05 Mar 2026 05:39:48 -0800 (PST) Received: from hu-sushruts-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-359b2d5fe2dsm2195236a91.7.2026.03.05.05.39.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 05:39:47 -0800 (PST) From: Sushrut Shree Trivedi Date: Thu, 05 Mar 2026 19:09:32 +0530 Subject: [PATCH v4 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-industrial-mezzanine-pcie-v4-2-1f2c9d1344d7@oss.qualcomm.com> References: <20260305-industrial-mezzanine-pcie-v4-0-1f2c9d1344d7@oss.qualcomm.com> In-Reply-To: <20260305-industrial-mezzanine-pcie-v4-0-1f2c9d1344d7@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Sushrut Shree Trivedi , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772717976; l=4306; i=sushrut.trivedi@oss.qualcomm.com; s=20251127; h=from:subject:message-id; bh=EKv8wOSJGRlhpeUGi+dyApwOnzSEKJGSXglpAxxJlcQ=; b=57Rdh+0nw//YsAa0uXxLianwueKyTEtSnAGRJzh93o6DwK2vIc/0PL+lkjF63P0W0jwq83uEL 0Q02AUNUkIWCaDFacs4D1YkmkfrnbRCEfiGogvRlWhv0lDAC4YyFl6F X-Developer-Key: i=sushrut.trivedi@oss.qualcomm.com; a=ed25519; pk=OrUHTxBaSg1oY3CtCictJ5A4bDMNLRZS1S+QfD9pdjw= X-Proofpoint-GUID: p4aGPkqJ_jyH6P28ul03KZDXNDR1N8Kk X-Authority-Analysis: v=2.4 cv=eqTSD4pX c=1 sm=1 tr=0 ts=69a987a5 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=bvgCVipTNhjOeuzF1ioA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: p4aGPkqJ_jyH6P28ul03KZDXNDR1N8Kk X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDEwOSBTYWx0ZWRfX4vt1Qg9HbEIo 0r/oLT+YsFwPqqeuz36bIXzeTWXOvTUnYuOB4Hwe3W9NFZMC7/Oz6e93hw348l5Mcqbc+tFMNu0 d77seZAT/2u1MP/nDaSdZVnR0kSDx9uQlBh/CJKlbfrRpipc+qUjuOxcApNmv9Rhf194qLuaL8F bsjUNzghamCTEbj7OEP8uG3VoZ/WRfiSgVI9Qhwl+73mRiYOOnSoH77sy3ZVcqTyWckqmOCrfB1 OtkXeK6gahLRRXvp76mWUEyPpOcCytFtKOkZhJRZdyZkKd+jKH3Yd0BF+ZIwhhWUYDwf+4E09+o xcUmwSEmPLU9UoqV3LNE5fkwP1Wwy1iF+emy4m5Wr4HVLsbhgBdTCLfJZpnTZu1InxIwVZdeQFc uhOCSKGa5gSnMlNw6sTvGPuLnT8ac+mSCReacjSgnQNY/lIoNL19oIoQwe+/z5jjZuEeYKM1yKQ FlrQ7QsXboXPL+p3d8A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-05_04,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603050109 Add a node for the second TC9563 PCIe switch on PCIe1, which is connected in cascade to the first TC9563 switch via the former's downstream port. Two embedded Ethernet devices are present on one of the downstream ports of this second switch as well. All the ports present in the node represent the downstream ports and embedded endpoints. The second TC9563 is powered up via the same LDO regulators as the first one, and these can be controlled via two GPIOs, which are already present as fixed regulators. This TC9563 can also be configured through I2C. Signed-off-by: Sushrut Shree Trivedi Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 102 +++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 2 +- 2 files changed, 103 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.= dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index c58a9ad5c331..2a2b7c2f9210 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -146,6 +146,100 @@ pci@0,1 { }; }; =20 +&pcie1 { + iommu-map =3D <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>, + <0x208 &apps_smmu 0x1c84 0x1>, + <0x210 &apps_smmu 0x1c85 0x1>, + <0x218 &apps_smmu 0x1c86 0x1>, + <0x300 &apps_smmu 0x1c87 0x1>, + <0x408 &apps_smmu 0x1c90 0x1>, + <0x410 &apps_smmu 0x1c91 0x1>, + <0x418 &apps_smmu 0x1c92 0x1>, + <0x500 &apps_smmu 0x1c93 0x1>, + <0x600 &apps_smmu 0x1c94 0x1>, + <0x700 &apps_smmu 0x1c95 0x1>, + <0x701 &apps_smmu 0x1c96 0x1>, + <0x800 &apps_smmu 0x1c97 0x1>, + <0x900 &apps_smmu 0x1c98 0x1>, + <0x901 &apps_smmu 0x1c99 0x1>; +}; + +&pcie1_switch0_dsp1 { + #address-cells =3D <3>; + #size-cells =3D <2>; + + pcie@0,0 { + compatible =3D "pci1179,0623"; + reg =3D <0x30000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x2 0xff>; + + vddc-supply =3D <&vdd_ntn_0p9>; + vdd18-supply =3D <&vdd_ntn_1p8>; + vdd09-supply =3D <&vdd_ntn_0p9>; + vddio1-supply =3D <&vdd_ntn_1p8>; + vddio2-supply =3D <&vdd_ntn_1p8>; + vddio18-supply =3D <&vdd_ntn_1p8>; + + i2c-parent =3D <&i2c1 0x77>; + + resx-gpios =3D <&tlmm 124 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie1_tc9563_resx_n>; + pinctrl-names =3D "default"; + + pcie@1,0 { + reg =3D <0x40800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x3 0xff>; + }; + + pcie@2,0 { + reg =3D <0x41000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x4 0xff>; + }; + + pcie@3,0 { + reg =3D <0x41800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + bus-range =3D <0x5 0xff>; + + pci@0,0 { + reg =3D <0x50000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + + pci@0,1 { + reg =3D <0x50100 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + }; + }; +}; + &tlmm { pcie0_tc9563_resx_n: pcie0-tc9563-resx-state { pins =3D "gpio78"; @@ -177,4 +271,12 @@ pcie0_wake_n: pcie0-wake-n-state { bias-pull-up; }; =20 + pcie1_tc9563_resx_n: pcie1-tc9563-resx-state { + pins =3D "gpio124"; + function =3D "gpio"; + bias-disable; + input-disable; + output-enable; + }; + }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot= /dts/qcom/qcs6490-rb3gen2.dts index e3d2f01881ae..cd54525e45e0 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -852,7 +852,7 @@ pcie@0,0 { pinctrl-0 =3D <&tc9563_resx_n>; pinctrl-names =3D "default"; =20 - pcie@1,0 { + pcie1_switch0_dsp1: pcie@1,0 { reg =3D <0x20800 0x0 0x0 0x0 0x0>; #address-cells =3D <3>; #size-cells =3D <2>; --=20 2.25.1