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Thu, 05 Mar 2026 02:40:31 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ae4650000dsm134429325ad.54.2026.03.05.02.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 02:40:31 -0800 (PST) From: Taniya Das Date: Thu, 05 Mar 2026 16:10:10 +0530 Subject: [PATCH v5 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-gpucc_sm8750_v2-v5-3-78292b40b053@oss.qualcomm.com> References: <20260305-gpucc_sm8750_v2-v5-0-78292b40b053@oss.qualcomm.com> In-Reply-To: <20260305-gpucc_sm8750_v2-v5-0-78292b40b053@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-ORIG-GUID: IKMIi0qCnVdlx7mE7OXwMrsB4Qaf9fLK X-Proofpoint-GUID: IKMIi0qCnVdlx7mE7OXwMrsB4Qaf9fLK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDA4NiBTYWx0ZWRfX2zOfshz5fuhq ftcFLeeNYhLjJ0LyHEV1IlOAcoK5v+syVVgZaWsVyMKIwzbIPN91NtBnYORsdBct7HbeKQSshtm NknXjEYY/NCkITT8KhmRe87thiIQxP24MOZcm/On0c97+RAlUorREyJ+geCoqrV2N6jtpzU6x2p H2H2Zt9G1p1pvtY21/5Dy4Wt7Q9e7DcBD5KlhLyS11JLWpHu8kHKwIAu74VbTTQCHg02OC2b1k6 pUfUBDTtjA/9f1vaxjnHinQLb6vIz5O7QHJI7DUFZWKhBI8wMvZbWZAcv0XlKVmbX75DyaYFCKu h9KjXkaXlNqhKhELxQD3pjwfWsfQAWaT4TSIrCkG9awA97vjn3U6hsHgcqX4Jp/mrZNBYFFP8fv 9ISxYQXJ6MXe7/yrBMUP1oS+ehAuGx33BoSORJAQ+kMTv1M1ybOsfoTBdvKDVTy/9/sVJBumUUt N9xfAgO6E/LTTi7qlzA== X-Authority-Analysis: v=2.4 cv=N64k1m9B c=1 sm=1 tr=0 ts=69a95da1 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=CyMIzFe51rGKrm3YhSgA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-05_02,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 bulkscore=0 clxscore=1015 adultscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603050086 From: Konrad Dybcio Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this is simply a separate block housing the GX GDSC) nodes, required to power up the graphics-related hardware. Make use of it by enabling the associated IOMMU as well. The GPU itself needs some more work and will be enabled later. Reviewed-by: Abel Vesa Signed-off-by: Konrad Dybcio Co-developed-by: Taniya Das Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 68 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index f56b1f889b857a28859910f5c4465c8ce3473b00..0e7a343297e3f5d7a8189f50726= dc6279078c21c 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -4,7 +4,9 @@ */ =20 #include +#include #include +#include #include #include #include @@ -3001,6 +3003,34 @@ videocc: clock-controller@aaf0000 { #power-domain-cells =3D <1>; }; =20 + gxclkctl: clock-controller@3d64000 { + compatible =3D "qcom,sm8750-gxclkctl"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells =3D <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,sm8750-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + power-domains =3D <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm8750-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; @@ -4515,6 +4545,44 @@ tpdm_swao_out: endpoint { }; }; =20 + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,sm8750-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names =3D "hlos"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + apps_smmu: iommu@15000000 { compatible =3D "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg =3D <0x0 0x15000000 0x0 0x100000>; --=20 2.34.1