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Thu, 05 Mar 2026 02:40:21 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ae4650000dsm134429325ad.54.2026.03.05.02.40.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 02:40:21 -0800 (PST) From: Taniya Das Date: Thu, 05 Mar 2026 16:10:08 +0530 Subject: [PATCH v5 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-gpucc_sm8750_v2-v5-1-78292b40b053@oss.qualcomm.com> References: <20260305-gpucc_sm8750_v2-v5-0-78292b40b053@oss.qualcomm.com> In-Reply-To: <20260305-gpucc_sm8750_v2-v5-0-78292b40b053@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-ORIG-GUID: qzUX5AssdxKdTvhRsDiusd4tHZrVXRO3 X-Proofpoint-GUID: qzUX5AssdxKdTvhRsDiusd4tHZrVXRO3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDA4NiBTYWx0ZWRfXxmRGYbfnzFCc naS6VqTvJHNrdYI8DuPTOIWQlfZdk70QSySstdti4+QxkkWw1dPRlroINOGFQ/tgPu4rDPEV9eX k+wS/UKzR6a94rBZNXV1wBfL0kGdE+YURn9WQO1L99Z/V905DBOkspnMIXu20oheJoIVkY+BJ8e OAGps9Q9cMWkg9ll4y6TVPPybQCJYWm0hlAoNYq+0DoofJFCU1Ox8MrX9uHoyyVNb139uk1mqZT d4UtV4+4Roprut/klTCV30IByCi2kYf9K5ZMt2CCdCL2C5EbaTBIRsofffq+g1tle94gfaG4UJg Kgk0MqH7I0uq7HQlmJuHwqD/Lt64MmIcb6F8tokqrlWAQXgA9qaY/8aObhrKic4KFxDO0B32SAt /4jaIld2M1NaDH74waP5BUToA9iXApemgTTFfQrYaIlqb7p6zf2AHRiff4Nv5qCnM3ib3+wd3tx YXrs06AgG6SBwz4gUeQ== X-Authority-Analysis: v=2.4 cv=N64k1m9B c=1 sm=1 tr=0 ts=69a95d97 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=lJl75u3uZd5g0oXYmjoA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-05_02,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 bulkscore=0 clxscore=1015 adultscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603050086 From: Konrad Dybcio The SM8750 features a "traditional" GPU_CC block, much of which is controlled through the GMU microcontroller. GPU_CC block requires the MX and CX rail control and thus add the corresponding power-domains and require-opps. Additionally, there's an separate GX_CC block, where the GX GDSC is moved. Update the bindings to accommodate for SM8750 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Taniya Das --- .../bindings/clock/qcom,kaanapali-gxclkctl.yaml | 1 + .../bindings/clock/qcom,sm8450-gpucc.yaml | 23 ++++++++++ include/dt-bindings/clock/qcom,sm8750-gpucc.h | 50 ++++++++++++++++++= ++++ 3 files changed, 74 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkct= l.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.ya= ml index 5490a975f3db7d253a17cc13a67f6c44e0d47ef3..1876f23c174e4ede590847d8022= 2e49b4200d8ba 100644 --- a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml @@ -21,6 +21,7 @@ properties: compatible: enum: - qcom,kaanapali-gxclkctl + - qcom,sm8750-gxclkctl =20 power-domains: description: diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index 6feaa32569f9a852c2049fee00ee7a2e2aefb558..d8828f905bc017172eb8442a8bb= 760781feb372a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -8,6 +8,7 @@ title: Qualcomm Graphics Clock & Reset Controller on SM8450 =20 maintainers: - Konrad Dybcio + - Taniya Das =20 description: | Qualcomm graphics clock control module provides the clocks, resets and p= ower @@ -22,6 +23,7 @@ description: | include/dt-bindings/clock/qcom,sm8550-gpucc.h include/dt-bindings/reset/qcom,sm8450-gpucc.h include/dt-bindings/reset/qcom,sm8650-gpucc.h + include/dt-bindings/reset/qcom,sm8750-gpucc.h include/dt-bindings/reset/qcom,x1e80100-gpucc.h =20 properties: @@ -35,6 +37,7 @@ properties: - qcom,sm8475-gpucc - qcom,sm8550-gpucc - qcom,sm8650-gpucc + - qcom,sm8750-gpucc - qcom,x1e80100-gpucc - qcom,x1p42100-gpucc =20 @@ -44,6 +47,16 @@ properties: - description: GPLL0 main branch source - description: GPLL0 div branch source =20 + power-domains: + items: + - description: A phandle to the MX power-domain + - description: A phandle to the CX power-domain + + required-opps: + items: + - description: A phandle to an OPP node describing MX performance po= ints + - description: A phandle to an OPP node describing CX performance po= ints + required: - compatible - clocks @@ -51,6 +64,16 @@ required: =20 allOf: - $ref: qcom,gcc.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8750-gpucc + then: + required: + - power-domains + - required-opps =20 unevaluatedProperties: false =20 diff --git a/include/dt-bindings/clock/qcom,sm8750-gpucc.h b/include/dt-bin= dings/clock/qcom,sm8750-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..e2143d905fece19f4ef5cf41372= 4f1597daa85ba --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8750-gpucc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DPM_CLK 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_ACCU_SHIFT_CLK 12 +#define GPU_CC_GX_ACD_AHB_FF_CLK 13 +#define GPU_CC_GX_AHB_FF_CLK 14 +#define GPU_CC_GX_GMU_CLK 15 +#define GPU_CC_GX_RCG_AHB_FF_CLK 16 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_DIV_CLK_SRC 21 +#define GPU_CC_MEMNOC_GFX_CLK 22 +#define GPU_CC_PLL0 23 +#define GPU_CC_PLL0_OUT_EVEN 24 +#define GPU_CC_RSCC_HUB_AON_CLK 25 +#define GPU_CC_RSCC_XO_AON_CLK 26 +#define GPU_CC_SLEEP_CLK 27 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 + +/* GPU_CC resets */ +#define GPU_CC_GPU_CC_CB_BCR 0 +#define GPU_CC_GPU_CC_CX_BCR 1 +#define GPU_CC_GPU_CC_FAST_HUB_BCR 2 +#define GPU_CC_GPU_CC_FF_BCR 3 +#define GPU_CC_GPU_CC_GMU_BCR 4 +#define GPU_CC_GPU_CC_GX_BCR 5 +#define GPU_CC_GPU_CC_XO_BCR 6 + +#endif --=20 2.34.1 From nobody Thu Apr 9 23:27:32 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 482A9382298 for ; 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Thu, 05 Mar 2026 02:40:26 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ae4650000dsm134429325ad.54.2026.03.05.02.40.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 02:40:26 -0800 (PST) From: Taniya Das Date: Thu, 05 Mar 2026 16:10:09 +0530 Subject: [PATCH v5 2/3] clk: qcom: Add a driver for SM8750 GPU clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-gpucc_sm8750_v2-v5-2-78292b40b053@oss.qualcomm.com> References: <20260305-gpucc_sm8750_v2-v5-0-78292b40b053@oss.qualcomm.com> In-Reply-To: <20260305-gpucc_sm8750_v2-v5-0-78292b40b053@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-GUID: E5OISxI_NtDCSLxwOLOB6vteVMdwTbYD X-Authority-Analysis: v=2.4 cv=BNK+bVQG c=1 sm=1 tr=0 ts=69a95d9c cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=PLT511quuigA__OA0o4A:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDA4NiBTYWx0ZWRfX8IzaY3o5cm6B dKNw08IQLdimuZY8BcxCbcizWUIEXyNzrbOalnt7ARyGCTx9TL4RX0gLsM5BNRrvvooE5IMRlA3 dyDkEXylYKRO1O7+HE/2vrj9qKBgjsWcMptLIVP4jcZyd1fQ/AkEemXS9cfrNspIYPua1W5eG6M owjZMfjDcaLR9rRCyq9g9Ev0O4TupwMhsSnhrqWEsqorE/+bDz1lRAcxSRTBWTTUDBwh7CixMuR ekRagmPWppJwMd3e7K3klWqxmhy9by9AkXrF9GAsIYASkJqRE0WNoyO0wpyjn8DYguFsPpFB9+v FthsOPt4ZOo8yjPsqksqHRQ3/T2FwYb+qQ2liJSMxiD9ANb3G+WU5YhPqAO7Jj/XwlH90zicfh0 WgliMomyn7MUc4FkY2/UoHjCSImAA5PDzAo45kl8Bypwfg6X+pFzHS0zyWqoYsK3RAaTK7SV1O2 28P3tFhtO46xXm7Q4/A== X-Proofpoint-ORIG-GUID: E5OISxI_NtDCSLxwOLOB6vteVMdwTbYD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-05_02,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 spamscore=0 clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603050086 From: Konrad Dybcio Support the graphics clock controller for SM8750 for Graphics SW driver to use the clocks. GXCLKCTL (Graphics GX Clock Controller) is a block dedicated to managing clocks for the GPU subsystem on GX power domain. The GX clock controller driver manages only the GX GDSC and the rest of the resources of the controller are managed by the firmware. Update the compatible for Graphics GX Clock Controller for SM8750 as the GX clock controller is a reuse of the Kaanapali driver. Reviewed-by: Abel Vesa Signed-off-by: Konrad Dybcio Co-developed-by: Taniya Das Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm8750.c | 473 ++++++++++++++++++++++++++++++= ++++ drivers/clk/qcom/gxclkctl-kaanapali.c | 1 + 4 files changed, 484 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a8a86ea6bb7445e396048a5bba23fce8d719281f..e4ec41e3dc7dee43a5682a3bd93= 297785e67e41f 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1481,6 +1481,15 @@ config SM_GPUCC_8650 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. =20 +config SM_GPUCC_8750 + tristate "SM8750 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_8750 + help + Support for the graphics clock controller on SM8750 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_LPASSCC_6115 tristate "SM6115 Low Power Audio Subsystem (LPASS) Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 6b0ad8832b55f1914079f15323b8cdd1608ad4c0..817b13f5e78cb534e165b09d95e= 70cd4a58b12bd 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -180,6 +180,7 @@ obj-$(CONFIG_SM_GPUCC_8350) +=3D gpucc-sm8350.o obj-$(CONFIG_SM_GPUCC_8450) +=3D gpucc-sm8450.o obj-$(CONFIG_SM_GPUCC_8550) +=3D gpucc-sm8550.o obj-$(CONFIG_SM_GPUCC_8650) +=3D gpucc-sm8650.o +obj-$(CONFIG_SM_GPUCC_8750) +=3D gpucc-sm8750.o gxclkctl-kaanapali.o obj-$(CONFIG_SM_GPUCC_MILOS) +=3D gpucc-milos.o obj-$(CONFIG_SM_LPASSCC_6115) +=3D lpasscc-sm6115.o obj-$(CONFIG_SM_TCSRCC_8550) +=3D tcsrcc-sm8550.o diff --git a/drivers/clk/qcom/gpucc-sm8750.c b/drivers/clk/qcom/gpucc-sm875= 0.c new file mode 100644 index 0000000000000000000000000000000000000000..5d52c6d8b5e51356ee691d8a2ef= 46e80bffab0cb --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm8750.c @@ -0,0 +1,473 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_EVEN, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL0_OUT_ODD, +}; + +static const struct pll_vco taycan_elu_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x34, + .alpha =3D 0x1555, + .config_ctl_val =3D 0x19660387, + .config_ctl_hi_val =3D 0x098060a0, + .config_ctl_hi1_val =3D 0xb416cb20, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &gpu_cc_pll0_config, + .vco_table =3D taycan_elu_vco, + .num_vco =3D ARRAY_SIZE(taycan_elu_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_elu_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll0_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gpu_cc_pll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_elu_ops, + }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL0_OUT_EVEN, 2 }, + { P_GPU_CC_PLL0_OUT_ODD, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll0_out_even.clkr.hw }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(500000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(687500000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x9318, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src =3D { + .cmd_rcgr =3D 0x93ec, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_div_clk_src =3D { + .reg =3D 0x942c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk =3D { + .halt_reg =3D 0x90bc, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x90bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_accu_shift_clk =3D { + .halt_reg =3D 0x910c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x910c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x90d4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk =3D { + .halt_reg =3D 0x90e4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x90e4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cxo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_demet_clk =3D { + .halt_reg =3D 0x9010, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_demet_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_dpm_clk =3D { + .halt_reg =3D 0x9110, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9110, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_dpm_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk =3D { + .halt_reg =3D 0x900c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x900c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_freq_measure_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_accu_shift_clk =3D { + .halt_reg =3D 0x9070, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk =3D { + .halt_reg =3D 0x9060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { + .halt_reg =3D 0x7000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk =3D { + .halt_reg =3D 0x93e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x93e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_aon_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk =3D { + .halt_reg =3D 0x90e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_cx_int_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk =3D { + .halt_reg =3D 0x90f4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90f4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_memnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cc_cx_gdsc =3D { + .gdscr =3D 0x9080, + .gds_hw_ctrl =3D 0x9094, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x8, + .pd =3D { + .name =3D "gpu_cc_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct clk_regmap *gpu_cc_sm8750_clocks[] =3D { + [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] =3D &gpu_cc_cx_accu_shift_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, + [GPU_CC_DEMET_CLK] =3D &gpu_cc_demet_clk.clkr, + [GPU_CC_DPM_CLK] =3D &gpu_cc_dpm_clk.clkr, + [GPU_CC_FREQ_MEASURE_CLK] =3D &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_ACCU_SHIFT_CLK] =3D &gpu_cc_gx_accu_shift_clk.clkr, + [GPU_CC_GX_GMU_CLK] =3D &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] =3D &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] =3D &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_DIV_CLK_SRC] =3D &gpu_cc_hub_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] =3D &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, + [GPU_CC_PLL0_OUT_EVEN] =3D &gpu_cc_pll0_out_even.clkr, +}; + +static struct gdsc *gpu_cc_sm8750_gdscs[] =3D { + [GPU_CC_CX_GDSC] =3D &gpu_cc_cx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_sm8750_resets[] =3D { + [GPU_CC_GPU_CC_XO_BCR] =3D { 0x9000 }, + [GPU_CC_GPU_CC_GX_BCR] =3D { 0x905c }, + [GPU_CC_GPU_CC_CX_BCR] =3D { 0x907c }, + [GPU_CC_GPU_CC_GMU_BCR] =3D { 0x9314 }, + [GPU_CC_GPU_CC_CB_BCR] =3D { 0x93a0 }, + [GPU_CC_GPU_CC_FAST_HUB_BCR] =3D { 0x93e4 }, +}; + +static const struct regmap_config gpu_cc_sm8750_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9800, + .fast_io =3D true, +}; + +static struct clk_alpha_pll *gpu_cc_alpha_plls[] =3D { + &gpu_cc_pll0, +}; + +static u32 gpu_cc_sm8750_critical_cbcrs[] =3D { + 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */ + 0x9008, /* GPU_CC_CXO_AON_CLK */ + 0x9064, /* GPU_CC_GX_AHB_FF_CLK */ + 0x90cc, /* GPU_CC_SLEEP_CLK */ + 0x93a4, /* GPU_CC_CB_CLK */ + 0x93a8, /* GPU_CC_RSCC_HUB_AON_CLK */ +}; + +static struct qcom_cc_driver_data gpu_cc_sm8750_driver_data =3D { + .alpha_plls =3D gpu_cc_alpha_plls, + .num_alpha_plls =3D ARRAY_SIZE(gpu_cc_alpha_plls), + .clk_cbcrs =3D gpu_cc_sm8750_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gpu_cc_sm8750_critical_cbcrs), +}; + +static const struct qcom_cc_desc gpu_cc_sm8750_desc =3D { + .config =3D &gpu_cc_sm8750_regmap_config, + .clks =3D gpu_cc_sm8750_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_sm8750_clocks), + .resets =3D gpu_cc_sm8750_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_sm8750_resets), + .gdscs =3D gpu_cc_sm8750_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_sm8750_gdscs), + .use_rpm =3D true, + .driver_data =3D &gpu_cc_sm8750_driver_data, +}; + +static const struct of_device_id gpu_cc_sm8750_match_table[] =3D { + { .compatible =3D "qcom,sm8750-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm8750_match_table); + +static int gpu_cc_sm8750_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gpu_cc_sm8750_desc); +} + +static struct platform_driver gpu_cc_sm8750_driver =3D { + .probe =3D gpu_cc_sm8750_probe, + .driver =3D { + .name =3D "sm8750-gpucc", + .of_match_table =3D gpu_cc_sm8750_match_table, + }, +}; +module_platform_driver(gpu_cc_sm8750_driver); + +MODULE_DESCRIPTION("QTI GPU_CC SM8750 Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/gxclkctl-kaanapali.c b/drivers/clk/qcom/gxclk= ctl-kaanapali.c index c209ce5fe4f003aabefd4421eb4f5662e257912a..d46243ee2ddaaa233361dc00a2f= 64d85ee4ebcaf 100644 --- a/drivers/clk/qcom/gxclkctl-kaanapali.c +++ b/drivers/clk/qcom/gxclkctl-kaanapali.c @@ -53,6 +53,7 @@ static const struct qcom_cc_desc gx_clkctl_kaanapali_desc= =3D { =20 static const struct of_device_id gx_clkctl_kaanapali_match_table[] =3D { { .compatible =3D "qcom,kaanapali-gxclkctl" }, + { .compatible =3D "qcom,sm8750-gxclkctl" }, { } }; MODULE_DEVICE_TABLE(of, gx_clkctl_kaanapali_match_table); --=20 2.34.1 From nobody Thu Apr 9 23:27:32 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BB2F384224 for ; Thu, 5 Mar 2026 10:40:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 05 Mar 2026 02:40:32 -0800 (PST) X-Received: by 2002:a17:902:db0f:b0:2ae:5745:f0e4 with SMTP id d9443c01a7336-2ae6aa0207bmr55854145ad.2.1772707231966; Thu, 05 Mar 2026 02:40:31 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ae4650000dsm134429325ad.54.2026.03.05.02.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 02:40:31 -0800 (PST) From: Taniya Das Date: Thu, 05 Mar 2026 16:10:10 +0530 Subject: [PATCH v5 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-gpucc_sm8750_v2-v5-3-78292b40b053@oss.qualcomm.com> References: <20260305-gpucc_sm8750_v2-v5-0-78292b40b053@oss.qualcomm.com> In-Reply-To: <20260305-gpucc_sm8750_v2-v5-0-78292b40b053@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-ORIG-GUID: IKMIi0qCnVdlx7mE7OXwMrsB4Qaf9fLK X-Proofpoint-GUID: IKMIi0qCnVdlx7mE7OXwMrsB4Qaf9fLK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDA4NiBTYWx0ZWRfX2zOfshz5fuhq ftcFLeeNYhLjJ0LyHEV1IlOAcoK5v+syVVgZaWsVyMKIwzbIPN91NtBnYORsdBct7HbeKQSshtm NknXjEYY/NCkITT8KhmRe87thiIQxP24MOZcm/On0c97+RAlUorREyJ+geCoqrV2N6jtpzU6x2p H2H2Zt9G1p1pvtY21/5Dy4Wt7Q9e7DcBD5KlhLyS11JLWpHu8kHKwIAu74VbTTQCHg02OC2b1k6 pUfUBDTtjA/9f1vaxjnHinQLb6vIz5O7QHJI7DUFZWKhBI8wMvZbWZAcv0XlKVmbX75DyaYFCKu h9KjXkaXlNqhKhELxQD3pjwfWsfQAWaT4TSIrCkG9awA97vjn3U6hsHgcqX4Jp/mrZNBYFFP8fv 9ISxYQXJ6MXe7/yrBMUP1oS+ehAuGx33BoSORJAQ+kMTv1M1ybOsfoTBdvKDVTy/9/sVJBumUUt N9xfAgO6E/LTTi7qlzA== X-Authority-Analysis: v=2.4 cv=N64k1m9B c=1 sm=1 tr=0 ts=69a95da1 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=CyMIzFe51rGKrm3YhSgA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-05_02,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 bulkscore=0 clxscore=1015 adultscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603050086 From: Konrad Dybcio Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this is simply a separate block housing the GX GDSC) nodes, required to power up the graphics-related hardware. Make use of it by enabling the associated IOMMU as well. The GPU itself needs some more work and will be enabled later. Reviewed-by: Abel Vesa Signed-off-by: Konrad Dybcio Co-developed-by: Taniya Das Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 68 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index f56b1f889b857a28859910f5c4465c8ce3473b00..0e7a343297e3f5d7a8189f50726= dc6279078c21c 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -4,7 +4,9 @@ */ =20 #include +#include #include +#include #include #include #include @@ -3001,6 +3003,34 @@ videocc: clock-controller@aaf0000 { #power-domain-cells =3D <1>; }; =20 + gxclkctl: clock-controller@3d64000 { + compatible =3D "qcom,sm8750-gxclkctl"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells =3D <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,sm8750-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + power-domains =3D <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm8750-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; @@ -4515,6 +4545,44 @@ tpdm_swao_out: endpoint { }; }; =20 + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,sm8750-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names =3D "hlos"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + apps_smmu: iommu@15000000 { compatible =3D "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg =3D <0x0 0x15000000 0x0 0x100000>; --=20 2.34.1