From nobody Thu Apr 9 21:52:49 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA79E3793DB for ; Thu, 5 Mar 2026 15:57:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772726264; cv=none; b=K+VFz091UlyovIsYtKhvm3bqIwoL5U+o64pAvKZZuCggGlTM0UUZS84S7nhKHBaTTk4MCn4udqLvskYsfYqfj6ahWoApJxabchkCcUUf0iWIoPZQMNnkGfkJYRM4RovmuifeR2Q8hmgjl4RwM5HUJQiu2qoCSvYdQT9whbZTkak= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772726264; c=relaxed/simple; bh=n72iIq4BxfaQ2rmNRuv1KqQ7vrrHsi4zGqlUhinuhJI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=ln4qFZMBnQiJP++t5iyi63dtDjXo1piQWboEx6lFCkx5rNYSH7bev4k6TyDbE0nd1b53le2d/aE4leyvpQT09mBDv+2CGqCp2ex0sL9NWjStAns6tcG/k11YoY1SStokdibsYrr2Lxj9R00ZN/HiXcJ2M3xxIzGaWh3zYFJ2jfQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=MuwUcQh7; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="MuwUcQh7" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id C2D9B4E42574; Thu, 5 Mar 2026 15:57:38 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 8A68D5FF89; Thu, 5 Mar 2026 15:57:38 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8A19510369758; Thu, 5 Mar 2026 16:57:34 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772726257; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding; bh=L9gUCJRXsHA1q2oaEh9yELbHN3zEBr7zj1d5W7vHJAs=; b=MuwUcQh7ZeMSlUZUsfM45WmvScWSjOqb6zBxmBvwPjfk0s8yNZUhlUfm1yHlDk2v9ZdnUp 0gZGEvTYPQ1IqrlmFLqXtqek1EgrV9EsWXxGkaMiSKI2MYouHSUG2WrhvYL8wE/5lxYth2 SKR7nH+K8MsDV+f1aTfJlJjuXpRo3s8IpjXTI4ninda/Y0V4/cRzOHb9fJs6x3bG6ScWDi 3A+CTMDTP1n8kIAj6kSlYDran8KXvtXlUlsJPysx+YTrS9Pnvg33ANcej+zcXQ2U8UPSUC duAJ/v/NN4Fvre+BgBWmWq4cOPqDtp5iJiUx2d/nMH3C22AmLouhH3uKl/jaVg== From: Gregory CLEMENT Date: Thu, 05 Mar 2026 16:57:32 +0100 Subject: [PATCH] phy: cadence: Sierra: Do not modify register when getting parent clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-fix_sierra_get_parent-v1-1-a7c18e9e6c58@bootlin.com> X-B4-Tracking: v=1; b=H4sIAOunqWkC/x2MSwqAMBDFriKztlA/9XcVkVLqU2dTZSoiiHe3u AwkeShCGJGG7CHBxZH3kKDIM/KbCysUz4mp1GWjK23UwreNDBFnV5z2cIJwqt53dWW8bwxaSu0 hSOL/Haf3/QB7Dg/7ZwAAAA== X-Change-ID: 20260305-fix_sierra_get_parent-9c8435cc65e7 To: Vinod Koul , Neil Armstrong , Aswath Govindraju , Swapnil Jakhade Cc: =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Petazzoni , linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Gregory CLEMENT X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The get_parent() callback for the PLL_CMNLC1 clock was incorrectly writing to the register while determining the parent clock index. This unintended register access forces the PHY back into training mode. If the PHY is already configured, this unexpected change prevents it from exiting training mode. Remove the register write operation to ensure the PHY remains stable during the get_parent() callback. Fixes: da08aab940092 ("phy: cadence: Sierra: Fix to get correct parent for = mux clocks") Signed-off-by: Gregory CLEMENT --- drivers/phy/cadence/phy-cadence-sierra.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence= /phy-cadence-sierra.c index 92ab1a31646ae..d4e8979c3abba 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -706,15 +706,10 @@ static u8 cdns_sierra_pll_mux_get_parent(struct clk_h= w *hw) =20 regmap_field_read(field, &val); =20 - if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) { + if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) index =3D clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC1]= , 0, val); - if (index =3D=3D 1) { - regmap_field_write(plllc1en_field, 1); - regmap_field_write(termen_field, 1); - } - } else { + else index =3D clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC],= 0, val); - } =20 return index; } --- base-commit: 11439c4635edd669ae435eec308f4ab8a0804808 change-id: 20260305-fix_sierra_get_parent-9c8435cc65e7 Best regards, --=20 Gr=C3=A9gory CLEMENT, Bootlin Embedded Linux and Kernel engineering https://bootlin.com