From nobody Thu Apr 9 23:25:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCF083A7F4E; Thu, 5 Mar 2026 14:40:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772721622; cv=none; b=fc4RVLpYytgapfe6yrja1qGS0NPEoTeNQ4aud+LfhtSKLOOc1UyqRlVmUTparVFqpthiz2sbrH045307vffaaL4QV7o6VnTmekByHJn+ueywyW3+jPOdKKgMPUQ7se5CUq64e8cpkZ5sGawoszOkCtR2CNiEBVXB6gVo0ScyvOI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772721622; c=relaxed/simple; bh=PbM85mGsMx4OQAX2YfPD5JAa646G0nfY5iMdJuDOzTY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Mn6unmIVlHTRXFf2DP7GePVb3HJlNzffF2Xy2DW9n4q1zlmbLeA1E3F7CSBizXnXwalKZCRTr8yinWr4kC+ud61BKXAb4vpSJz6ETxBWawV4Z1mxtOQ7gibPvXFN25aZXnPHz5BTSxIMbvpuXEHHPn7C7jg9p15WEnPXZiqHUhk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HQ0hachb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HQ0hachb" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8A98FC2BCB0; Thu, 5 Mar 2026 14:40:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772721622; bh=PbM85mGsMx4OQAX2YfPD5JAa646G0nfY5iMdJuDOzTY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=HQ0hachbv1K+WvoM4jqgkusyS72URaHgr27aw9UZJXOg15kj+KDS/DHDvYNTwAosB 33Cuh23mLIf06/ubKtC8s0fVeElbbTFlQA7AQWjdWKCvxrLwGUcZiyzp+I5Z9p0DEU j2P6QVlIMa89tuaCvjY9CffHUf0uUKbi2X5+GmCqjAvMaXvhfahRmikjpLztmCSui6 0WbGb6XrNwkv9tHnY7e20e65YGNEh/aN89+qjY+yZuMm57Yd4SNWA+L7CZzrzz5Ips w/GAB4zXFDBKPIUTezrZUahWgsFCAxTtMYpOs3OhjMt0kgJGZZ+AbM2zOWAP4ftKWH Oa3zlQGGyXBTQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78C91F33A79; Thu, 5 Mar 2026 14:40:22 +0000 (UTC) From: Cory Keitz via B4 Relay Date: Thu, 05 Mar 2026 14:40:13 +0000 Subject: [PATCH 2/2] i2c: qcom-cci: Add DT property for SCL clock stretching Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-cci-scl-stretch-v1-2-8412abc65745@amazon.com> References: <20260305-cci-scl-stretch-v1-0-8412abc65745@amazon.com> In-Reply-To: <20260305-cci-scl-stretch-v1-0-8412abc65745@amazon.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Cory Keitz X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772721622; l=1731; i=ckeitz@amazon.com; s=20260304; h=from:subject:message-id; bh=OwT3G4Wpy7L8KSSJSz2LODppXx7Vr9o7XgiwykQqPqU=; b=Y/sFC7CPtrdfbIbHxNIKks1+lYC88LTW/5BKg8Nn+9ZeRLLWP+0geVubpKbswUAB3aHUnX7iR rKHVbnFZCpIDswR5NiCI6o6VOHOHtmBR5msi55ZTF6iU5XHPID42C/Q X-Developer-Key: i=ckeitz@amazon.com; a=ed25519; pk=IWSPbPI9mzOdPU5zG2ROe/O75E4ckVxuBLNJVYVZCag= X-Endpoint-Received: by B4 Relay for ckeitz@amazon.com/20260304 with auth_id=662 X-Original-From: Cory Keitz Reply-To: ckeitz@amazon.com From: Cory Keitz The CCI hardware supports an SCL clock stretch enable bit in the MISC_CTL register, but the driver hardcodes it off for most SoC variants. This makes the bus driver unstable for configurations which rely on clock stretching. Notably, GMSL uses clock stretching to absorb the latency of transaction forwarding across the link. Add a per-master "qcom,scl-stretch-enable" boolean DT property that ORs with the existing hw_params default, allowing clock stretching to be enabled on individual CCI masters without affecting others. Signed-off-by: Cory Keitz --- drivers/i2c/busses/i2c-qcom-cci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qco= m-cci.c index 884055df1560..022c10b310a0 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -111,6 +111,7 @@ struct cci_master { struct i2c_adapter adap; u16 master; u8 mode; + bool scl_stretch_en; int status; struct completion irq_complete; struct cci *cci; @@ -284,7 +285,8 @@ static int cci_init(struct cci *cci) val =3D hw->tbuf; writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_2(i)); =20 - val =3D hw->scl_stretch_en << 8 | hw->trdhld << 4 | hw->tsp; + val =3D (hw->scl_stretch_en | cci->master[i].scl_stretch_en) << 8 | + hw->trdhld << 4 | hw->tsp; writel(val, cci->base + CCI_I2C_Mm_MISC_CTL(i)); } =20 @@ -572,6 +574,9 @@ static int cci_probe(struct platform_device *pdev) master->mode =3D I2C_MODE_FAST_PLUS; } =20 + master->scl_stretch_en =3D + of_property_read_bool(child, "qcom,scl-stretch-enable"); + init_completion(&master->irq_complete); } =20 --=20 2.47.3