From nobody Thu Apr 9 23:26:09 2026 Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A68736CE0D for ; Thu, 5 Mar 2026 11:35:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772710530; cv=none; b=D4TMAGoQZT4BCXqy2Q31P1/LvkzR9F6y4cuKnk7GL+i6FOKgh0C06Q2G1U9ktvO/LK7R84sbsE1CgL4oEMZopflZ8j0sOK9TvW0S4MzOHOMGuMnFOPdV5tW6dYP3CdCF6xfOFq3nGkYLiJvebvSytC+hcHYQGI4jcxfqCa1ncIs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772710530; c=relaxed/simple; bh=3lZJ170S8zrsun7Jh3wItDtUCQJImaUgulKM+XWejhU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Zug/2X9E5+YD2pOQlfVRxbAGFYSirlQb/aSBU57rgpvTaCSefUBWwbCpiU7efiP0ED0+/qISmZ40zwq1HVLXre+IjB7HRSUsjTXSg/9il/xSSebTdq0VFr5mWQVSOaK32nR5dnX7mMPSMDeuOMiE3KBcJUmBiXHwl0ba5X+5A1c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com; spf=pass smtp.mailfrom=imgtec.com; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b=LA8+6oDY; arc=none smtp.client-ip=91.207.212.86 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=imgtec.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b="LA8+6oDY" Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 625701nh2402044; Thu, 5 Mar 2026 11:07:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=v 9LXvk7AYhEAMjwGCgZR3SACmCL+dJCjkYqhwKueTAY=; b=LA8+6oDY61C7JWJ9e gjxLI0xT3xeGdhcbE88C5EeZ8X+xQOSU0VM/ba+CtNDks2Ot9+ihyGM9Qb+I+JSG azy8rDV1A0T9p/zWMw8jjpLXL6pxpttKATGmRRQXMdrr26gpGpdmdkWIoyG32O8R SkLhoOlZuSCvLAuijWtFBByAcN8UF3qgwb9GW4gKHPGe8y23QqbvefoMWrA3telL pXJmrjMoONaBQYWztI7KnLn9RCEeNvtySpIrr4thhKR6ZF/LdJgtSvf84P6KgU7v N+lgAQdiqY8RRKqeeKP5XpqcIoUoLvv0guYzCj1T0fDz0AeI34/cl2Z78vR4v9GC UUhVg== Received: from hhmail01.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 4ckqgrv073-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Mar 2026 11:07:26 +0000 (GMT) Received: from NP-G-BRAJESH.pu.imgtec.org (172.25.128.150) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.37; Thu, 5 Mar 2026 11:07:23 +0000 From: Brajesh Gupta Date: Thu, 5 Mar 2026 11:06:17 +0000 Subject: [PATCH 2/2] drm/imagination: Skip 2nd thread DM association for non META Firmware Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260305-b4-staging-layout_mars_base-v1-2-09831fa17cef@imgtec.com> References: <20260305-b4-staging-layout_mars_base-v1-0-09831fa17cef@imgtec.com> In-Reply-To: <20260305-b4-staging-layout_mars_base-v1-0-09831fa17cef@imgtec.com> To: Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Alessio Belle , Alexandru Dadu CC: , , "Brajesh Gupta" X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772708838; l=1623; i=brajesh.gupta@imgtec.com; s=20260107; h=from:subject:message-id; bh=3lZJ170S8zrsun7Jh3wItDtUCQJImaUgulKM+XWejhU=; b=pd56H51WHcR5/FunymyCUS7A8pXsEpohsPu0W6uG2zc8O5HjPnODqkohkZPmjXiA2o68rA/B7 xC3zsYXjhEHAmw861eqOCiWhBc7hzJum7+xKbC3xctWHlnoFF/NWIwt X-Developer-Key: i=brajesh.gupta@imgtec.com; a=ed25519; pk=mxdDr22E/sHiu68U/bLe0W/SRYi3i848ZgoBuEyk21E= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDA4OCBTYWx0ZWRfXw9CAOdvAR2m7 Qbpnq9Ma89ZEq6YbqvHXFHvTbjONicSNWd+6MK4k7l2bRAp7zk2vDgL7AsJaFpg8x6psw2lnlGo VJdAzt4JfE3ziwEfqBGJ6oOLY/v7ufBWSJSiFOL42Ou1B+pwBQAgk761BHuyISprmBlBCYtcobW D//aCl5vSrFw/qUct66BGEzp7O1HjmhQ7FX5JLxgmjdpO722ANOortL8xkNvuGcBbjWjTjXMjrX bGxqT3M0kMimT1NMsGG4ruaXmxrYRZiBsy5QFCUH+4Spt4wE0e3cGmj43kXa3K1PbqEYn1uHxHj eBndRudhZdH5X2j/BIlCMVK9niMMgTwzMC4jY3GmOvE5cVP7/m+ICZiL6ZXmepzIbWLQgf/xVXo o9ejujV4tWj0+elf7QY8Rxx6H0UNM1MhbpSUf21UGcR5q7EkLZMMIvaGRuRQj45a8VGAnZII96L LeTjPTWWbitUZx/xJ1w== X-Proofpoint-ORIG-GUID: PVfz9kub7_tzqLY87mCliZm8A9h-eXpt X-Authority-Analysis: v=2.4 cv=GbAaXAXL c=1 sm=1 tr=0 ts=69a963ee cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=aSvOoEy96_oA:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=kQ-hrUj2-E3RCbRHssb7:22 a=qZQ2PDNLMSdLoqI-hfl9:22 a=r_1tXGB3AAAA:8 a=RMA9JOuqd9HpLUXpPykA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: PVfz9kub7_tzqLY87mCliZm8A9h-eXpt Only a META firmware can have two threads. Signed-off-by: Brajesh Gupta --- drivers/gpu/drm/imagination/pvr_fw_startstop.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/d= rm/imagination/pvr_fw_startstop.c index ce089f51f06a..3bca57cbaaf0 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c +++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c @@ -242,12 +242,14 @@ pvr_fw_stop(struct pvr_device *pvr_dev) ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL & ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK); =20 - pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, - ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL & - ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); - pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, - ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL & - ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); + if (pvr_dev->fw_dev.processor_type =3D=3D PVR_FW_PROCESSOR_TYPE_META) { + pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, + ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL & + ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); + pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, + ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL & + ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); + } =20 /* Extra Idle checks. */ err =3D pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIF_STATUS_MMU, 0, --=20 2.43.0