From nobody Thu Apr 9 21:52:42 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EF3539A7EC; Thu, 5 Mar 2026 12:23:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772713415; cv=none; b=VGR90J3NSoQ6QaDya8UOhKBugBUxVPVGp2KJ9xd2gFUAx44HIGy6BMHNX82cqi2sNNAv9e/bTr5UweE0tesGMgdwgey8MrkVqwG+4W3S0k9V6RwFJJOnpPDMB7u0HnZ/RXKaAfImTSGzJmazrPs9EuWv5VBFyYbaPeqnUx5todU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772713415; c=relaxed/simple; bh=MRMcRh6OYKlvw86W26MLmjms1YLqtLMi4wr68wds6UU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nFMRh8rLhfPhJfqCto1UYv2PyL/abAAUXz6XwIRSWPoqYkgQco8w/Q6r0vYklksicrPtcXd6Ce75whWF9pmeYxI3/eprpRW8u0hzTsMtMAibiwpHohiGPDP7bnaCB+jxfnLDWuqevtuL9fiOmXtBkZ6WeJMoJY81M5Cddih6Oxk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bdfs+4PC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bdfs+4PC" Received: by smtp.kernel.org (Postfix) with ESMTPS id 43081C2BC87; Thu, 5 Mar 2026 12:23:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772713415; bh=MRMcRh6OYKlvw86W26MLmjms1YLqtLMi4wr68wds6UU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=bdfs+4PCSKnuT1+OluZ50TWpc2guMBpUSOGLrOfRlDRGCLTvXP+AQmbt8vyHIftEK hAHYcKNhGuqZ/cYR77WYQlJH9xLWHBijSE0jNqeSiVeylbb3BI5diNLob4zDfzJ3ra GYFnO4S73sJuPJqL67GFNejHKBI7nkE/WBw1QarWn8Sh7OqX+RvyAQcM389cjiMeZw s3hq8XJ647YAyWiH9R+AWTxBTl2evLaWb++wq2elAGtbI4c50sej4b0Jd54EwlQlRO D2mIxlva/EaubFNiJTIZHutktyZOYwYfa84r3xHLcD/98UA32j2QhHBExa8HW21LI5 GtNFl0fw5FO3A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CACAF30956; Thu, 5 Mar 2026 12:23:35 +0000 (UTC) From: Radu Sabau via B4 Relay Date: Thu, 05 Mar 2026 14:23:27 +0200 Subject: [PATCH 1/4] dt-bindings: iio: adc: add bindings for AD4691 family Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-ad4692-multichannel-sar-adc-driver-v1-1-336229a8dcc7@analog.com> References: <20260305-ad4692-multichannel-sar-adc-driver-v1-0-336229a8dcc7@analog.com> In-Reply-To: <20260305-ad4692-multichannel-sar-adc-driver-v1-0-336229a8dcc7@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772713413; l=10122; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=lsINb5qT8O5iLIY36KaeYf7LKPIGXET2nXgZufTpeWU=; b=AX6kACPh4Wvnmru2wcsCLTF6WOCvYBofqGrkbFkq7sq110JY0cEdluBcLZ8ecbDNgBQO5Fp40 f5SRk0xp+VjCk3/6ncUahK1V/DW/u+pp26YpMZL7vytcaDrbDsoaCfu X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add YAML bindings and dt-bindings header for the Analog Devices AD4691 family of multichannel SAR ADCs (AD4691, AD4692, AD4693, AD4694). The binding describes five operating modes selectable via the adi,spi-mode property, optional PWM/clock for CNV Clock and CNV Burst modes, GPIO pins, voltage supplies and the trigger-source interface for SPI Engine offload operation. Signed-off-by: Radu Sabau --- .../devicetree/bindings/iio/adc/adi,ad4691.yaml | 278 +++++++++++++++++= ++++ MAINTAINERS | 8 + include/dt-bindings/iio/adc/adi,ad4691.h | 13 + 3 files changed, 299 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4691.yaml new file mode 100644 index 000000000000..b0d8036184b0 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml @@ -0,0 +1,278 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4691.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4691 Family Multichannel SAR ADCs + +maintainers: + - Radu Sabau + +description: | + The AD4691 family are high-speed, low-power, multichannel successive + approximation register (SAR) analog-to-digital converters (ADCs) with + an SPI-compatible serial interface. The family supports multiple operati= ng + modes including CNV Clock Mode, CNV Burst Mode, Autonomous Mode, SPI Bur= st + Mode, and Manual Mode. + + The driver supports both standard SPI and SPI Engine (offload) operation. + + Datasheets: + * https://www.analog.com/en/products/ad4692.html + * https://www.analog.com/en/products/ad4691.html + * https://www.analog.com/en/products/ad4694.html + * https://www.analog.com/en/products/ad4693.html + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad4691 + - adi,ad4692 + - adi,ad4693 + - adi,ad4694 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 40000000 + + spi-cpol: true + spi-cpha: true + + adi,spi-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4] + description: | + Selects the ADC operating mode: + 0 - CNV Clock Mode: External PWM drives CNV pin, samples at PWM ra= te. + 1 - CNV Burst Mode: PWM triggers burst cycles, internal oscillator + drives conversions within each burst. + 2 - Autonomous Mode: Internal oscillator drives conversions, softw= are + starts/stops via register write. + 3 - SPI Burst Mode: Similar to Autonomous Mode but optimized for + SPI burst reads. + 4 - Manual Mode: CNV is directly tied to SPI CS. Each SPI transfer + triggers a conversion and returns previous result (pipelined). + + vio-supply: + description: I/O voltage supply (1.71V to 1.89V or VDD). + + vref-supply: + description: + External reference voltage supply (2.4V to 5.25V). Mutually exclusive + with vrefin-supply. + + vrefin-supply: + description: + Internal reference buffer input supply. Mutually exclusive with + vref-supply. + + reset-gpios: + description: GPIO connected to the RESET pin (active high). + maxItems: 1 + + gp0-gpios: + description: + GPIO connected to the GP0 pin. Required for non-offload operation to + receive DATA_READY or BUSY interrupts. For SPI Engine offload, this + is optional as the trigger is provided by the SPI offload subsystem. + maxItems: 1 + + gp1-gpios: + description: GPIO connected to the GP1 pin. + maxItems: 1 + + gp2-gpios: + description: GPIO connected to the GP2 pin. + maxItems: 1 + + gp3-gpios: + description: GPIO connected to the GP3 pin. + maxItems: 1 + + clocks: + description: Reference clock for PWM timing in CNV Clock and CNV Burst= modes. + maxItems: 1 + + clock-names: + items: + - const: ref_clk + + pwms: + description: + PWM connected to the CNV pin. Required for CNV Clock Mode and CNV Bu= rst + Mode to control conversion timing. + maxItems: 1 + + pwm-names: + items: + - const: cnv + + interrupts: + description: + Interrupt from the GP0 pin configured as DATA_READY or BUSY. Required + for non-offload operation in all modes except Manual Mode (mode 4), + where CNV is tied to CS and no DATA_READY signal is generated. + maxItems: 1 + + interrupt-names: + items: + - const: DRDY + + '#trigger-source-cells': + description: | + For SPI Engine offload operation, this node acts as a trigger source. + Two cells are required: + - First cell: Trigger event type (0 =3D BUSY, 1 =3D DATA_READY) + - Second cell: GPIO pin number (only 0 =3D GP0 is supported) + + Macros are available in dt-bindings/iio/adc/adi,ad4691.h: + AD4691_TRIGGER_EVENT_BUSY, AD4691_TRIGGER_EVENT_DATA_READY + AD4691_TRIGGER_PIN_GP0 + const: 2 + +required: + - compatible + - reg + - adi,spi-mode + - vio-supply + - reset-gpios + +allOf: + # vref-supply and vrefin-supply are mutually exclusive, one is required + - oneOf: + - required: + - vref-supply + - required: + - vrefin-supply + + # AD4694 (20-bit) does not support Manual Mode + - if: + properties: + compatible: + const: adi,ad4694 + then: + properties: + adi,spi-mode: + enum: [0, 1, 2, 3] + + # CNV Clock Mode and CNV Burst Mode require PWM and clock + - if: + properties: + adi,spi-mode: + enum: [0, 1] + then: + required: + - clocks + - clock-names + - pwms + - pwm-names + + # Non-Manual modes (0-3) without SPI offload require a DRDY interrupt. + # Offload configurations expose '#trigger-source-cells' instead. + - if: + properties: + adi,spi-mode: + enum: [0, 1, 2, 3] + not: + required: + - '#trigger-source-cells' + then: + required: + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + /* Example: AD4692 in CNV Clock Mode with standard SPI */ + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4692"; + reg =3D <0>; + spi-cpol; + spi-cpha; + spi-max-frequency =3D <40000000>; + + adi,spi-mode =3D <0>; /* CNV Clock Mode */ + + vio-supply =3D <&vio_supply>; + vref-supply =3D <&vref_5v>; + + reset-gpios =3D <&gpio 10 GPIO_ACTIVE_HIGH>; + gp0-gpios =3D <&gpio 11 GPIO_ACTIVE_HIGH>; + + clocks =3D <&ref_clk>; + clock-names =3D "ref_clk"; + + pwms =3D <&pwm_gen 0 0>; + pwm-names =3D "cnv"; + + interrupts =3D <12 4>; + interrupt-names =3D "DRDY"; + }; + }; + + - | + #include + #include + + /* Example: AD4692 in Manual Mode with SPI Engine offload */ + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4692"; + reg =3D <0>; + spi-cpol; + spi-cpha; + spi-max-frequency =3D <31250000>; + + adi,spi-mode =3D <4>; /* Manual Mode */ + + vio-supply =3D <&vio_supply>; + vrefin-supply =3D <&vrefin_supply>; + + reset-gpios =3D <&gpio 10 GPIO_ACTIVE_HIGH>; + }; + }; + + - | + #include + #include + + /* Example: AD4691 in Autonomous Mode with SPI Engine offload trigger = */ + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4691"; + reg =3D <0>; + spi-cpol; + spi-cpha; + spi-max-frequency =3D <40000000>; + + adi,spi-mode =3D <2>; /* Autonomous Mode */ + + vio-supply =3D <&vio_supply>; + vref-supply =3D <&vref_5v>; + + reset-gpios =3D <&gpio 10 GPIO_ACTIVE_HIGH>; + gp0-gpios =3D <&gpio 11 GPIO_ACTIVE_HIGH>; + + #trigger-source-cells =3D <2>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 61bf550fd37c..9994d107d88d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1484,6 +1484,14 @@ W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4170-4.yaml F: drivers/iio/adc/ad4170-4.c =20 +ANALOG DEVICES INC AD4691 DRIVER +M: Radu Sabau +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml +F: include/dt-bindings/iio/adc/adi,ad4691.h + ANALOG DEVICES INC AD4695 DRIVER M: Michael Hennerich M: Nuno S=C3=A1 diff --git a/include/dt-bindings/iio/adc/adi,ad4691.h b/include/dt-bindings= /iio/adc/adi,ad4691.h new file mode 100644 index 000000000000..294b03974f48 --- /dev/null +++ b/include/dt-bindings/iio/adc/adi,ad4691.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_ADI_AD4691_H +#define _DT_BINDINGS_ADI_AD4691_H + +/* Trigger event types */ +#define AD4691_TRIGGER_EVENT_BUSY 0 +#define AD4691_TRIGGER_EVENT_DATA_READY 1 + +/* Trigger GPIO pin selection */ +#define AD4691_TRIGGER_PIN_GP0 0 + +#endif /* _DT_BINDINGS_ADI_AD4691_H */ --=20 2.43.0 From nobody Thu Apr 9 21:52:42 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 959AF37416A; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-ad4692-multichannel-sar-adc-driver-v1-2-336229a8dcc7@analog.com> References: <20260305-ad4692-multichannel-sar-adc-driver-v1-0-336229a8dcc7@analog.com> In-Reply-To: <20260305-ad4692-multichannel-sar-adc-driver-v1-0-336229a8dcc7@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772713413; l=37439; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=TCWKolk7iMtcppe+0vro0WVACPHBWNzsay83Ne7LSFM=; b=60+4pm7LNhsC1r8PuSu8OanhZBih6oZbQYsJe4ozbI62o0aCPsF7eclVjM/8r7iKJJ2PyeMhB EfTnfhbM9yRB16e5FZtXteaxpSXTv4xJzOs1o6UioTH+8ZZGH/iKFnI X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add support for the Analog Devices AD4691 family of high-speed, low-power multichannel SAR ADCs: AD4691 (16-ch, 500 kSPS), AD4692 (16-ch, 1 MSPS), AD4693 (8-ch, 500 kSPS) and AD4694 (8-ch, 1 MSPS). The driver implements a custom regmap layer over raw SPI to handle the device's mixed 1/2/3/4-byte register widths and uses the standard IIO read_raw/write_raw interface for single-channel reads. Five operating modes are supported: - CNV Clock Mode: external PWM drives CNV; sampling rate set via PWM period - CNV Burst Mode: PWM triggers burst cycles; internal oscillator drives conversions within each burst - Autonomous Mode: internal oscillator drives conversions; started/stopped via register write - SPI Burst Mode: like Autonomous but optimised for SPI burst reads - Manual Mode: CNV tied to SPI CS; pipelined protocol; Signed-off-by: Radu Sabau --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 11 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad4691.c | 1196 ++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 1209 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9994d107d88d..5325f7d3b7f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1490,6 +1490,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml +F: drivers/iio/adc/ad4691.c F: include/dt-bindings/iio/adc/adi,ad4691.h =20 ANALOG DEVICES INC AD4695 DRIVER diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 60038ae8dfc4..3685a03aa8dc 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -139,6 +139,17 @@ config AD4170_4 To compile this driver as a module, choose M here: the module will be called ad4170-4. =20 +config AD4691 + tristate "Analog Devices AD4691 Family ADC Driver" + depends on SPI + select REGMAP + help + Say yes here to build support for Analog Devices AD4691 Family MuxSAR + SPI analog to digital converters (ADC). + + To compile this driver as a module, choose M here: the module will be + called ad4691. + config AD4695 tristate "Analog Device AD4695 ADC Driver" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index c76550415ff1..4ac1ea09d773 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_AD4080) +=3D ad4080.o obj-$(CONFIG_AD4130) +=3D ad4130.o obj-$(CONFIG_AD4134) +=3D ad4134.o obj-$(CONFIG_AD4170_4) +=3D ad4170-4.o +obj-$(CONFIG_AD4691) +=3D ad4691.o obj-$(CONFIG_AD4695) +=3D ad4695.o obj-$(CONFIG_AD4851) +=3D ad4851.o obj-$(CONFIG_AD7091R) +=3D ad7091r-base.o diff --git a/drivers/iio/adc/ad4691.c b/drivers/iio/adc/ad4691.c new file mode 100644 index 000000000000..dee8bc312d44 --- /dev/null +++ b/drivers/iio/adc/ad4691.c @@ -0,0 +1,1196 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2024-2026 Analog Devices, Inc. + * Author: Radu Sabau + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#define AD4691_NUM_REGULATORS 1 +#define AD4691_MAX_ADC_MODE 4 + +#define AD4691_VREF_MIN 2400000 +#define AD4691_VREF_MAX 5250000 + +/* + * Default sampling frequency for MANUAL_MODE. + * Each sample needs (num_channels + 1) SPI transfers of 24 bits. + * The factor 36 =3D 24 * 3/2 folds in a 50% scheduling margin: + * freq =3D spi_hz / (24 * 3/2 * (num_channels + 1)) + * =3D spi_hz / (36 * (num_channels + 1)) + */ +#define AD4691_MANUAL_MODE_STD_FREQ(x, y) ((y) / (36 * ((x) + 1))) +#define AD4691_CNV_DUTY_CYCLE_NS 380 +#define AD4691_MAX_CONV_PERIOD_US 800 + +#define AD4691_SEQ_ALL_CHANNELS_OFF 0x00 +#define AD4691_STATE_RESET_ALL 0x01 + +#define AD4691_REF_CTRL_MASK GENMASK(4, 2) + +#define AD4691_DEVICE_MANUAL 0x14 + +#define AD4691_NOOP 0x00 +#define AD4691_ADC_CHAN(ch) ((0x10 + (ch)) << 3) + +#define AD4691_PRODUCT_ID_LSB_REG 0x04 + +#define AD4691_STATUS_REG 0x14 +#define AD4691_CLAMP_STATUS1_REG 0x1A +#define AD4691_CLAMP_STATUS2_REG 0x1B +#define AD4691_DEVICE_SETUP 0x20 +#define AD4691_REF_CTRL 0x21 +#define AD4691_OSC_FREQ_REG 0x23 +#define AD4691_STD_SEQ_CONFIG 0x25 +#define AD4691_SPARE_CONTROL 0x2A + +#define AD4691_OSC_EN_REG 0x180 +#define AD4691_STATE_RESET_REG 0x181 +#define AD4691_ADC_SETUP 0x182 +#define AD4691_ACC_MASK1_REG 0x184 +#define AD4691_ACC_MASK2_REG 0x185 +#define AD4691_ACC_COUNT_LIMIT(n) (0x186 + (n)) +#define AD4691_ACC_COUNT_VAL 0x3F +#define AD4691_GPIO_MODE1_REG 0x196 +#define AD4691_GPIO_MODE2_REG 0x197 +#define AD4691_GPIO_READ 0x1A0 +#define AD4691_ACC_STATUS_FULL1_REG 0x1B0 +#define AD4691_ACC_STATUS_FULL2_REG 0x1B1 +#define AD4691_ACC_STATUS_OVERRUN1_REG 0x1B2 +#define AD4691_ACC_STATUS_OVERRUN2_REG 0x1B3 +#define AD4691_ACC_STATUS_SAT1_REG 0x1B4 +#define AD4691_ACC_STATUS_SAT2_REG 0x1BE +#define AD4691_ACC_SAT_OVR_REG(n) (0x1C0 + (n)) +#define AD4691_AVG_IN(n) (0x201 + (2 * (n))) +#define AD4691_AVG_STS_IN(n) (0x222 + (3 * (n))) +#define AD4691_ACC_IN(n) (0x252 + (3 * (n))) +#define AD4691_ACC_STS_DATA(n) (0x283 + (4 * (n))) + +#define AD4691_CHANNEL(chan, index, real_bits, storage_bits, _shift) \ + { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) \ + | BIT(IIO_CHAN_INFO_SCALE), \ + .channel =3D chan, \ + .scan_index =3D index, \ + .scan_type =3D { \ + .sign =3D 'u', \ + .realbits =3D real_bits, \ + .storagebits =3D storage_bits, \ + .shift =3D _shift, \ + }, \ + } + +enum ad4691_ids { + AD4691_ID_AD4691, + AD4691_ID_AD4692, + AD4691_ID_AD4693, + AD4691_ID_AD4694, +}; + +enum ad4691_adc_mode { + AD4691_CNV_CLOCK_MODE, + AD4691_CNV_BURST_MODE, + AD4691_AUTONOMOUS_MODE, + AD4691_SPI_BURST_MODE, + AD4691_MANUAL_MODE, +}; + +enum ad4691_gpio_mode { + AD4691_HIGH_Z, + AD4691_DIGITAL_OUTPUT_LOW, + AD4691_DIGITAL_OUTPUT_HIGH, + AD4691_DIGITAL_INPUT, + AD4691_ADC_BUSY, + AD4691_SEQ_DONE, + AD4691_DATA_READY, + AD4691_ACC_OVR_ERROR, + AD4691_ACC_SAT_ERROR, +}; + +enum ad4691_int_osc_freq { + AD4691_OSC_1MHZ =3D 0, + AD4691_OSC_500KHZ, + AD4691_OSC_400KHZ, + AD4691_OSC_250KHZ, + AD4691_OSC_200KHZ, + AD4691_OSC_167KHZ, + AD4691_OSC_133KHZ, + AD4691_OSC_125KHZ, + AD4691_OSC_100KHZ, + AD4691_OSC_50KHZ, + AD4691_OSC_25KHZ, + AD4691_OSC_12P5KHZ, + AD4691_OSC_10KHZ, + AD4691_OSC_5KHZ, + AD4691_OSC_2P5KHZ, + AD4691_OSC_1P25KHZ, +}; + +enum ad4691_ref_ctrl { + AD4691_VREF_2P5 =3D 0, + AD4691_VREF_3P0, + AD4691_VREF_3P3, + AD4691_VREF_4P096, + AD4691_VREF_5P0, +}; + +static int ad4691_int_osc_val[] =3D { + [AD4691_OSC_1MHZ] =3D 1000000, + [AD4691_OSC_500KHZ] =3D 500000, + [AD4691_OSC_400KHZ] =3D 400000, + [AD4691_OSC_250KHZ] =3D 250000, + [AD4691_OSC_200KHZ] =3D 200000, + [AD4691_OSC_167KHZ] =3D 167000, + [AD4691_OSC_133KHZ] =3D 133000, + [AD4691_OSC_125KHZ] =3D 125000, + [AD4691_OSC_100KHZ] =3D 100000, + [AD4691_OSC_50KHZ] =3D 50000, + [AD4691_OSC_25KHZ] =3D 25000, + [AD4691_OSC_12P5KHZ] =3D 12500, + [AD4691_OSC_10KHZ] =3D 10000, + [AD4691_OSC_5KHZ] =3D 5000, + [AD4691_OSC_2P5KHZ] =3D 2500, + [AD4691_OSC_1P25KHZ] =3D 1250, +}; + +struct ad4691_chip_info { + const struct iio_chan_spec *channels; + const char *name; + u8 product_id; + int num_channels; + int max_rate; +}; + +static const struct iio_chan_spec ad4691_channels[] =3D { + AD4691_CHANNEL(0, 0, 16, 32, 0), + AD4691_CHANNEL(1, 1, 16, 32, 0), + AD4691_CHANNEL(2, 2, 16, 32, 0), + AD4691_CHANNEL(3, 3, 16, 32, 0), + AD4691_CHANNEL(4, 4, 16, 32, 0), + AD4691_CHANNEL(5, 5, 16, 32, 0), + AD4691_CHANNEL(6, 6, 16, 32, 0), + AD4691_CHANNEL(7, 7, 16, 32, 0), + AD4691_CHANNEL(8, 8, 16, 32, 0), + AD4691_CHANNEL(9, 9, 16, 32, 0), + AD4691_CHANNEL(10, 10, 16, 32, 0), + AD4691_CHANNEL(11, 11, 16, 32, 0), + AD4691_CHANNEL(12, 12, 16, 32, 0), + AD4691_CHANNEL(13, 13, 16, 32, 0), + AD4691_CHANNEL(14, 14, 16, 32, 0), + AD4691_CHANNEL(15, 15, 16, 32, 0) +}; + +static const struct iio_chan_spec ad4693_channels[] =3D { + AD4691_CHANNEL(0, 0, 16, 32, 0), + AD4691_CHANNEL(1, 1, 16, 32, 0), + AD4691_CHANNEL(2, 2, 16, 32, 0), + AD4691_CHANNEL(3, 3, 16, 32, 0), + AD4691_CHANNEL(4, 4, 16, 32, 0), + AD4691_CHANNEL(5, 5, 16, 32, 0), + AD4691_CHANNEL(6, 6, 16, 32, 0), + AD4691_CHANNEL(7, 7, 16, 32, 0) +}; + +static const struct iio_chan_spec ad4691_manual_channels[] =3D { + AD4691_CHANNEL(0, 0, 16, 24, 8), + AD4691_CHANNEL(1, 1, 16, 24, 8), + AD4691_CHANNEL(2, 2, 16, 24, 8), + AD4691_CHANNEL(3, 3, 16, 24, 8), + AD4691_CHANNEL(4, 4, 16, 24, 8), + AD4691_CHANNEL(5, 5, 16, 24, 8), + AD4691_CHANNEL(6, 6, 16, 24, 8), + AD4691_CHANNEL(7, 7, 16, 24, 8), + AD4691_CHANNEL(8, 8, 16, 24, 8), + AD4691_CHANNEL(9, 9, 16, 24, 8), + AD4691_CHANNEL(10, 10, 16, 24, 8), + AD4691_CHANNEL(11, 11, 16, 24, 8), + AD4691_CHANNEL(12, 12, 16, 24, 8), + AD4691_CHANNEL(13, 13, 16, 24, 8), + AD4691_CHANNEL(14, 14, 16, 24, 8), + AD4691_CHANNEL(15, 15, 16, 24, 8) +}; + +static const struct iio_chan_spec ad4693_manual_channels[] =3D { + AD4691_CHANNEL(0, 0, 16, 24, 8), + AD4691_CHANNEL(1, 1, 16, 24, 8), + AD4691_CHANNEL(2, 2, 16, 24, 8), + AD4691_CHANNEL(3, 3, 16, 24, 8), + AD4691_CHANNEL(4, 4, 16, 24, 8), + AD4691_CHANNEL(5, 5, 16, 24, 8), + AD4691_CHANNEL(6, 6, 16, 24, 8), + AD4691_CHANNEL(7, 7, 16, 24, 8) +}; + +static const struct ad4691_chip_info ad4691_chips[] =3D { + [AD4691_ID_AD4691] =3D { + .channels =3D ad4691_channels, + .name =3D "ad4691", + .product_id =3D 0x11, + .num_channels =3D ARRAY_SIZE(ad4691_channels), + .max_rate =3D 500000, + }, + [AD4691_ID_AD4692] =3D { + .channels =3D ad4691_channels, + .name =3D "ad4692", + .product_id =3D 0x12, + .num_channels =3D ARRAY_SIZE(ad4691_channels), + .max_rate =3D 1000000, + }, + [AD4691_ID_AD4693] =3D { + .channels =3D ad4693_channels, + .name =3D "ad4693", + .product_id =3D 0x13, + .num_channels =3D ARRAY_SIZE(ad4693_channels), + .max_rate =3D 500000, + }, + [AD4691_ID_AD4694] =3D { + .channels =3D ad4693_channels, + .name =3D "ad4694", + .product_id =3D 0x14, + .num_channels =3D ARRAY_SIZE(ad4693_channels), + .max_rate =3D 1000000, + }, +}; + +struct ad4691_state { + const struct ad4691_chip_info *chip; + struct spi_device *spi; + struct regmap *regmap; + + unsigned long ref_clk_rate; + struct pwm_device *conv_trigger; + + struct regulator_bulk_data regulators[AD4691_NUM_REGULATORS]; + + enum ad4691_adc_mode adc_mode; + + int vref; + u64 cnv_period; + /* + * Synchronize access to members of the driver state, and ensure + * atomicity of consecutive SPI operations. + */ + struct mutex lock; + + ktime_t sampling_period; + + /* DMA (thus cache coherency maintenance) may require the + * transfer buffers to live in their own cache lines. + * Make the buffer large enough for one 24 bit sample and one 64 bit + * aligned 64 bit timestamp. + */ + unsigned char rx_data[ALIGN(3, sizeof(s64)) + sizeof(s64)] __aligned(IIO_= DMA_MINALIGN); + unsigned char tx_data[ALIGN(3, sizeof(s64)) + sizeof(s64)] __aligned(IIO_= DMA_MINALIGN); +}; + +static void ad4691_disable_regulators(void *data) +{ + struct ad4691_state *st =3D data; + + regulator_bulk_disable(AD4691_NUM_REGULATORS, st->regulators); +} + +static void ad4691_disable_regulator(void *data) +{ + struct regulator *reg =3D data; + + regulator_disable(reg); +} + +static void ad4691_disable_pwm(void *data) +{ + struct pwm_device *pwm =3D data; + struct pwm_state state; + + pwm_get_state(pwm, &state); + state.enabled =3D false; + pwm_apply_might_sleep(pwm, &state); +} + +static int ad4691_regulators_get(struct ad4691_state *st) +{ + struct device *dev =3D &st->spi->dev; + struct regulator *ref; + int ret; + + st->regulators[0].supply =3D "vio"; + + ret =3D devm_regulator_bulk_get(dev, AD4691_NUM_REGULATORS, + st->regulators); + if (ret) + return dev_err_probe(dev, ret, "Failed to get VIO regulator\n"); + + ret =3D regulator_bulk_enable(AD4691_NUM_REGULATORS, st->regulators); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable regulators\n"); + + ret =3D devm_add_action_or_reset(dev, ad4691_disable_regulators, st); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register regulator disable action\n"); + + ref =3D devm_regulator_get_optional(dev, "vref"); + if (IS_ERR(ref)) { + if (PTR_ERR(ref) !=3D -ENODEV) + return dev_err_probe(dev, PTR_ERR(ref), + "Failed to get vref regulator"); + + /* Internal REFIN must be used if optional REF isn't used. */ + ref =3D devm_regulator_get(dev, "vrefin"); + if (IS_ERR(ref)) + return dev_err_probe(dev, PTR_ERR(ref), + "Failed to get vrefin regulator"); + } + + ret =3D regulator_enable(ref); + if (ret) { + dev_err_probe(dev, ret, "Failed to enable specified ref supply\n"); + return ret; + } + + ret =3D devm_add_action_or_reset(dev, ad4691_disable_regulator, ref); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register ref disable action\n"); + + st->vref =3D regulator_get_voltage(ref); + if (st->vref < AD4691_VREF_MIN || st->vref > AD4691_VREF_MAX) + return dev_err_probe(dev, -EINVAL, "vref(%d) must be under [%u %u]\n", + st->vref, AD4691_VREF_MIN, AD4691_VREF_MAX); + + return 0; +} + +static int ad4691_reg_read(void *context, unsigned int reg, unsigned int *= val) +{ + struct ad4691_state *st =3D context; + unsigned char buf[6]; + int ret; + + buf[0] =3D (reg >> 8) | 0x80; + buf[1] =3D reg & 0xFF; + + switch (reg) { + case 0 ... AD4691_OSC_FREQ_REG: + case AD4691_SPARE_CONTROL ... AD4691_ACC_SAT_OVR_REG(15): + ret =3D spi_write_then_read(st->spi, &buf[0], 2, &buf[2], 1); + if (!ret) + *val =3D buf[2]; + break; + case AD4691_STD_SEQ_CONFIG: + case AD4691_AVG_IN(0) ... AD4691_AVG_IN(15): + ret =3D spi_write_then_read(st->spi, &buf[0], 2, &buf[2], 2); + if (!ret) + *val =3D get_unaligned_be16(&buf[2]); + break; + case AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15): + ret =3D spi_write_then_read(st->spi, &buf[0], 2, &buf[2], 3); + if (!ret) + *val =3D get_unaligned_be24(&buf[2]); + break; + case AD4691_ACC_IN(0) ... AD4691_ACC_IN(15): + ret =3D spi_write_then_read(st->spi, &buf[0], 2, &buf[2], 3); + if (!ret) + *val =3D get_unaligned_be24(&buf[2]); + break; + case AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15): + ret =3D spi_write_then_read(st->spi, &buf[0], 2, &buf[2], 4); + if (!ret) + *val =3D get_unaligned_be32(&buf[2]); + break; + default: + return -EINVAL; + } + + return ret; +} + +static int ad4691_reg_write(void *context, unsigned int reg, unsigned int = val) +{ + struct ad4691_state *st =3D context; + unsigned char buf[4]; + + buf[0] =3D (reg >> 8); + buf[1] =3D reg & 0xFF; + + switch (reg) { + case 0 ... AD4691_OSC_FREQ_REG: + case AD4691_SPARE_CONTROL ... AD4691_GPIO_MODE2_REG: + if (val > 0xFF) + return -EINVAL; + buf[2] =3D val; + + return spi_write(st->spi, buf, 3); + case AD4691_STD_SEQ_CONFIG: + if (val > 0xFFFF) + return -EINVAL; + put_unaligned_be16(val, &buf[2]); + + return spi_write(st->spi, buf, 4); + default: + return -EINVAL; + } +} + +static bool ad4691_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case AD4691_STATUS_REG: + case AD4691_CLAMP_STATUS1_REG: + case AD4691_CLAMP_STATUS2_REG: + case AD4691_GPIO_READ: + case AD4691_ACC_STATUS_FULL1_REG ... AD4691_ACC_STATUS_SAT2_REG: + case AD4691_ACC_SAT_OVR_REG(0) ... AD4691_ACC_SAT_OVR_REG(15): + case AD4691_AVG_IN(0) ... AD4691_AVG_IN(15): + case AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15): + case AD4691_ACC_IN(0) ... AD4691_ACC_IN(15): + case AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15): + return true; + default: + return false; + } +} + +static bool ad4691_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0 ... AD4691_OSC_FREQ_REG: + case AD4691_SPARE_CONTROL ... AD4691_ACC_SAT_OVR_REG(15): + case AD4691_STD_SEQ_CONFIG: + case AD4691_AVG_IN(0) ... AD4691_AVG_IN(15): + case AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15): + case AD4691_ACC_IN(0) ... AD4691_ACC_IN(15): + case AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15): + return true; + default: + return false; + } +} + +static bool ad4691_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0 ... AD4691_OSC_FREQ_REG: + case AD4691_STD_SEQ_CONFIG: + case AD4691_SPARE_CONTROL ... AD4691_GPIO_MODE2_REG: + return true; + default: + return false; + } +} + +static const struct regmap_config ad4691_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 32, + .reg_read =3D ad4691_reg_read, + .reg_write =3D ad4691_reg_write, + .volatile_reg =3D ad4691_volatile_reg, + .readable_reg =3D ad4691_readable_reg, + .writeable_reg =3D ad4691_writeable_reg, + .max_register =3D AD4691_ACC_STS_DATA(15), + .cache_type =3D REGCACHE_RBTREE, +}; + +static int ad4691_transfer(struct ad4691_state *st, int command, + unsigned int *val) +{ + struct spi_transfer xfer =3D { + .tx_buf =3D st->tx_data, + .rx_buf =3D st->rx_data, + .len =3D 3, + }; + int ret; + + memcpy(st->tx_data, &command, 3); + + ret =3D spi_sync_transfer(st->spi, &xfer, 1); + if (ret) + return ret; + + *val =3D get_unaligned_be24(st->rx_data); + + return 0; +} + +static int ad4691_get_sampling_freq(struct ad4691_state *st) +{ + unsigned int val; + int ret; + + switch (st->adc_mode) { + case AD4691_MANUAL_MODE: + return DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, + ktime_to_ns(st->sampling_period)); + case AD4691_CNV_CLOCK_MODE: + return DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, + pwm_get_period(st->conv_trigger)); + case AD4691_CNV_BURST_MODE: + case AD4691_AUTONOMOUS_MODE: + case AD4691_SPI_BURST_MODE: + ret =3D regmap_read(st->regmap, AD4691_OSC_FREQ_REG, &val); + if (ret) + return ret; + + return ad4691_int_osc_val[val]; + default: + return -EINVAL; + } +} + +static int __ad4691_set_sampling_freq(struct ad4691_state *st, int freq) +{ + unsigned long long target, ref_clk_period_ns; + struct pwm_state cnv_state; + + pwm_init_state(st->conv_trigger, &cnv_state); + + freq =3D clamp(freq, 1, st->chip->max_rate); + target =3D DIV_ROUND_CLOSEST_ULL(st->ref_clk_rate, freq); + ref_clk_period_ns =3D DIV_ROUND_CLOSEST_ULL(NANO, st->ref_clk_rate); + st->cnv_period =3D ref_clk_period_ns * target; + cnv_state.period =3D ref_clk_period_ns * target; + cnv_state.duty_cycle =3D AD4691_CNV_DUTY_CYCLE_NS; + cnv_state.enabled =3D false; + + return pwm_apply_might_sleep(st->conv_trigger, &cnv_state); +} + +/* + * ad4691_cnv_burst_period_ns - Compute the CNV_BURST_MODE PWM period. + * @st: Driver state. + * @n_active: Number of active channels. + * + * The period must cover the full conversion time tOSC*(n_active+1) plus + * the SPI transfer time for reading the accumulator results and issuing + * STATE_RESET, with a 50% margin on the SPI portion to absorb jitter. + * + * Return: Period in nanoseconds. + */ +static u64 ad4691_cnv_burst_period_ns(struct ad4691_state *st, + int n_active) +{ + unsigned int osc_idx =3D AD4691_OSC_1MHZ; + u64 osc_freq, conv_time_ns, spi_bits, spi_time_ns; + + regmap_read(st->regmap, AD4691_OSC_FREQ_REG, &osc_idx); + if (osc_idx >=3D ARRAY_SIZE(ad4691_int_osc_val)) + osc_idx =3D AD4691_OSC_1MHZ; + + osc_freq =3D ad4691_int_osc_val[osc_idx]; + conv_time_ns =3D div64_u64((u64)(n_active + 1) * NSEC_PER_SEC, osc_freq); + + spi_bits =3D (u64)n_active * 32 + 24; + spi_time_ns =3D div64_u64(spi_bits * NSEC_PER_SEC, st->spi->max_speed_hz); + + /* 50% margin on SPI time absorbs OS scheduling jitter. */ + return conv_time_ns + spi_time_ns * 3 / 2; +} + +static int ad4691_pwm_get(struct spi_device *spi, struct ad4691_state *st) +{ + struct clk *ref_clk; + int ret; + + ref_clk =3D devm_clk_get_enabled(&spi->dev, "ref_clk"); + if (IS_ERR(ref_clk)) + return dev_err_probe(&spi->dev, PTR_ERR(ref_clk), + "Failed to get ref_clk\n"); + + st->ref_clk_rate =3D clk_get_rate(ref_clk); + + st->conv_trigger =3D devm_pwm_get(&spi->dev, "cnv"); + if (IS_ERR(st->conv_trigger)) { + return dev_err_probe(&spi->dev, PTR_ERR(st->conv_trigger), + "Failed to get cnv pwm\n"); + } + + ret =3D devm_add_action_or_reset(&spi->dev, ad4691_disable_pwm, + st->conv_trigger); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to register PWM disable action\n"); + + switch (st->adc_mode) { + case AD4691_CNV_CLOCK_MODE: + return __ad4691_set_sampling_freq(st, st->chip->max_rate); + case AD4691_CNV_BURST_MODE: { + /* + * In CNV Burst Mode, the internal oscillator drives per-channel + * conversions. The PWM triggers each burst cycle; its period + * must cover the full conversion time tOSC*(n+1) plus SPI + * transfer time. Use worst-case channel count here; the period + * is refined at buffer enable time when the active count is known. + */ + u64 period_ns =3D ad4691_cnv_burst_period_ns(st, st->chip->num_channels); + int pwm_freq =3D (int)max(1ULL, div64_u64(NSEC_PER_SEC, period_ns)); + + return __ad4691_set_sampling_freq(st, pwm_freq); + } + default: + return -EOPNOTSUPP; + } +} + +static int ad4691_set_sampling_freq(struct iio_dev *indio_dev, unsigned in= t freq) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + int ret, i; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + mutex_lock(&st->lock); + switch (st->adc_mode) { + case AD4691_MANUAL_MODE: + if (!freq || freq > st->chip->max_rate) { + ret =3D -EINVAL; + goto exit; + } + + st->sampling_period =3D ns_to_ktime(DIV_ROUND_CLOSEST_ULL + (NSEC_PER_SEC, freq)); + ret =3D 0; + goto exit; + case AD4691_CNV_CLOCK_MODE: + if (!st->conv_trigger) { + ret =3D -ENODEV; + goto exit; + } + + if (!freq || freq > st->chip->max_rate) { + ret =3D -EINVAL; + goto exit; + } + + ret =3D __ad4691_set_sampling_freq(st, freq); + break; + case AD4691_CNV_BURST_MODE: { + u64 period_ns; + int pwm_freq; + + i =3D find_closest_descending(freq, ad4691_int_osc_val, 16); + ret =3D regmap_write(st->regmap, AD4691_OSC_FREQ_REG, i); + if (ret) + goto exit; + + /* + * Compute the worst-case PWM period using the maximum channel + * count. The exact period is refined at buffer enable time when + * the active channel count is known. + */ + period_ns =3D ad4691_cnv_burst_period_ns(st, st->chip->num_channels); + pwm_freq =3D (int)max(1ULL, div64_u64(NSEC_PER_SEC, period_ns)); + ret =3D __ad4691_set_sampling_freq(st, pwm_freq); + + break; + } + case AD4691_AUTONOMOUS_MODE: + case AD4691_SPI_BURST_MODE: + i =3D find_closest_descending(freq, ad4691_int_osc_val, 16); + ret =3D regmap_write(st->regmap, AD4691_OSC_FREQ_REG, i); + break; + default: + ret =3D -EINVAL; + break; + } + +exit: + mutex_unlock(&st->lock); + iio_device_release_direct(indio_dev); + return ret; +} + +static int ad4691_sampling_enable(struct ad4691_state *st, bool enable) +{ + struct pwm_state conv_state =3D { }; + + switch (st->adc_mode) { + case AD4691_CNV_CLOCK_MODE: + case AD4691_CNV_BURST_MODE: + conv_state.period =3D st->cnv_period; + conv_state.duty_cycle =3D AD4691_CNV_DUTY_CYCLE_NS; + conv_state.polarity =3D PWM_POLARITY_NORMAL; + conv_state.enabled =3D enable; + + return pwm_apply_might_sleep(st->conv_trigger, &conv_state); + case AD4691_AUTONOMOUS_MODE: + return regmap_write(st->regmap, AD4691_OSC_EN_REG, enable); + case AD4691_SPI_BURST_MODE: + if (enable) + return regmap_write(st->regmap, AD4691_OSC_EN_REG, enable); + + /* + * SPI Burst Mode is self-terminating: the oscillator stops + * automatically after the configured number of conversions. + * No explicit disable write is needed. + */ + return 0; + default: + return -EINVAL; + } +} + +/* + * Return the time in microseconds for a single-channel conversion driven = by + * the internal oscillator. A single read requires (n_active + 1) =3D 2 os= cillator + * periods (n_active =3D 1). + */ +static unsigned long ad4691_osc_single_conv_us(struct ad4691_state *st) +{ + unsigned int osc_idx =3D AD4691_OSC_1MHZ; + + regmap_read(st->regmap, AD4691_OSC_FREQ_REG, &osc_idx); + if (osc_idx >=3D ARRAY_SIZE(ad4691_int_osc_val)) + osc_idx =3D AD4691_OSC_1MHZ; + + return DIV_ROUND_UP(2UL * USEC_PER_SEC, ad4691_int_osc_val[osc_idx]); +} + +static int ad4691_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long info) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + unsigned int reg_val; + int ret; + + switch (info) { + case IIO_CHAN_INFO_RAW: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + switch (st->adc_mode) { + case AD4691_CNV_CLOCK_MODE: + case AD4691_CNV_BURST_MODE: + case AD4691_AUTONOMOUS_MODE: + case AD4691_SPI_BURST_MODE: + ret =3D regmap_write(st->regmap, AD4691_STATE_RESET_REG, + AD4691_STATE_RESET_ALL); + if (ret) + goto done; + + ret =3D regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, BIT(chan->chann= el)); + if (ret) + goto done; + + if (chan->channel < 8) { + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK1_REG, + ~BIT(chan->channel) & 0xFF); + if (ret) + goto done; + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK2_REG, + 0xFF); + } else { + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK1_REG, + 0xFF); + if (ret) + goto done; + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK2_REG, + ~BIT(chan->channel - 8) & 0xFF); + } + + if (ret) + goto done; + + ret =3D ad4691_sampling_enable(st, true); + if (ret) + goto done; + + /* + * Wait for conversion to complete using a timed delay. + * CNV_CLOCK_MODE conversion time is bounded by + * AD4691_MAX_CONV_PERIOD_US. All other modes are driven by + * the internal oscillator; two oscillator periods cover a + * single-channel read (n_active + 1 =3D 2). + */ + if (st->adc_mode =3D=3D AD4691_CNV_CLOCK_MODE) { + usleep_range(AD4691_MAX_CONV_PERIOD_US, + AD4691_MAX_CONV_PERIOD_US + 100); + } else { + unsigned long conv_us =3D ad4691_osc_single_conv_us(st); + + usleep_range(conv_us, conv_us + conv_us / 4 + 1); + } + + ret =3D ad4691_sampling_enable(st, false); + if (ret) + goto done; + + ret =3D regmap_read(st->regmap, + AD4691_AVG_IN(chan->channel), + ®_val); + + *val =3D reg_val; + regmap_write(st->regmap, AD4691_STATE_RESET_REG, + AD4691_STATE_RESET_ALL); + + break; + case AD4691_MANUAL_MODE: + ret =3D ad4691_transfer(st, AD4691_ADC_CHAN(chan->channel), val); + if (ret) + goto done; + + ret =3D ad4691_transfer(st, AD4691_NOOP, val); + if (ret) + goto done; + + /* Extract ADC data from the 24-bit SPI frame */ + *val =3D *val >> 8; + break; + default: + ret =3D -EINVAL; + goto done; + } + +done: + iio_device_release_direct(indio_dev); + + if (ret) + return ret; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SAMP_FREQ: + *val =3D ad4691_get_sampling_freq(st); + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + *val =3D st->vref / 1000; + *val2 =3D chan->scan_type.realbits; + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static int ad4691_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long info) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: + switch (st->adc_mode) { + case AD4691_CNV_CLOCK_MODE: + case AD4691_MANUAL_MODE: + return -EOPNOTSUPP; + case AD4691_CNV_BURST_MODE: + case AD4691_AUTONOMOUS_MODE: + case AD4691_SPI_BURST_MODE: + *vals =3D ad4691_int_osc_val; + *length =3D ARRAY_SIZE(ad4691_int_osc_val); + *type =3D IIO_VAL_INT; + + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static int ad4691_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + return ad4691_set_sampling_freq(indio_dev, val); + default: + return -EINVAL; + } +} + +static int ad4691_reg_access(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + int ret; + + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) + return -EOPNOTSUPP; + + mutex_lock(&st->lock); + if (readval) { + ret =3D regmap_read(st->regmap, reg, readval); + goto mutex_unlock; + } + + ret =3D regmap_write(st->regmap, reg, writeval); + +mutex_unlock: + mutex_unlock(&st->lock); + return ret; +} + +static const struct iio_info ad4691_info =3D { + .read_raw =3D &ad4691_read_raw, + .read_avail =3D &ad4691_read_avail, + .write_raw =3D &ad4691_write_raw, + .debugfs_reg_access =3D &ad4691_reg_access, +}; + +static const struct spi_device_id ad4691_id[] =3D { + { "ad4692", (kernel_ulong_t)&ad4691_chips[AD4691_ID_AD4692] }, + { "ad4691", (kernel_ulong_t)&ad4691_chips[AD4691_ID_AD4691] }, + { "ad4694", (kernel_ulong_t)&ad4691_chips[AD4691_ID_AD4694] }, + { "ad4693", (kernel_ulong_t)&ad4691_chips[AD4691_ID_AD4693] }, + {} +}; +MODULE_DEVICE_TABLE(spi, ad4691_id); + +static int ad4691_gpio_setup(struct ad4691_state *st) +{ + struct device *dev =3D &st->spi->dev; + struct gpio_desc *reset; + + reset =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(reset)) + return dev_err_probe(dev, PTR_ERR(reset), + "Failed to get reset GPIO\n"); + + /* Reset delay required. See datasheet Table 5. */ + fsleep(300); + gpiod_set_value(reset, 0); + + return 0; +} + +static int ad4691_config(struct ad4691_state *st) +{ + struct device *dev =3D &st->spi->dev; + unsigned int reg_val; + u32 mode; + int ret; + + ret =3D regmap_read(st->regmap, AD4691_PRODUCT_ID_LSB_REG, ®_val); + if (ret) + return dev_err_probe(dev, ret, "Failed to read product ID\n"); + + if (reg_val !=3D st->chip->product_id) + return dev_err_probe(dev, -ENODEV, + "Product ID mismatch: expected 0x%02x, got 0x%02x\n", + st->chip->product_id, reg_val); + + ret =3D device_property_read_u32(dev, "adi,spi-mode", &mode); + if (ret) + return dev_err_probe(dev, -EINVAL, "Could not find SPI mode\n"); + + if (mode > AD4691_MAX_ADC_MODE) + return dev_err_probe(dev, -EINVAL, "Invalid SPI mode(%u)\n", mode); + + st->adc_mode =3D mode; + + /* + * CNV_CLOCK_MODE and CNV_BURST_MODE require a PWM for conversion timing. + * MANUAL_MODE doesn't need PWM - CS is tied to CNV, so each SPI + * transfer automatically triggers a conversion. + */ + if (st->adc_mode =3D=3D AD4691_CNV_CLOCK_MODE || + st->adc_mode =3D=3D AD4691_CNV_BURST_MODE) { + if (device_property_present(dev, "pwms")) { + ret =3D ad4691_pwm_get(st->spi, st); + if (ret) + return ret; + } else { + return dev_err_probe(dev, -ENODEV, + "CNV modes require 'pwms' property\n"); + } + } + + /* Perform a state reset on the channels at start-up. */ + ret =3D regmap_write(st->regmap, AD4691_STATE_RESET_REG, + AD4691_STATE_RESET_ALL); + if (ret) + return dev_err_probe(dev, ret, "Failed to write state reset\n"); + + /* Clear STATUS register by reading from the STATUS register. */ + ret =3D regmap_read(st->regmap, AD4691_STATUS_REG, ®_val); + if (ret) + return dev_err_probe(dev, ret, "Failed to read status register\n"); + + switch (st->vref) { + case AD4691_VREF_MIN ... 2750000: + ret =3D regmap_write(st->regmap, AD4691_REF_CTRL, + FIELD_PREP(AD4691_REF_CTRL_MASK, + AD4691_VREF_2P5)); + break; + case 2750001 ... 3250000: + ret =3D regmap_write(st->regmap, AD4691_REF_CTRL, + FIELD_PREP(AD4691_REF_CTRL_MASK, + AD4691_VREF_3P0)); + break; + case 3250001 ... 3750000: + ret =3D regmap_write(st->regmap, AD4691_REF_CTRL, + FIELD_PREP(AD4691_REF_CTRL_MASK, + AD4691_VREF_3P3)); + break; + case 3750001 ... 4500000: + ret =3D regmap_write(st->regmap, AD4691_REF_CTRL, + FIELD_PREP(AD4691_REF_CTRL_MASK, + AD4691_VREF_4P096)); + break; + case 4500001 ... AD4691_VREF_MAX: + ret =3D regmap_write(st->regmap, AD4691_REF_CTRL, + FIELD_PREP(AD4691_REF_CTRL_MASK, + AD4691_VREF_5P0)); + break; + default: + return dev_err_probe(dev, -EINVAL, + "Unsupported vref voltage: %d uV\n", + st->vref); + } + if (ret) + return dev_err_probe(dev, ret, "Failed to write REF_CTRL\n"); + + switch (st->adc_mode) { + case AD4691_CNV_CLOCK_MODE: + case AD4691_CNV_BURST_MODE: + case AD4691_AUTONOMOUS_MODE: + case AD4691_SPI_BURST_MODE: + /* + * The adi,spi-mode DT property values 0-3 map directly to the + * ADC_SETUP register encoding for these four modes. + */ + ret =3D regmap_write(st->regmap, AD4691_ADC_SETUP, mode); + if (ret) + return dev_err_probe(dev, ret, + "Failed to write ADC_SETUP\n"); + + if (st->adc_mode =3D=3D AD4691_AUTONOMOUS_MODE) + /* Configure GP0 as ADC_BUSY for trigger */ + return regmap_write(st->regmap, AD4691_GPIO_MODE1_REG, + AD4691_ADC_BUSY); + else + /* Configure GP0 as DATA_READY for trigger */ + return regmap_write(st->regmap, AD4691_GPIO_MODE1_REG, + AD4691_DATA_READY); + case AD4691_MANUAL_MODE: + /* GP0 as ADC_BUSY; conversion completion is polled via CS in MANUAL_MOD= E. */ + ret =3D regmap_write(st->regmap, AD4691_GPIO_MODE1_REG, + AD4691_ADC_BUSY); + if (ret) + return dev_err_probe(dev, ret, + "Failed to write GPIO_MODE1\n"); + + return regmap_write(st->regmap, AD4691_DEVICE_SETUP, + AD4691_DEVICE_MANUAL); + default: + return -EINVAL; + } +} + +static void ad4691_setup_channels(struct iio_dev *indio_dev, + struct ad4691_state *st) +{ + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + if (st->chip->num_channels =3D=3D 8) + indio_dev->channels =3D ad4693_manual_channels; + else + indio_dev->channels =3D ad4691_manual_channels; + } else { + indio_dev->channels =3D st->chip->channels; + } + + indio_dev->num_channels =3D st->chip->num_channels; +} + +static int ad4691_probe(struct spi_device *spi) +{ + struct device *dev =3D &spi->dev; + struct iio_dev *indio_dev; + struct ad4691_state *st; + int ret; + + indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + mutex_init(&st->lock); + + st->spi =3D spi; + spi_set_drvdata(spi, indio_dev); + + st->regmap =3D devm_regmap_init(dev, NULL, st, &ad4691_regmap_config); + if (IS_ERR(st->regmap)) + return dev_err_probe(dev, PTR_ERR(st->regmap), + "Failed to initialize regmap\n"); + + st->chip =3D spi_get_device_match_data(spi); + if (!st->chip) { + st->chip =3D (void *)spi_get_device_id(spi)->driver_data; + if (!st->chip) + return dev_err_probe(dev, -ENODEV, + "Could not find chip info data\n"); + } + + ret =3D ad4691_regulators_get(st); + if (ret) + return ret; + + ret =3D ad4691_gpio_setup(st); + if (ret) + return ret; + + ret =3D ad4691_config(st); + if (ret) + return ret; + + indio_dev->name =3D st->chip->name; + indio_dev->info =3D &ad4691_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + + ad4691_setup_channels(indio_dev, st); + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id ad4691_of_match[] =3D { + { .compatible =3D "adi,ad4692", .data =3D &ad4691_chips[AD4691_ID_AD4692]= }, + { .compatible =3D "adi,ad4691", .data =3D &ad4691_chips[AD4691_ID_AD4691]= }, + { .compatible =3D "adi,ad4694", .data =3D &ad4691_chips[AD4691_ID_AD4694]= }, + { .compatible =3D "adi,ad4693", .data =3D &ad4691_chips[AD4691_ID_AD4693]= }, + {}, +}; +MODULE_DEVICE_TABLE(of, ad4691_of_match); + +static struct spi_driver ad4691_driver =3D { + .driver =3D { + .name =3D "ad4691", + .of_match_table =3D ad4691_of_match, + }, + .probe =3D ad4691_probe, + .id_table =3D ad4691_id, +}; +module_spi_driver(ad4691_driver); + +MODULE_AUTHOR("Radu Sabau "); +MODULE_DESCRIPTION("Analog Devices AD4691 Family ADC Driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Thu Apr 9 21:52:42 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAFBC39C65B; Thu, 5 Mar 2026 12:23:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772713415; cv=none; b=XED6/T2LM+3T6N8QQNK55t9fgGTA5xpT70dueEe4EuAGJ/wvs36gdwhwtJmiOdgdkWvkJkQVVgnuo2tHNhaYsISvY6xO40+gXs0IRhX+vwOvmp3ICIoliMPUbrf3iBkTQfvIJb5XOlUD9isnLiUwgAwSJy7th0ZLjGy9PH5j3i4= ARC-Message-Signature: i=1; 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b=QvdAk9USDxxhhj0r+hCo5JcjC+PARN2duf0LnNe46w7wsdMTbs9Zp1YbU1AZx5+Yu xITLNTNTvYM01Zb/xu6zb8PLY8PjtberuENwU+sYSVBaSoIMSKWKuy1PmDMu5+MMA0 iLmBbZuJ1k3ASpQHYM9SyLoyNDIrxUspyzVkjAAmvfmWaw3GB6/NGRg7dWZL/QgnNq 2VoqVntKvrE/QRHplY70UIkHrFpHr/eyd8MQjD1xKxIgxjTvL0PDXahUfj24IiOUfG VCP1oNI90yvOWqUbHLGR5G/bNrKbyQaJ3neUw8LddDkEomYRZfHttVl4iW0DvOfbBA okesqtZss0mgA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 620D9F30959; Thu, 5 Mar 2026 12:23:35 +0000 (UTC) From: Radu Sabau via B4 Relay Date: Thu, 05 Mar 2026 14:23:29 +0200 Subject: [PATCH 3/4] iio: adc: ad4691: add triggered buffer support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-ad4692-multichannel-sar-adc-driver-v1-3-336229a8dcc7@analog.com> References: <20260305-ad4692-multichannel-sar-adc-driver-v1-0-336229a8dcc7@analog.com> In-Reply-To: <20260305-ad4692-multichannel-sar-adc-driver-v1-0-336229a8dcc7@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772713413; l=12862; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=ljLdjl7LKh8bWVM9PqQW0wndeElVvojPks9hWMLcmBg=; b=oFwWvou/67Hi/3HgCN2YTbMr8UyIeJdiG39EcCty4hSiHVEV28SgiavIXMzglfipeNw1DXbEZ CvBuKgoMDSAAiDzjcEtmq2kV28XJ4cqkUh56QyhT9CKZXz3dVpAqwFd X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add buffered capture support using the IIO triggered buffer framework. For CNV Clock, CNV Burst, Autonomous and SPI Burst modes the GP0 pin is configured as DATA_READY output and an interrupt is registered on its falling edge. Each interrupt fires the trigger, which reads accumulated results from the internal accumulator registers via regmap. For Manual Mode (pipelined SPI protocol) there is no DATA_READY signal, so an hrtimer-based IIO trigger is used instead. The timer period is derived from the requested sampling frequency and validated against the minimum SPI transfer time for the active channel count. The trigger handler walks the active scan mask issuing one 3-byte SPI transfer per channel (selecting the next channel while reading the previous result) and pushes samples to the IIO buffer. Signed-off-by: Radu Sabau --- drivers/iio/adc/Kconfig | 2 + drivers/iio/adc/ad4691.c | 316 +++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 318 insertions(+) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 3685a03aa8dc..d498f16c0816 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -142,6 +142,8 @@ config AD4170_4 config AD4691 tristate "Analog Devices AD4691 Family ADC Driver" depends on SPI + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER select REGMAP help Say yes here to build support for Analog Devices AD4691 Family MuxSAR diff --git a/drivers/iio/adc/ad4691.c b/drivers/iio/adc/ad4691.c index dee8bc312d44..ab48f336e46c 100644 --- a/drivers/iio/adc/ad4691.c +++ b/drivers/iio/adc/ad4691.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -24,8 +25,13 @@ #include #include =20 +#include #include =20 +#include +#include +#include + #include =20 #define AD4691_NUM_REGULATORS 1 @@ -42,6 +48,7 @@ * =3D spi_hz / (36 * (num_channels + 1)) */ #define AD4691_MANUAL_MODE_STD_FREQ(x, y) ((y) / (36 * ((x) + 1))) +#define AD4691_BITS_PER_XFER 24 #define AD4691_CNV_DUTY_CYCLE_NS 380 #define AD4691_MAX_CONV_PERIOD_US 800 =20 @@ -287,6 +294,8 @@ struct ad4691_state { =20 struct regulator_bulk_data regulators[AD4691_NUM_REGULATORS]; =20 + struct iio_trigger *trig; + enum ad4691_adc_mode adc_mode; =20 int vref; @@ -297,6 +306,8 @@ struct ad4691_state { */ struct mutex lock; =20 + /* hrtimer for MANUAL_MODE triggered buffer (non-offload) */ + struct hrtimer sampling_timer; ktime_t sampling_period; =20 /* DMA (thus cache coherency maintenance) may require the @@ -306,6 +317,11 @@ struct ad4691_state { */ unsigned char rx_data[ALIGN(3, sizeof(s64)) + sizeof(s64)] __aligned(IIO_= DMA_MINALIGN); unsigned char tx_data[ALIGN(3, sizeof(s64)) + sizeof(s64)] __aligned(IIO_= DMA_MINALIGN); + /* Scan buffer for triggered buffer push (one sample + timestamp) */ + struct { + u32 val; + s64 ts __aligned(8); + } scan __aligned(IIO_DMA_MINALIGN); }; =20 static void ad4691_disable_regulators(void *data) @@ -949,6 +965,233 @@ static int ad4691_reg_access(struct iio_dev *indio_de= v, unsigned int reg, return ret; } =20 +static int ad4691_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + int n_active =3D hweight_long(*indio_dev->active_scan_mask); + int ret; + + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + u64 min_period_ns; + + /* N+1 transfers needed for N channels, with 50% overhead */ + min_period_ns =3D div64_u64((u64)(n_active + 1) * AD4691_BITS_PER_XFER * + NSEC_PER_SEC * 3, + st->spi->max_speed_hz * 2); + + if (ktime_to_ns(st->sampling_period) < min_period_ns) { + dev_err(&st->spi->dev, + "Sampling period %lld ns too short for %d channels. Min: %llu ns\n", + ktime_to_ns(st->sampling_period), n_active, + min_period_ns); + return -EINVAL; + } + + hrtimer_start(&st->sampling_timer, st->sampling_period, + HRTIMER_MODE_REL); + return 0; + } + + ret =3D regmap_write(st->regmap, AD4691_STATE_RESET_REG, + AD4691_STATE_RESET_ALL); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK1_REG, + ~(*indio_dev->active_scan_mask) & 0xFF); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK2_REG, + ~(*indio_dev->active_scan_mask >> 8) & 0xFF); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, + *indio_dev->active_scan_mask); + if (ret) + return ret; + + if (st->adc_mode =3D=3D AD4691_AUTONOMOUS_MODE) + ret =3D regmap_write(st->regmap, AD4691_GPIO_MODE1_REG, AD4691_ADC_BUSY); + else + ret =3D regmap_write(st->regmap, AD4691_GPIO_MODE1_REG, AD4691_DATA_READ= Y); + if (ret) + return ret; + + switch (st->adc_mode) { + case AD4691_CNV_BURST_MODE: + /* + * Recompute the PWM period now that the active channel count is + * known. The period must cover one full burst cycle: oscillator + * conversion time (tOSC * (n+1)) plus all SPI transfer time. + */ + st->cnv_period =3D ad4691_cnv_burst_period_ns(st, n_active, false); + fallthrough; + case AD4691_AUTONOMOUS_MODE: + case AD4691_SPI_BURST_MODE: + case AD4691_CNV_CLOCK_MODE: + return ad4691_sampling_enable(st, true); + default: + return -EOPNOTSUPP; + } +} + +static int ad4691_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + int ret; + + switch (st->adc_mode) { + case AD4691_AUTONOMOUS_MODE: + case AD4691_SPI_BURST_MODE: + case AD4691_CNV_BURST_MODE: + case AD4691_CNV_CLOCK_MODE: + ret =3D ad4691_sampling_enable(st, false); + if (ret) + return ret; + break; + case AD4691_MANUAL_MODE: + hrtimer_cancel_wait_running(&st->sampling_timer); + return 0; + default: + return -EOPNOTSUPP; + } + + ret =3D regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, + AD4691_SEQ_ALL_CHANNELS_OFF); + if (ret) + return ret; + + return regmap_write(st->regmap, AD4691_STATE_RESET_REG, + AD4691_STATE_RESET_ALL); +} + +static const struct iio_buffer_setup_ops ad4691_buffer_setup_ops =3D { + .postenable =3D &ad4691_buffer_postenable, + .postdisable =3D &ad4691_buffer_postdisable, +}; + +static irqreturn_t ad4691_irq(int irq, void *private) +{ + struct iio_dev *indio_dev =3D private; + struct ad4691_state *st =3D iio_priv(indio_dev); + + /* + * DATA_READY has asserted: stop conversions before reading so the + * accumulator does not continue sampling while the trigger handler + * processes the data. Then fire the IIO trigger to push the sample + * to the buffer. + * + * In direct (read_raw) mode the buffer is not enabled; read_raw uses + * a timed delay and stops conversions itself, so skip the trigger poll. + */ + ad4691_sampling_enable(st, false); + + if (iio_buffer_enabled(indio_dev)) + iio_trigger_poll(st->trig); + + return IRQ_HANDLED; +} + +static enum hrtimer_restart ad4691_sampling_timer_handler(struct hrtimer *= timer) +{ + struct ad4691_state *st =3D container_of(timer, struct ad4691_state, + sampling_timer); + + iio_trigger_poll(st->trig); + hrtimer_forward_now(timer, st->sampling_period); + + return HRTIMER_RESTART; +} + +static const struct iio_trigger_ops ad4691_trigger_ops =3D { + .validate_device =3D iio_trigger_validate_own_device, +}; + +static irqreturn_t ad4691_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct ad4691_state *st =3D iio_priv(indio_dev); + unsigned int val; + int ret, i; + + mutex_lock(&st->lock); + + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + unsigned int prev_val; + int prev_chan =3D -1; + + /* + * MANUAL_MODE with CNV tied to CS: each transfer triggers a + * conversion AND returns the previous conversion's result. + * First transfer returns garbage, so we do N+1 transfers for + * N channels. + */ + iio_for_each_active_channel(indio_dev, i) { + ret =3D ad4691_transfer(st, AD4691_ADC_CHAN(i), &val); + if (ret) + goto done; + + /* Push previous channel's data (skip first - garbage) */ + if (prev_chan >=3D 0) { + st->scan.val =3D prev_val; + iio_push_to_buffers_with_ts(indio_dev, + &st->scan, sizeof(st->scan), + iio_get_time_ns(indio_dev)); + } + prev_val =3D val; + prev_chan =3D i; + } + + /* Final NOOP transfer to get last channel's data */ + ret =3D ad4691_transfer(st, AD4691_NOOP, &val); + if (ret) + goto done; + + st->scan.val =3D val; + iio_push_to_buffers_with_ts(indio_dev, &st->scan, sizeof(st->scan), + iio_get_time_ns(indio_dev)); + goto done; + } + + for (i =3D 0; i < st->chip->num_channels; i++) { + if (BIT(i) & *indio_dev->active_scan_mask) { + ret =3D regmap_read(st->regmap, AD4691_AVG_IN(i), &val); + if (ret) + goto done; + + st->scan.val =3D val; + iio_push_to_buffers_with_ts(indio_dev, &st->scan, sizeof(st->scan), + iio_get_time_ns(indio_dev)); + } + } + + regmap_write(st->regmap, AD4691_STATE_RESET_REG, AD4691_STATE_RESET_ALL); + + /* START next conversion. */ + switch (st->adc_mode) { + case AD4691_CNV_CLOCK_MODE: + case AD4691_CNV_BURST_MODE: + case AD4691_AUTONOMOUS_MODE: + case AD4691_SPI_BURST_MODE: + ad4691_sampling_enable(st, true); + break; + case AD4691_MANUAL_MODE: + default: + break; + } + + iio_trigger_notify_done(indio_dev->trig); + mutex_unlock(&st->lock); + return IRQ_HANDLED; +done: + mutex_unlock(&st->lock); + iio_trigger_notify_done(indio_dev->trig); + return IRQ_HANDLED; +} + static const struct iio_info ad4691_info =3D { .read_raw =3D &ad4691_read_raw, .read_avail =3D &ad4691_read_avail, @@ -1121,6 +1364,75 @@ static void ad4691_setup_channels(struct iio_dev *in= dio_dev, indio_dev->num_channels =3D st->chip->num_channels; } =20 +static int ad4691_setup_triggered_buffer(struct iio_dev *indio_dev, + struct ad4691_state *st) +{ + struct device *dev =3D &st->spi->dev; + int irq, ret; + + st->trig =3D devm_iio_trigger_alloc(dev, "%s-dev%d", + indio_dev->name, + iio_device_id(indio_dev)); + if (!st->trig) + return dev_err_probe(dev, -ENOMEM, + "Failed to allocate IIO trigger\n"); + + st->trig->ops =3D &ad4691_trigger_ops; + iio_trigger_set_drvdata(st->trig, st); + + ret =3D devm_iio_trigger_register(dev, st->trig); + if (ret) + return dev_err_probe(dev, ret, "IIO trigger register failed\n"); + + indio_dev->trig =3D iio_trigger_get(st->trig); + + switch (st->adc_mode) { + case AD4691_CNV_CLOCK_MODE: + case AD4691_CNV_BURST_MODE: + case AD4691_AUTONOMOUS_MODE: + case AD4691_SPI_BURST_MODE: + /* + * DATA_READY asserts at end-of-conversion (or when the + * accumulator fills in AUTONOMOUS_MODE). The IRQ handler stops + * conversions and fires the IIO trigger so the trigger handler + * can read and push the sample to the buffer. + */ + irq =3D fwnode_irq_get_byname(dev_fwnode(dev), "DRDY"); + if (irq <=3D 0) + return dev_err_probe(dev, irq ? irq : -ENOENT, + "failed to get DRDY interrupt\n"); + + ret =3D devm_request_threaded_irq(dev, irq, NULL, + &ad4691_irq, + IRQF_ONESHOT | IRQF_TRIGGER_FALLING, + indio_dev->name, indio_dev); + if (ret) + return dev_err_probe(dev, ret, + "request irq %d failed\n", irq); + break; + case AD4691_MANUAL_MODE: + /* + * No DATA_READY signal in MANUAL_MODE; CNV is tied to CS so + * conversions start with each SPI transfer. Use an hrtimer to + * schedule periodic reads. + */ + hrtimer_setup(&st->sampling_timer, ad4691_sampling_timer_handler, + CLOCK_MONOTONIC, HRTIMER_MODE_REL); + st->sampling_period =3D ns_to_ktime(DIV_ROUND_CLOSEST_ULL( + NSEC_PER_SEC, + AD4691_MANUAL_MODE_STD_FREQ(st->chip->num_channels, + st->spi->max_speed_hz))); + break; + default: + return -EINVAL; + } + + return devm_iio_triggered_buffer_setup(dev, indio_dev, + &iio_pollfunc_store_time, + &ad4691_trigger_handler, + &ad4691_buffer_setup_ops); +} + static int ad4691_probe(struct spi_device *spi) { struct device *dev =3D &spi->dev; @@ -1169,6 +1481,10 @@ static int ad4691_probe(struct spi_device *spi) =20 ad4691_setup_channels(indio_dev, st); =20 + ret =3D ad4691_setup_triggered_buffer(indio_dev, st); + if (ret) + return ret; + return devm_iio_device_register(dev, indio_dev); } =20 --=20 2.43.0 From nobody Thu Apr 9 21:52:42 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9A5E39D6FD; Thu, 5 Mar 2026 12:23:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772713415; cv=none; b=pixJDcT5syPQ/9mGrGQNmpejREt1gu0VCI+PHCzED4XB3E2iSnh2k8gUP3vyQVxNnV/s+LOolln/DYbCzTmpm5rkurfIOT1CzFoJSdSGucJMcdrvJm6LBpXh1TJHvQR46CTx2Wbobsow/aRvf7K1HXRv6nhSR1roHHq4ivVa6gU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772713415; c=relaxed/simple; bh=XMyV1p3aB7Qf2mFuPa6CrsdsH84IZNGoq026sEdAMXQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZsShrtsFjoQ6gIsxO5gY7PvckgJVElCCf+YO7/qE3mt6MZ3oArKZHSqJA7STIG6XTRoC/UrZHJC2IV9p2jfwG7DepF4VJQ5JfOKg7SDhBTVLD1Y3InWn5QeUwD+0T5zGXO4rQDavFRSa21Di0facjNysbt+GTkTTmh1iZfEEuj0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iEeUuqDu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iEeUuqDu" Received: by smtp.kernel.org (Postfix) with ESMTPS id 84F52C4AF13; Thu, 5 Mar 2026 12:23:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772713415; bh=XMyV1p3aB7Qf2mFuPa6CrsdsH84IZNGoq026sEdAMXQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=iEeUuqDu3h+0eFXGuOOjtON1SiuUuCz7s0bkPtt4Ja1A2R86Kt3i5i8XePNjiLtFK kMnS0j+zdQhomHrZLlt1Wwz0xq96cojgFAL44dHXrEeqj/pwKLE61NKdLEpjbKGtHv dbJB+zkSzfP0x2N9aTFlGeOD/ompMSKG3kg+hbdUZ27Y7oq4MR4LYLNo7OryPVb4w6 xHKQj/dRmui2mKVAwBS6dGmqFQDRpsal0+GzdJthwslWiDgOBiyhAIU3/DiSQ5C6fq knKH3iFn7iytCraEUt3tidpVoH0Kxscenpp9esr5hdwEO+mMvspFKbpbF1M7bbWKzd +00fJxZfBBq5g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 760DEF3092C; Thu, 5 Mar 2026 12:23:35 +0000 (UTC) From: Radu Sabau via B4 Relay Date: Thu, 05 Mar 2026 14:23:30 +0200 Subject: [PATCH 4/4] iio: adc: ad4691: add SPI offload support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-ad4692-multichannel-sar-adc-driver-v1-4-336229a8dcc7@analog.com> References: <20260305-ad4692-multichannel-sar-adc-driver-v1-0-336229a8dcc7@analog.com> In-Reply-To: <20260305-ad4692-multichannel-sar-adc-driver-v1-0-336229a8dcc7@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772713413; l=25027; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=fsJYfVJAeFuv2N8CEoY4pRwap+ES24z5DGo+5a2M3YI=; b=8v8JFRQz/pAwK4RQsJ0ld0jvDSjFQt97MafVAPQJ0NKgxq2MJg3oZ1bNMiELvBITgMHsbfbXO cXH/3RhjvUHCKdsDscmVXTPZ+UQjwEApA0n8J2JNowRPlz2MfCNg3wU X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add SPI offload support to the AD4691 family driver to enable DMA-based RX stream acquisition. When an SPI offload is available, the driver switches to a pre-built SPI message with 32-bit transfers (4-byte frames aligned to DMA width) and registers a periodic offload trigger for autonomous, CPU-independent sampling. The offload path implements its own buffer setup ops (ad4691_offload_buffer_postenable/predisable) that enable the offload trigger and wire the DMAengine buffer, while the existing software triggered buffer path is retained as a fallback for non-offload configurations. Offload channel specs use a 32-bit storage/repeat with a 16-bit shift to extract ADC data from the MSBytes of each DMA word, matching the wire format in Manual Mode where SDO outputs ADC data directly without a command echo. Kconfig gains a dependency on IIO_BUFFER_DMAENGINE. Signed-off-by: Radu Sabau --- drivers/iio/adc/Kconfig | 1 + drivers/iio/adc/ad4691.c | 541 +++++++++++++++++++++++++++++++++++++++++++= +++- 2 files changed, 531 insertions(+), 11 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index d498f16c0816..93f090e9a562 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -144,6 +144,7 @@ config AD4691 depends on SPI select IIO_BUFFER select IIO_TRIGGERED_BUFFER + select IIO_BUFFER_DMAENGINE select REGMAP help Say yes here to build support for Analog Devices AD4691 Family MuxSAR diff --git a/drivers/iio/adc/ad4691.c b/drivers/iio/adc/ad4691.c index ab48f336e46c..7ec0a2555a4b 100644 --- a/drivers/iio/adc/ad4691.c +++ b/drivers/iio/adc/ad4691.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -21,11 +22,15 @@ #include #include #include +#include +#include #include #include #include =20 #include +#include +#include #include =20 #include @@ -49,6 +54,7 @@ */ #define AD4691_MANUAL_MODE_STD_FREQ(x, y) ((y) / (36 * ((x) + 1))) #define AD4691_BITS_PER_XFER 24 +#define AD4691_OFFLOAD_BITS_PER_WORD 32 #define AD4691_CNV_DUTY_CYCLE_NS 380 #define AD4691_MAX_CONV_PERIOD_US 800 =20 @@ -253,6 +259,43 @@ static const struct iio_chan_spec ad4693_manual_channe= ls[] =3D { AD4691_CHANNEL(7, 7, 16, 24, 8) }; =20 +/* + * Manual mode offload channels. + * + * Transfer format: 4-byte SPI frame to match 32-bit DMA width. + * In Manual Mode there is no command echo - SDO outputs ADC data directly. + * 16-bit ADC data in 2 MSBytes, shift=3D16 for extraction. + */ +static const struct iio_chan_spec ad4691_manual_offload_channels[] =3D { + AD4691_CHANNEL(0, 0, 16, 32, 16), + AD4691_CHANNEL(1, 1, 16, 32, 16), + AD4691_CHANNEL(2, 2, 16, 32, 16), + AD4691_CHANNEL(3, 3, 16, 32, 16), + AD4691_CHANNEL(4, 4, 16, 32, 16), + AD4691_CHANNEL(5, 5, 16, 32, 16), + AD4691_CHANNEL(6, 6, 16, 32, 16), + AD4691_CHANNEL(7, 7, 16, 32, 16), + AD4691_CHANNEL(8, 8, 16, 32, 16), + AD4691_CHANNEL(9, 9, 16, 32, 16), + AD4691_CHANNEL(10, 10, 16, 32, 16), + AD4691_CHANNEL(11, 11, 16, 32, 16), + AD4691_CHANNEL(12, 12, 16, 32, 16), + AD4691_CHANNEL(13, 13, 16, 32, 16), + AD4691_CHANNEL(14, 14, 16, 32, 16), + AD4691_CHANNEL(15, 15, 16, 32, 16) +}; + +static const struct iio_chan_spec ad4693_manual_offload_channels[] =3D { + AD4691_CHANNEL(0, 0, 16, 32, 16), + AD4691_CHANNEL(1, 1, 16, 32, 16), + AD4691_CHANNEL(2, 2, 16, 32, 16), + AD4691_CHANNEL(3, 3, 16, 32, 16), + AD4691_CHANNEL(4, 4, 16, 32, 16), + AD4691_CHANNEL(5, 5, 16, 32, 16), + AD4691_CHANNEL(6, 6, 16, 32, 16), + AD4691_CHANNEL(7, 7, 16, 32, 16) +}; + static const struct ad4691_chip_info ad4691_chips[] =3D { [AD4691_ID_AD4691] =3D { .channels =3D ad4691_channels, @@ -310,6 +353,17 @@ struct ad4691_state { struct hrtimer sampling_timer; ktime_t sampling_period; =20 + struct spi_offload *offload; + struct spi_offload_trigger *offload_trigger; + struct spi_offload_trigger *offload_trigger_periodic; + u64 offload_trigger_hz; + struct spi_message offload_msg; + /* Max 16 channels * 2 transfers (cmd + data) + 1 state reset + 1 conv st= art */ + struct spi_transfer offload_xfer[34]; + /* TX commands for manual and accumulator modes */ + u32 offload_tx_cmd[17]; + u32 offload_tx_reset; + u32 offload_tx_conv_stop; /* DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * Make the buffer large enough for one 24 bit sample and one 64 bit @@ -324,6 +378,65 @@ struct ad4691_state { } scan __aligned(IIO_DMA_MINALIGN); }; =20 +static const struct spi_offload_config ad4691_offload_config =3D { + .capability_flags =3D SPI_OFFLOAD_CAP_TRIGGER | + SPI_OFFLOAD_CAP_RX_STREAM_DMA, +}; + +static bool ad4691_offload_trigger_match(struct spi_offload_trigger *trigg= er, + enum spi_offload_trigger_type type, + u64 *args, u32 nargs) +{ + if (type !=3D SPI_OFFLOAD_TRIGGER_DATA_READY) + return false; + + /* + * Requires 2 args: + * args[0] is the trigger event (BUSY or DATA_READY). + * args[1] is the GPIO pin number (only GP0 supported). + */ + if (nargs !=3D 2) + return false; + + if (args[0] !=3D AD4691_TRIGGER_EVENT_BUSY && + args[0] !=3D AD4691_TRIGGER_EVENT_DATA_READY) + return false; + + if (args[1] !=3D AD4691_TRIGGER_PIN_GP0) + return false; + + return true; +} + +static int ad4691_offload_trigger_request(struct spi_offload_trigger *trig= ger, + enum spi_offload_trigger_type type, + u64 *args, u32 nargs) +{ + /* + * GP0 is configured as DATA_READY or BUSY in ad4691_config() + * based on the ADC mode. No additional configuration needed here. + */ + if (nargs !=3D 2) + return -EINVAL; + + return 0; +} + +static int ad4691_offload_trigger_validate(struct spi_offload_trigger *tri= gger, + struct spi_offload_trigger_config *config) +{ + if (config->type !=3D SPI_OFFLOAD_TRIGGER_DATA_READY) + return -EINVAL; + + return 0; +} + +static const struct spi_offload_trigger_ops ad4691_offload_trigger_ops =3D= { + .match =3D ad4691_offload_trigger_match, + .request =3D ad4691_offload_trigger_request, + .validate =3D ad4691_offload_trigger_validate, +}; + static void ad4691_disable_regulators(void *data) { struct ad4691_state *st =3D data; @@ -560,6 +673,9 @@ static int ad4691_get_sampling_freq(struct ad4691_state= *st) =20 switch (st->adc_mode) { case AD4691_MANUAL_MODE: + /* Offload uses periodic trigger, non-offload uses hrtimer */ + if (st->offload) + return st->offload_trigger_hz; return DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, ktime_to_ns(st->sampling_period)); case AD4691_CNV_CLOCK_MODE: @@ -600,6 +716,7 @@ static int __ad4691_set_sampling_freq(struct ad4691_sta= te *st, int freq) * ad4691_cnv_burst_period_ns - Compute the CNV_BURST_MODE PWM period. * @st: Driver state. * @n_active: Number of active channels. + * @is_offload: True for the SPI offload path, false for the triggered buf= fer path. * * The period must cover the full conversion time tOSC*(n_active+1) plus * the SPI transfer time for reading the accumulator results and issuing @@ -608,7 +725,7 @@ static int __ad4691_set_sampling_freq(struct ad4691_sta= te *st, int freq) * Return: Period in nanoseconds. */ static u64 ad4691_cnv_burst_period_ns(struct ad4691_state *st, - int n_active) + int n_active, bool is_offload) { unsigned int osc_idx =3D AD4691_OSC_1MHZ; u64 osc_freq, conv_time_ns, spi_bits, spi_time_ns; @@ -620,7 +737,20 @@ static u64 ad4691_cnv_burst_period_ns(struct ad4691_st= ate *st, osc_freq =3D ad4691_int_osc_val[osc_idx]; conv_time_ns =3D div64_u64((u64)(n_active + 1) * NSEC_PER_SEC, osc_freq); =20 - spi_bits =3D (u64)n_active * 32 + 24; + if (is_offload) { + /* + * Offload SPI sequence per trigger: n_active AVG_IN reads + * (4 B each) + STATE_RESET (4 B). + */ + spi_bits =3D (u64)(n_active + 1) * 32; + } else { + /* + * Non-offload sequence per trigger: n_active AVG_IN reads + * (4 B: 2 cmd + 2 data each) + STATE_RESET (3 B). + */ + spi_bits =3D (u64)n_active * 32 + 24; + } + spi_time_ns =3D div64_u64(spi_bits * NSEC_PER_SEC, st->spi->max_speed_hz); =20 /* 50% margin on SPI time absorbs OS scheduling jitter. */ @@ -662,7 +792,9 @@ static int ad4691_pwm_get(struct spi_device *spi, struc= t ad4691_state *st) * transfer time. Use worst-case channel count here; the period * is refined at buffer enable time when the active count is known. */ - u64 period_ns =3D ad4691_cnv_burst_period_ns(st, st->chip->num_channels); + u64 period_ns =3D ad4691_cnv_burst_period_ns(st, + st->chip->num_channels, + false); int pwm_freq =3D (int)max(1ULL, div64_u64(NSEC_PER_SEC, period_ns)); =20 return __ad4691_set_sampling_freq(st, pwm_freq); @@ -683,6 +815,26 @@ static int ad4691_set_sampling_freq(struct iio_dev *in= dio_dev, unsigned int freq mutex_lock(&st->lock); switch (st->adc_mode) { case AD4691_MANUAL_MODE: + /* For offload mode, validate and store frequency for periodic trigger */ + if (st->offload) { + struct spi_offload_trigger_config config =3D { + .type =3D SPI_OFFLOAD_TRIGGER_PERIODIC, + .periodic =3D { + .frequency_hz =3D freq, + }, + }; + + ret =3D spi_offload_trigger_validate(st->offload_trigger_periodic, + &config); + if (ret) + goto exit; + + st->offload_trigger_hz =3D config.periodic.frequency_hz; + ret =3D 0; + goto exit; + } + + /* Non-offload: update hrtimer sampling period */ if (!freq || freq > st->chip->max_rate) { ret =3D -EINVAL; goto exit; @@ -719,7 +871,9 @@ static int ad4691_set_sampling_freq(struct iio_dev *ind= io_dev, unsigned int freq * count. The exact period is refined at buffer enable time when * the active channel count is known. */ - period_ns =3D ad4691_cnv_burst_period_ns(st, st->chip->num_channels); + period_ns =3D ad4691_cnv_burst_period_ns(st, + st->chip->num_channels, + false); pwm_freq =3D (int)max(1ULL, div64_u64(NSEC_PER_SEC, period_ns)); ret =3D __ad4691_set_sampling_freq(st, pwm_freq); =20 @@ -839,6 +993,13 @@ static int ad4691_read_raw(struct iio_dev *indio_dev, =20 /* * Wait for conversion to complete using a timed delay. + * An interrupt-driven approach is not used for single-shot + * reads: the DATA_READY IRQ is registered only in the + * triggered buffer path, and offload configurations route + * DATA_READY to the SPI engine, not to a CPU interrupt. + * Using usleep_range keeps the driver simple and correct + * across all configurations. + * * CNV_CLOCK_MODE conversion time is bounded by * AD4691_MAX_CONV_PERIOD_US. All other modes are driven by * the internal oscillator; two oscillator periods cover a @@ -1072,6 +1233,294 @@ static const struct iio_buffer_setup_ops ad4691_buf= fer_setup_ops =3D { .postdisable =3D &ad4691_buffer_postdisable, }; =20 +static int ad4691_offload_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + struct spi_offload_trigger_config config =3D { }; + struct spi_offload_trigger *trigger; + struct spi_transfer *xfer =3D st->offload_xfer; + int ret, num_xfers =3D 0; + int active_chans[16]; + unsigned int bit; + int n_active =3D 0; + int i; + + memset(xfer, 0, sizeof(st->offload_xfer)); + + /* Collect active channels in scan order */ + iio_for_each_active_channel(indio_dev, bit) + active_chans[n_active++] =3D bit; + + /* + * MANUAL_MODE uses a periodic (PWM) trigger and reads directly from the = ADC. + * All other modes use the DATA_READY trigger and read from accumulators. + */ + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + config.type =3D SPI_OFFLOAD_TRIGGER_PERIODIC; + config.periodic.frequency_hz =3D st->offload_trigger_hz; + trigger =3D st->offload_trigger_periodic; + if (!trigger) + return -EINVAL; + } else { + if (st->adc_mode !=3D AD4691_AUTONOMOUS_MODE) + ret =3D regmap_write(st->regmap, AD4691_GPIO_MODE1_REG, + AD4691_DATA_READY); + else + ret =3D regmap_write(st->regmap, AD4691_GPIO_MODE1_REG, + AD4691_ADC_BUSY); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_STATE_RESET_REG, + AD4691_STATE_RESET_ALL); + if (ret) + return ret; + + /* Configure accumulator masks - 0 =3D enabled, 1 =3D masked */ + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK1_REG, + ~(*indio_dev->active_scan_mask) & 0xFF); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK2_REG, + ~(*indio_dev->active_scan_mask >> 8) & 0xFF); + if (ret) + return ret; + + /* Configure sequencer with active channels */ + ret =3D regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, + *indio_dev->active_scan_mask); + if (ret) + return ret; + + /* Configure accumulator count limit for each active channel */ + iio_for_each_active_channel(indio_dev, bit) { + ret =3D regmap_write(st->regmap, AD4691_ACC_COUNT_LIMIT(bit), + AD4691_ACC_COUNT_VAL); + if (ret) + return ret; + } + + config.type =3D SPI_OFFLOAD_TRIGGER_DATA_READY; + trigger =3D st->offload_trigger; + } + + switch (st->adc_mode) { + case AD4691_CNV_CLOCK_MODE: + case AD4691_CNV_BURST_MODE: + case AD4691_AUTONOMOUS_MODE: + case AD4691_SPI_BURST_MODE: + /* + * AUTONOMOUS mode: must stop conversion before reading. + * Sequence: CONV_STOP -> read accumulators -> STATE_RESET -> CONV_START + */ + if (st->adc_mode =3D=3D AD4691_AUTONOMOUS_MODE) { + /* + * With bits_per_word=3D32, SPI engine reads native u32 + * and transmits MSB first. No byte-swap needed. + */ + st->offload_tx_conv_stop =3D (AD4691_OSC_EN_REG >> 8) << 24 | + (AD4691_OSC_EN_REG & 0xFF) << 16 | + 0x00 << 8; /* CONV_START =3D 0 to stop */ + xfer[num_xfers].tx_buf =3D &st->offload_tx_conv_stop; + xfer[num_xfers].len =3D 4; + xfer[num_xfers].bits_per_word =3D 32; + xfer[num_xfers].speed_hz =3D st->spi->max_speed_hz; + xfer[num_xfers].cs_change =3D 1; + num_xfers++; + } + + /* + * Single transfer per channel: 2-byte cmd + 2-byte data =3D 4 bytes + * (one 32-bit SPI Engine DMA word). + * + * AVG_IN registers are used instead of ACC_IN. See the + * AD4691_OFFLOAD_CHANNEL macro for a detailed explanation. + * + * RX word layout (big-endian): [cmd_hi, cmd_lo, d_hi, d_lo] + */ + for (i =3D 0; i < n_active; i++) { + unsigned int reg; + int ch =3D active_chans[i]; + + reg =3D AD4691_AVG_IN(ch); + st->offload_tx_cmd[ch] =3D + ((reg >> 8) | 0x80) << 24 | + (reg & 0xFF) << 16; + xfer[num_xfers].tx_buf =3D &st->offload_tx_cmd[ch]; + xfer[num_xfers].len =3D 4; + xfer[num_xfers].bits_per_word =3D 32; + xfer[num_xfers].speed_hz =3D st->spi->max_speed_hz; + xfer[num_xfers].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + xfer[num_xfers].cs_change =3D 1; + num_xfers++; + } + + /* + * State reset: clear accumulator so DATA_READY can fire again. + * + * With bits_per_word=3D32, SPI engine reads native u32 + * and transmits MSB first. No byte-swap needed. + * + * The device uses address-descending mode when streaming, so + * the 4th byte is written to the OSC_EN register. In AUTONOMOUS + * and SPI_BURST modes we want OSC_EN re-asserted, therefore set + * the 4th byte to 0x01 for those modes. + */ + if (st->adc_mode =3D=3D AD4691_AUTONOMOUS_MODE || + st->adc_mode =3D=3D AD4691_SPI_BURST_MODE) { + st->offload_tx_reset =3D ((AD4691_STATE_RESET_REG >> 8) << 24) | + ((AD4691_STATE_RESET_REG & 0xFF) << 16) | + (0x01 << 8) | 0x01; + } else { + st->offload_tx_reset =3D ((AD4691_STATE_RESET_REG >> 8) << 24) | + ((AD4691_STATE_RESET_REG & 0xFF) << 16) | + (0x01 << 8); + } + + xfer[num_xfers].tx_buf =3D &st->offload_tx_reset; + xfer[num_xfers].len =3D 4; + xfer[num_xfers].bits_per_word =3D 32; + xfer[num_xfers].speed_hz =3D st->spi->max_speed_hz; + xfer[num_xfers].cs_change =3D 0; + num_xfers++; + + break; + + case AD4691_MANUAL_MODE: + /* + * Manual mode with CNV tied to CS: Each CS toggle triggers a + * conversion AND reads the previous conversion result (pipeline). + */ + for (i =3D 0; i < n_active; i++) { + st->offload_tx_cmd[num_xfers] =3D AD4691_ADC_CHAN(active_chans[i]) << 2= 4; + xfer[num_xfers].tx_buf =3D &st->offload_tx_cmd[num_xfers]; + xfer[num_xfers].len =3D 4; + xfer[num_xfers].bits_per_word =3D 32; + xfer[num_xfers].speed_hz =3D st->spi->max_speed_hz; + xfer[num_xfers].cs_change =3D 1; + xfer[num_xfers].cs_change_delay.value =3D 1000; + xfer[num_xfers].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + /* First transfer RX is garbage - don't capture it */ + if (num_xfers) + xfer[num_xfers].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + num_xfers++; + } + + /* Final NOOP to flush pipeline and get last channel's data */ + st->offload_tx_cmd[num_xfers] =3D AD4691_NOOP << 24; + xfer[num_xfers].tx_buf =3D &st->offload_tx_cmd[num_xfers]; + xfer[num_xfers].len =3D 4; + xfer[num_xfers].bits_per_word =3D 32; + xfer[num_xfers].speed_hz =3D st->spi->max_speed_hz; + xfer[num_xfers].cs_change =3D 0; + xfer[num_xfers].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + num_xfers++; + break; + + default: + return -EINVAL; + } + + if (num_xfers =3D=3D 0) + return -EINVAL; + + /* + * For MANUAL_MODE, validate that the trigger frequency is low enough + * for all SPI transfers to complete. Each transfer is 32 bits. + * Add 50% margin for CS setup/hold and other overhead. + */ + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + u64 min_period_ns; + u64 trigger_period_ns; + + /* Time for all transfers in nanoseconds, with 50% overhead margin */ + min_period_ns =3D div64_u64((u64)num_xfers * AD4691_OFFLOAD_BITS_PER_WOR= D * + NSEC_PER_SEC * 3, + st->spi->max_speed_hz * 2); + + trigger_period_ns =3D div64_u64(NSEC_PER_SEC, st->offload_trigger_hz); + + if (trigger_period_ns < min_period_ns) + return -EINVAL; + } + + spi_message_init_with_transfers(&st->offload_msg, xfer, num_xfers); + st->offload_msg.offload =3D st->offload; + + ret =3D spi_optimize_message(st->spi, &st->offload_msg); + if (ret) + return ret; + + /* + * Start conversions before enabling the trigger for all non-MANUAL modes. + * If the trigger is enabled first, the SPI engine blocks waiting for + * DATA_READY, and any subsequent SPI write times out. + * + * MANUAL_MODE: CNV is tied to CS; conversion starts with each transfer. + * CNV_BURST_MODE: cnv_period updated above; PWM starts conversions. + * AUTONOMOUS_MODE: OSC_EN=3D1 written here; DATA_READY fires when + * accumulation completes and triggers the SPI engine offload sequence. + */ + if (st->adc_mode !=3D AD4691_MANUAL_MODE) { + if (st->adc_mode =3D=3D AD4691_CNV_BURST_MODE) + st->cnv_period =3D + ad4691_cnv_burst_period_ns(st, n_active, true); + ret =3D ad4691_sampling_enable(st, true); + if (ret) + goto err_unoptimize_message; + } + + ret =3D spi_offload_trigger_enable(st->offload, trigger, &config); + if (ret) + goto err_sampling_disable; + + return 0; + +err_sampling_disable: + ad4691_sampling_enable(st, false); +err_unoptimize_message: + spi_unoptimize_message(&st->offload_msg); + return ret; +} + +static int ad4691_offload_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + struct spi_offload_trigger *trigger; + int ret =3D 0, tmp; + + trigger =3D (st->adc_mode =3D=3D AD4691_MANUAL_MODE) ? + st->offload_trigger_periodic : st->offload_trigger; + + spi_offload_trigger_disable(st->offload, trigger); + spi_unoptimize_message(&st->offload_msg); + + /* Stop conversions and reset sequencer state (not needed for MANUAL_MODE= ) */ + if (st->adc_mode !=3D AD4691_MANUAL_MODE) { + tmp =3D ad4691_sampling_enable(st, false); + if (!ret) + ret =3D tmp; + + tmp =3D regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, + AD4691_SEQ_ALL_CHANNELS_OFF); + if (!ret) + ret =3D tmp; + + tmp =3D regmap_write(st->regmap, AD4691_STATE_RESET_REG, + AD4691_STATE_RESET_ALL); + if (!ret) + ret =3D tmp; + } + + return ret; +} + +static const struct iio_buffer_setup_ops ad4691_offload_buffer_setup_ops = =3D { + .postenable =3D &ad4691_offload_buffer_postenable, + .predisable =3D &ad4691_offload_buffer_predisable, +}; + static irqreturn_t ad4691_irq(int irq, void *private) { struct iio_dev *indio_dev =3D private; @@ -1353,10 +1802,17 @@ static void ad4691_setup_channels(struct iio_dev *i= ndio_dev, struct ad4691_state *st) { if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { - if (st->chip->num_channels =3D=3D 8) - indio_dev->channels =3D ad4693_manual_channels; - else - indio_dev->channels =3D ad4691_manual_channels; + if (st->offload) { + if (st->chip->num_channels =3D=3D 8) + indio_dev->channels =3D ad4693_manual_offload_channels; + else + indio_dev->channels =3D ad4691_manual_offload_channels; + } else { + if (st->chip->num_channels =3D=3D 8) + indio_dev->channels =3D ad4693_manual_channels; + else + indio_dev->channels =3D ad4691_manual_channels; + } } else { indio_dev->channels =3D st->chip->channels; } @@ -1364,6 +1820,54 @@ static void ad4691_setup_channels(struct iio_dev *in= dio_dev, indio_dev->num_channels =3D st->chip->num_channels; } =20 +static int ad4691_setup_offload(struct iio_dev *indio_dev, + struct ad4691_state *st) +{ + struct device *dev =3D &st->spi->dev; + struct dma_chan *rx_dma; + int ret; + + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + st->offload_trigger_periodic =3D devm_spi_offload_trigger_get(dev, + st->offload, SPI_OFFLOAD_TRIGGER_PERIODIC); + if (IS_ERR(st->offload_trigger_periodic)) + return dev_err_probe(dev, + PTR_ERR(st->offload_trigger_periodic), + "failed to get periodic offload trigger\n"); + + st->offload_trigger_hz =3D AD4691_MANUAL_MODE_STD_FREQ(st->chip->num_cha= nnels, + st->spi->max_speed_hz); + } else { + struct spi_offload_trigger_info trigger_info =3D { + .fwnode =3D dev_fwnode(dev), + .ops =3D &ad4691_offload_trigger_ops, + .priv =3D st, + }; + + ret =3D devm_spi_offload_trigger_register(dev, &trigger_info); + if (ret) + return dev_err_probe(dev, ret, + "failed to register offload trigger\n"); + + st->offload_trigger =3D devm_spi_offload_trigger_get(dev, + st->offload, SPI_OFFLOAD_TRIGGER_DATA_READY); + if (IS_ERR(st->offload_trigger)) + return dev_err_probe(dev, PTR_ERR(st->offload_trigger), + "failed to get offload trigger\n"); + } + + rx_dma =3D devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); + if (IS_ERR(rx_dma)) + return dev_err_probe(dev, PTR_ERR(rx_dma), + "failed to get offload RX DMA\n"); + + indio_dev->modes =3D INDIO_DIRECT_MODE | INDIO_BUFFER_HARDWARE; + indio_dev->setup_ops =3D &ad4691_offload_buffer_setup_ops; + + return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, + rx_dma, IIO_BUFFER_DIRECTION_IN); +} + static int ad4691_setup_triggered_buffer(struct iio_dev *indio_dev, struct ad4691_state *st) { @@ -1455,6 +1959,14 @@ static int ad4691_probe(struct spi_device *spi) return dev_err_probe(dev, PTR_ERR(st->regmap), "Failed to initialize regmap\n"); =20 + st->offload =3D devm_spi_offload_get(dev, spi, &ad4691_offload_config); + if (IS_ERR(st->offload)) { + if (PTR_ERR(st->offload) !=3D -ENODEV) + return dev_err_probe(dev, PTR_ERR(st->offload), + "failed to get SPI offload\n"); + st->offload =3D NULL; + } + st->chip =3D spi_get_device_match_data(spi); if (!st->chip) { st->chip =3D (void *)spi_get_device_id(spi)->driver_data; @@ -1481,9 +1993,15 @@ static int ad4691_probe(struct spi_device *spi) =20 ad4691_setup_channels(indio_dev, st); =20 - ret =3D ad4691_setup_triggered_buffer(indio_dev, st); - if (ret) - return ret; + if (st->offload) { + ret =3D ad4691_setup_offload(indio_dev, st); + if (ret) + return ret; + } else { + ret =3D ad4691_setup_triggered_buffer(indio_dev, st); + if (ret) + return ret; + } =20 return devm_iio_device_register(dev, indio_dev); } @@ -1510,3 +2028,4 @@ module_spi_driver(ad4691_driver); MODULE_AUTHOR("Radu Sabau "); MODULE_DESCRIPTION("Analog Devices AD4691 Family ADC Driver"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_DMA_BUFFER"); --=20 2.43.0