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charset="utf-8" Convert the bindings document for Xilinx DMA. No changes to existing binding description. Signed-off-by: Abin Joseph --- v4: -> Fix the dt_binding_check error v3: -> Update the subject heading -> Remove examples for cdma and mcdma -> Fix the syntax issue for the clocks -> Squash the interrupt use case for axistream connected cases. -> Reorder the list as per the writing bindings v2: -> Add examples for each compatible -> Remove the note added -> Use 'enum' rather than 'anyOf' and 'const' -> Wrap 80 char per line for descriptions =20 -> Add dma-controller yaml reference =20 -> Add -| for paragraph separation=20 -> Remove labels from the examples --- .../bindings/dma/xilinx/xilinx_dma.txt | 111 ------- .../bindings/dma/xilinx/xlnx,axi-dma.yaml | 299 ++++++++++++++++++ 2 files changed, 299 insertions(+), 111 deletions(-) delete mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma= .txt create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-d= ma.yaml diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/= Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt deleted file mode 100644 index b567107270cb..000000000000 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ /dev/null @@ -1,111 +0,0 @@ -Xilinx AXI VDMA engine, it does transfers between memory and video devices. -It can be configured to have one channel or two channels. If configured -as two channels, one is to transmit to the video device and another is -to receive from the video device. - -Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream -target devices. It can be configured to have one channel or two channels. -If configured as two channels, one is to transmit to the device and another -is to receive from the device. - -Xilinx AXI CDMA engine, it does transfers between memory-mapped source -address and a memory-mapped destination address. - -Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream -target devices. It can be configured to have up to 16 independent transmit -and receive channels. - -Required properties: -- compatible: Should be one of- - "xlnx,axi-vdma-1.00.a" - "xlnx,axi-dma-1.00.a" - "xlnx,axi-cdma-1.00.a" - "xlnx,axi-mcdma-1.00.a" -- #dma-cells: Should be <1>, see "dmas" property below -- reg: Should contain VDMA registers location and length. -- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). -- dma-ranges: Should be as the following . -- dma-channel child node: Should have at least one channel and can have up= to - two channels per device. This node specifies the properties of each - DMA channel (see child node properties below). -- clocks: Input clock specifier. Refer to common clock bindings. -- clock-names: List of input clocks - For VDMA: - Required elements: "s_axi_lite_aclk" - Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk", - "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" - For CDMA: - Required elements: "s_axi_lite_aclk", "m_axi_aclk" - For AXIDMA and MCDMA: - Required elements: "s_axi_lite_aclk" - Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", - "m_axi_sg_aclk" - -Required properties for VDMA: -- xlnx,num-fstores: Should be the number of framebuffers as configured in = h/w. - -Optional properties for AXI DMA and MCDMA: -- xlnx,sg-length-width: Should be set to the width in bits of the length - register as configured in h/w. Takes values {8...26}. If the property - is missing or invalid then the default value 23 is used. This is the - maximum value that is supported by all IP versions. - -Optional properties for AXI DMA: -- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream I= P. -- xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is = from - 0-255. Setting this value to zero disables the delay timer interrupt. - 1 timeout interval =3D 125 * clock period of SG clock. -Optional properties for VDMA: -- xlnx,flush-fsync: Tells which channel to Flush on Frame sync. - It takes following values: - {1}, flush both channels - {2}, flush mm2s channel - {3}, flush s2mm channel - -Required child node properties: -- compatible: - For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or - "xlnx,axi-vdma-s2mm-channel". - For CDMA: It should be "xlnx,axi-cdma-channel". - For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel" - or "xlnx,axi-dma-s2mm-channel". -- interrupts: Should contain per channel VDMA interrupts. -- xlnx,datawidth: Should contain the stream data width, take values - {32,64...1024}. - -Optional child node properties: -- xlnx,include-dre: Tells hardware is configured for Data - Realignment Engine. -Optional child node properties for VDMA: -- xlnx,genlock-mode: Tells Genlock synchronization is - enabled/disabled in hardware. -- xlnx,enable-vert-flip: Tells vertical flip is - enabled/disabled in hardware(S2MM path). -Optional child node properties for MCDMA: -- dma-channels: Number of dma channels in child node. - -Example: -++++++++ - -axi_vdma_0: axivdma@40030000 { - compatible =3D "xlnx,axi-vdma-1.00.a"; - #dma_cells =3D <1>; - reg =3D < 0x40030000 0x10000 >; - dma-ranges =3D <0x00000000 0x00000000 0x40000000>; - xlnx,num-fstores =3D <0x8>; - xlnx,flush-fsync =3D <0x1>; - xlnx,addrwidth =3D <0x20>; - clocks =3D <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>; - clock-names =3D "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", - "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"; - dma-channel@40030000 { - compatible =3D "xlnx,axi-vdma-mm2s-channel"; - interrupts =3D < 0 54 4 >; - xlnx,datawidth =3D <0x40>; - } ; - dma-channel@40030030 { - compatible =3D "xlnx,axi-vdma-s2mm-channel"; - interrupts =3D < 0 53 4 >; - xlnx,datawidth =3D <0x40>; - } ; -} ; diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml= b/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml new file mode 100644 index 000000000000..7956e5d3783f --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml @@ -0,0 +1,299 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/xilinx/xlnx,axi-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx AXI VDMA, DMA, CDMA and MCDMA IP + +maintainers: + - Radhey Shyam Pandey + - Abin Joseph + +description: | + Xilinx AXI VDMA engine, it does transfers between memory and video devic= es. + It can be configured to have one channel or two channels. If configured + as two channels, one is to transmit to the video device and another is + to receive from the video device. + + Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream + target devices. It can be configured to have one channel or two channels. + If configured as two channels, one is to transmit to the device and anot= her + is to receive from the device. + + Xilinx AXI CDMA engine, it does transfers between memory-mapped source + address and a memory-mapped destination address. + + Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream + target devices. It can be configured to have up to 16 independent transm= it + and receive channels. + +properties: + compatible: + enum: + - xlnx,axi-cdma-1.00.a + - xlnx,axi-dma-1.00.a + - xlnx,axi-mcdma-1.00.a + - xlnx,axi-vdma-1.00.a + + reg: + maxItems: 1 + + "#dma-cells": + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + interrupts: + items: + - description: Interrupt for single channel (MM2S or S2MM) + - description: Interrupt for dual channel configuration + minItems: 1 + description: + Interrupt lines for the DMA controller. Only used when + xlnx,axistream-connected is present (DMA connected to AXI Stream + IP). When child dma-channel nodes are present, interrupts are + specified in the child nodes instead. + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + dma-ranges: true + + xlnx,addrwidth: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [32, 64] + description: The DMA addressing size in bits. + + xlnx,num-fstores: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + description: Should be the number of framebuffers as configured in h/w. + + xlnx,flush-fsync: + type: boolean + description: Tells which channel to Flush on Frame sync. + + xlnx,sg-length-width: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 8 + maximum: 26 + default: 23 + description: + Width in bits of the length register as configured in hardware. + + xlnx,irq-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + description: + Tells the interrupt delay timeout value. Valid range is from 0-255. + Setting this value to zero disables the delay timer interrupt. + 1 timeout interval =3D 125 * clock period of SG clock. + + xlnx,axistream-connected: + type: boolean + description: Tells whether DMA is connected to AXI stream IP. + +patternProperties: + "^dma-channel(-mm2s|-s2mm)?$": + type: object + description: + Should have at least one channel and can have up to two channels per + device. This node specifies the properties of each DMA channel. + + properties: + compatible: + enum: + - xlnx,axi-vdma-mm2s-channel + - xlnx,axi-vdma-s2mm-channel + - xlnx,axi-cdma-channel + - xlnx,axi-dma-mm2s-channel + - xlnx,axi-dma-s2mm-channel + + interrupts: + maxItems: 1 + + xlnx,datawidth: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [32, 64, 128, 256, 512, 1024] + description: Should contain the stream data width, take values {32= ,64...1024}. + + xlnx,include-dre: + type: boolean + description: Tells hardware is configured for Data Realignment Eng= ine. + + xlnx,genlock-mode: + type: boolean + description: Tells Genlock synchronization is enabled/disabled in = hardware. + + xlnx,enable-vert-flip: + type: boolean + description: + Tells vertical flip is enabled/disabled in hardware(S2MM path). + + dma-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of dma channels in child node. + + required: + - compatible + - interrupts + - xlnx,datawidth + + additionalProperties: false + +allOf: + - $ref: ../dma-controller.yaml# + + - if: + properties: + compatible: + contains: + const: xlnx,axi-vdma-1.00.a + then: + properties: + clock-names: + items: + - const: s_axi_lite_aclk + - const: m_axi_mm2s_aclk + - const: m_axi_s2mm_aclk + - const: m_axis_mm2s_aclk + - const: s_axis_s2mm_aclk + minItems: 1 + interrupts: false + patternProperties: + "^dma-channel(-mm2s|-s2mm)?$": + properties: + compatible: + enum: + - xlnx,axi-vdma-mm2s-channel + - xlnx,axi-vdma-s2mm-channel + required: + - xlnx,num-fstores + + - if: + properties: + compatible: + contains: + const: xlnx,axi-cdma-1.00.a + then: + properties: + clock-names: + items: + - const: s_axi_lite_aclk + - const: m_axi_aclk + interrupts: false + patternProperties: + "^dma-channel(-mm2s|-s2mm)?$": + properties: + compatible: + enum: + - xlnx,axi-cdma-channel + + - if: + properties: + compatible: + contains: + enum: + - xlnx,axi-dma-1.00.a + - xlnx,axi-mcdma-1.00.a + then: + properties: + clock-names: + items: + - const: s_axi_lite_aclk + - const: m_axi_mm2s_aclk + - const: m_axi_s2mm_aclk + - const: m_axi_sg_aclk + minItems: 1 + patternProperties: + "^dma-channel(-mm2s|-s2mm)?(@[0-9a-f]+)?$": + properties: + compatible: + enum: + - xlnx,axi-dma-mm2s-channel + - xlnx,axi-dma-s2mm-channel + +required: + - "#dma-cells" + - reg + - xlnx,addrwidth + - dma-ranges + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + dma-controller@40030000 { + compatible =3D "xlnx,axi-vdma-1.00.a"; + #dma-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0x40030000 0x10000>; + dma-ranges =3D <0x0 0x0 0x40000000>; + xlnx,num-fstores =3D <8>; + xlnx,flush-fsync; + xlnx,addrwidth =3D <32>; + clocks =3D <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>; + clock-names =3D "s_axi_lite_aclk", "m_axi_mm2s_aclk", + "m_axi_s2mm_aclk", "m_axis_mm2s_aclk", + "s_axis_s2mm_aclk"; + + dma-channel-mm2s { + compatible =3D "xlnx,axi-vdma-mm2s-channel"; + interrupts =3D ; + xlnx,datawidth =3D <64>; + }; + + dma-channel-s2mm { + compatible =3D "xlnx,axi-vdma-s2mm-channel"; + interrupts =3D ; + xlnx,datawidth =3D <64>; + }; + }; + + - | + #include + + dma-controller@a4030000 { + compatible =3D "xlnx,axi-dma-1.00.a"; + #dma-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0xa4030000 0x10000>; + dma-ranges =3D <0x0 0x0 0x40000000>; + xlnx,addrwidth =3D <32>; + xlnx,sg-length-width =3D <14>; + clocks =3D <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>; + clock-names =3D "s_axi_lite_aclk", "m_axi_mm2s_aclk", + "m_axi_s2mm_aclk", "m_axi_sg_aclk"; + + dma-channel-mm2s { + compatible =3D "xlnx,axi-dma-mm2s-channel"; + interrupts =3D ; + xlnx,datawidth =3D <64>; + xlnx,include-dre; + }; + + dma-channel-s2mm { + compatible =3D "xlnx,axi-dma-s2mm-channel"; + interrupts =3D ; + xlnx,datawidth =3D <64>; + xlnx,include-dre; + }; + }; --=20 2.43.0