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charset="utf-8" The Interface Plus [IFP] Mezzanine is an hardware expansion add-on board designed to be stacked on top of Lemans EVK. It has following peripherals : - 4x Type A USB ports in host mode. - TC9563 PCIe switch, which has following three downstream ports (DSP) : - 1st DSP is routed to an M.2 E-key connector, intended for WLAN modules. - 2nd DSP is routed to an M.2 B-key connector, intended for cellular modems. - 3rd DSP with support for Dual Ethernet ports. - eMMC. - Additional 2.5GbE Ethernet PHY connected to native EMAC with support for MAC Address configuration via NVMEM. - EEPROM. - LVDS Display. - 2*mini DP. Add support for following peripherals : - TC9563 PCIe Switch. - Additional 2.5GbE Ethernet Port. - EEPROM. Enable support for USB hub, LVDS display and mini-DP later once dependent changes are available in lemans-evk core-kit. Written with inputs from : Mohd Ayaan Anwar - Ethernet. Krishna Chaitanya Chundru - PCIe Monish Chunara - EEPROM. Signed-off-by: Umang Chheda Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../dts/qcom/lemans-evk-ifp-mezzanine.dtso | 263 ++++++++++++++++++ 2 files changed, 267 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 6d87be639aac..9872bbab2c71 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -45,6 +45,10 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-camera.dtb lemans-evk-el2-dtbs :=3D lemans-evk.dtb lemans-el2.dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-el2.dtb + +lemans-evk-ifp-mezzanine-dtbs :=3D lemans-evk.dtb lemans-evk-ifp-mezzanine= .dtbo + +dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-ifp-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/= arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso new file mode 100644 index 000000000000..268fc6b05d4b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + model =3D "Qualcomm Technologies, Inc. Lemans-evk IFP Mezzanine"; + + vreg_0p9: regulator-0v9 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_0P9"; + + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_1P8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +ðernet1 { + phy-handle =3D <&hsgmii_phy1>; + phy-mode =3D "2500base-x"; + + pinctrl-0 =3D <ðernet1_default>; + pinctrl-names =3D "default"; + + snps,mtl-rx-config =3D <&mtl_rx_setup1>; + snps,mtl-tx-config =3D <&mtl_tx_setup1>; + + nvmem-cells =3D <&mac_addr1>; + nvmem-cell-names =3D "mac-address"; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + hsgmii_phy1: ethernet-phy@18 { + compatible =3D "ethernet-phy-id004d.d101"; + reg =3D <0x18>; + reset-gpios =3D <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; + }; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; +}; + +&i2c18 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + eeprom@52 { + compatible =3D "giantec,gt24c256c", "atmel,24c256"; + reg =3D <0x52>; + pagesize =3D <64>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + mac_addr1: mac-addr@0 { + reg =3D <0x0 0x6>; + }; + }; + }; +}; + +&pcie0 { + iommu-map =3D <0x0 &pcie_smmu 0x0 0x1>, + <0x100 &pcie_smmu 0x1 0x1>, + <0x208 &pcie_smmu 0x2 0x1>, + <0x210 &pcie_smmu 0x3 0x1>, + <0x218 &pcie_smmu 0x4 0x1>, + <0x300 &pcie_smmu 0x5 0x1>, + <0x400 &pcie_smmu 0x6 0x1>, + <0x500 &pcie_smmu 0x7 0x1>, + <0x501 &pcie_smmu 0x8 0x1>; +}; + +&pcieport0 { + #address-cells =3D <3>; + #size-cells =3D <2>; + + pcie@0,0 { + compatible =3D "pci1179,0623"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x2 0xff>; + + vddc-supply =3D <&vreg_0p9>; + vdd18-supply =3D <&vreg_1p8>; + vdd09-supply =3D <&vreg_0p9>; + vddio1-supply =3D <&vreg_1p8>; + vddio2-supply =3D <&vreg_1p8>; + vddio18-supply =3D <&vreg_1p8>; + + i2c-parent =3D <&i2c18 0x77>; + + resx-gpios =3D <&tlmm 140 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&tc9563_resx_n>; + pinctrl-names =3D "default"; + + pcie@1,0 { + reg =3D <0x20800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x3 0xff>; + }; + + pcie@2,0 { + reg =3D <0x21000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x4 0xff>; + }; + + pcie@3,0 { + reg =3D <0x21800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + bus-range =3D <0x5 0xff>; + + pci@0,0 { + reg =3D <0x50000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + + pci@0,1 { + reg =3D <0x50100 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + }; + }; +}; + +&serdes1 { + phy-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + +&tlmm { + ethernet1_default: ethernet1-default-state { + ethernet1-mdc-pins { + pins =3D "gpio20"; + function =3D "emac1_mdc"; + drive-strength =3D <16>; + bias-pull-up; + }; + + ethernet1-mdio-pins { + pins =3D "gpio21"; + function =3D "emac1_mdio"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; + + tc9563_resx_n: tc9563-resx-state { + pins =3D "gpio140"; + function =3D "gpio"; + bias-disable; + /* Reset pin of tc9563 is active low hence set default + * state of this pin to output-high. + */ + output-high; + }; +}; --=20 2.34.1