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Wed, 04 Mar 2026 03:33:22 -0800 (PST) Received: from iku.example.org ([2a06:5906:61b:2d00:bddd:d1ed:d1ee:a876]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439b03db76bsm27345379f8f.18.2026.03.04.03.33.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 03:33:22 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Geert Uytterhoeven , Philipp Zabel , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 6/7] irqchip/renesas-rzv2h: Add CA55 software interrupt support Date: Wed, 4 Mar 2026 11:33:16 +0000 Message-ID: <20260304113317.129339-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260304113317.129339-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260304113317.129339-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The RZ/V2H ICU exposes four software-triggerable interrupts targeting the CA55 cores (int-ca55-0 to int-ca55-3). Add support for these interrupts to enable IRQ injection via the generic IRQ injection framework. Add a dedicated rzv2h_icu_swint_chip irq_chip for the CA55 region and implement rzv2h_icu_irq_set_irqchip_state() to handle software interrupt injection. Signed-off-by: Lad Prabhakar --- v4->v5: - Dropped gaurd from rzv2h_icu_swint_set_irqchip_state() as we just did a single writel v3->v4: - Made a seprate irq chip for SWINT v2->v3: - Replaced pr_debug with pr_info in the SWINT handler to ensure visibility of the message. v1->v2: - Made CA55 SW interrupt as part of ICU IRQ domain. - Implemented rzv2h_icu_irq_set_irqchip_state() to trigger SWINT. - Updated commit message accordingly. --- drivers/irqchip/irq-renesas-rzv2h.c | 95 ++++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 38d48632a5c2..a75ff3bb3846 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -29,7 +30,10 @@ #define ICU_TINT_START (ICU_IRQ_LAST + 1) #define ICU_TINT_COUNT 32 #define ICU_TINT_LAST (ICU_TINT_START + ICU_TINT_COUNT - 1) -#define ICU_NUM_IRQ (ICU_TINT_LAST + 1) +#define ICU_CA55_INT_START (ICU_TINT_LAST + 1) +#define ICU_CA55_INT_COUNT 4 +#define ICU_CA55_INT_LAST (ICU_CA55_INT_START + ICU_CA55_INT_COUNT - 1) +#define ICU_NUM_IRQ (ICU_CA55_INT_LAST + 1) =20 /* Registers */ #define ICU_NSCNT 0x00 @@ -42,6 +46,7 @@ #define ICU_TSCLR 0x24 #define ICU_TITSR(k) (0x28 + (k) * 4) #define ICU_TSSR(k) (0x30 + (k) * 4) +#define ICU_SWINT 0x130 #define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4) #define ICU_DMACKSELk(k) (0x500 + (k) * 4) =20 @@ -431,6 +436,27 @@ static int rzv2h_tint_set_type(struct irq_data *d, uns= igned int type) return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 +static int rzv2h_icu_swint_set_irqchip_state(struct irq_data *d, enum irqc= hip_irq_state which, + bool state) +{ + unsigned int hwirq =3D irqd_to_hwirq(d); + struct rzv2h_icu_priv *priv; + unsigned int bit; + + if (which !=3D IRQCHIP_STATE_PENDING) + return irq_chip_set_parent_state(d, which, state); + + if (!state) + return 0; + + priv =3D irq_data_to_priv(d); + bit =3D BIT(hwirq - ICU_CA55_INT_START); + + /* Trigger the software interrupt */ + writel_relaxed(bit, priv->base + ICU_SWINT); + return 0; +} + static int rzv2h_irqc_irq_suspend(void *data) { struct rzv2h_irqc_reg_cache *cache =3D &rzv2h_icu_data->cache; @@ -520,6 +546,23 @@ static const struct irq_chip rzv2h_icu_nmi_chip =3D { IRQCHIP_SKIP_SET_WAKE, }; =20 +static const struct irq_chip rzv2h_icu_swint_chip =3D { + .name =3D "rzv2h-icu", + .irq_eoi =3D irq_chip_eoi_parent, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D rzv2h_icu_swint_set_irqchip_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D irq_chip_set_type_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + static int rzv2h_icu_alloc(struct irq_domain *domain, unsigned int virq, u= nsigned int nr_irqs, void *arg) { @@ -549,6 +592,8 @@ static int rzv2h_icu_alloc(struct irq_domain *domain, u= nsigned int virq, unsigne chip =3D &rzv2h_icu_tint_chip; } else if (hwirq >=3D ICU_IRQ_START && hwirq <=3D ICU_IRQ_LAST) { chip =3D &rzv2h_icu_irq_chip; + } else if (hwirq >=3D ICU_CA55_INT_START && hwirq <=3D ICU_CA55_INT_LAST)= { + chip =3D &rzv2h_icu_swint_chip; } else { chip =3D &rzv2h_icu_nmi_chip; } @@ -586,6 +631,50 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu= _priv *priv, struct device return 0; } =20 +static irqreturn_t rzv2h_icu_swint_irq(int irq, void *data) +{ + u8 cpu =3D *(u8 *)data; + + pr_info("SWINT interrupt for CA55 core %u\n", cpu); + return IRQ_HANDLED; +} + +static int rzv2h_icu_setup_irqs(struct platform_device *pdev, struct irq_d= omain *irq_domain) +{ + bool irq_inject =3D IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION); + static const char * const rzv2h_swint_names[] =3D { + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + }; + static const u8 swint_idx[] =3D { 0, 1, 2, 3 }; + struct device *dev =3D &pdev->dev; + struct irq_fwspec fwspec; + unsigned int i, virq; + int ret; + + for (i =3D 0; i < ICU_CA55_INT_COUNT && irq_inject; i++) { + fwspec.fwnode =3D irq_domain->fwnode; + fwspec.param_count =3D 2; + fwspec.param[0] =3D ICU_CA55_INT_START + i; + fwspec.param[1] =3D IRQ_TYPE_EDGE_RISING; + + virq =3D irq_create_fwspec_mapping(&fwspec); + if (!virq) { + return dev_err_probe(dev, -EINVAL, "failed to create IRQ mapping for %s= \n", + rzv2h_swint_names[i]); + } + + ret =3D devm_request_irq(dev, virq, rzv2h_icu_swint_irq, 0, dev_name(dev= ), + (void *)&swint_idx[i]); + if (ret) { + return dev_err_probe(dev, ret, "Failed to request %s IRQ\n", + rzv2h_swint_names[i]); + } + } + + return 0; +} + static int rzv2h_icu_probe_common(struct platform_device *pdev, struct dev= ice_node *parent, const struct rzv2h_hw_info *hw_info) { @@ -640,6 +729,10 @@ static int rzv2h_icu_probe_common(struct platform_devi= ce *pdev, struct device_no =20 register_syscore(&rzv2h_irqc_syscore); =20 + ret =3D rzv2h_icu_setup_irqs(pdev, irq_domain); + if (ret) + goto pm_put; + /* * coccicheck complains about a missing put_device call before returning,= but it's a false * positive. We still need dev after successfully returning from this fun= ction. --=20 2.53.0