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Wed, 04 Mar 2026 03:33:22 -0800 (PST) Received: from iku.example.org ([2a06:5906:61b:2d00:bddd:d1ed:d1ee:a876]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439b03db76bsm27345379f8f.18.2026.03.04.03.33.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 03:33:21 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Geert Uytterhoeven , Philipp Zabel , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 5/7] irqchip/renesas-rzv2h: Replace single irq_chip with per-region irq_chip instances Date: Wed, 4 Mar 2026 11:33:15 +0000 Message-ID: <20260304113317.129339-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260304113317.129339-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260304113317.129339-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Replace the single rzv2h_icu_chip and its dispatcher callbacks with dedicated irq_chip instances for each interrupt region: NMI, IRQ, and TINT. Move the irqd_is_level_type() check ahead of the scoped_guard in rzv2h_icu_tint_eoi() and rzv2h_icu_irq_eoi() to avoid acquiring the spinlock unnecessarily for level-type interrupts. Drop the ICU_TINT_START guard from rzv2h_tint_irq_endisable() since it is now only reachable via the TINT chip path. Signed-off-by: Lad Prabhakar --- v4->v5: - Dropped scoped_guard arround single writel - Used scoped_guard in rzv2h_irq_set_type/rzv2h_tint_set_type to ensure irq_chip_set_type_parent() is called without locking v3->v4: - New patch. --- drivers/irqchip/irq-renesas-rzv2h.c | 174 +++++++++++++++++----------- 1 file changed, 104 insertions(+), 70 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index ce7d61b14ab6..38d48632a5c2 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -169,32 +169,47 @@ static inline struct rzv2h_icu_priv *irq_data_to_priv= (struct irq_data *data) return data->domain->host_data; } =20 -static void rzv2h_icu_eoi(struct irq_data *d) +static void rzv2h_icu_tint_eoi(struct irq_data *d) { struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); unsigned int tintirq_nr; u32 bit; =20 - scoped_guard(raw_spinlock, &priv->lock) { - if (hw_irq >=3D ICU_TINT_START) { - tintirq_nr =3D hw_irq - ICU_TINT_START; - bit =3D BIT(tintirq_nr); - if (!irqd_is_level_type(d)) - writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); - } else if (hw_irq >=3D ICU_IRQ_START) { - tintirq_nr =3D hw_irq - ICU_IRQ_START; - bit =3D BIT(tintirq_nr); - if (!irqd_is_level_type(d)) - writel_relaxed(bit, priv->base + ICU_ISCLR); - } else { - writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR); - } + if (!irqd_is_level_type(d)) { + tintirq_nr =3D hw_irq - ICU_TINT_START; + bit =3D BIT(tintirq_nr); + writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); + } + + irq_chip_eoi_parent(d); +} + +static void rzv2h_icu_irq_eoi(struct irq_data *d) +{ + struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); + unsigned int hw_irq =3D irqd_to_hwirq(d); + unsigned int tintirq_nr; + u32 bit; + + if (!irqd_is_level_type(d)) { + tintirq_nr =3D hw_irq - ICU_IRQ_START; + bit =3D BIT(tintirq_nr); + writel_relaxed(bit, priv->base + ICU_ISCLR); } =20 irq_chip_eoi_parent(d); } =20 +static void rzv2h_icu_nmi_eoi(struct irq_data *d) +{ + struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); + + writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR); + + irq_chip_eoi_parent(d); +} + static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) { struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); @@ -202,9 +217,6 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d= , bool enable) u32 tint_nr, tssel_n, k, tssr; u8 nr_tint; =20 - if (hw_irq < ICU_TINT_START) - return; - tint_nr =3D hw_irq - ICU_TINT_START; nr_tint =3D 32 / priv->info->field_width; k =3D tint_nr / nr_tint; @@ -227,13 +239,13 @@ static void rzv2h_tint_irq_endisable(struct irq_data = *d, bool enable) writel_relaxed(BIT(tint_nr), priv->base + priv->info->t_offs + ICU_TSCLR); } =20 -static void rzv2h_icu_irq_disable(struct irq_data *d) +static void rzv2h_icu_tint_disable(struct irq_data *d) { irq_chip_disable_parent(d); rzv2h_tint_irq_endisable(d, false); } =20 -static void rzv2h_icu_irq_enable(struct irq_data *d) +static void rzv2h_icu_tint_enable(struct irq_data *d) { rzv2h_tint_irq_endisable(d, true); irq_chip_enable_parent(d); @@ -259,7 +271,7 @@ static int rzv2h_nmi_set_type(struct irq_data *d, unsig= ned int type) =20 writel_relaxed(sense, priv->base + ICU_NITSR); =20 - return 0; + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 static void rzv2h_clear_irq_int(struct rzv2h_icu_priv *priv, unsigned int = hwirq) @@ -309,14 +321,15 @@ static int rzv2h_irq_set_type(struct irq_data *d, uns= igned int type) return -EINVAL; } =20 - guard(raw_spinlock)(&priv->lock); - iitsr =3D readl_relaxed(priv->base + ICU_IITSR); - iitsr &=3D ~ICU_IITSR_IITSEL_MASK(irq_nr); - iitsr |=3D ICU_IITSR_IITSEL_PREP(sense, irq_nr); - rzv2h_clear_irq_int(priv, hwirq); - writel_relaxed(iitsr, priv->base + ICU_IITSR); + scoped_guard(raw_spinlock, &priv->lock) { + iitsr =3D readl_relaxed(priv->base + ICU_IITSR); + iitsr &=3D ~ICU_IITSR_IITSEL_MASK(irq_nr); + iitsr |=3D ICU_IITSR_IITSEL_PREP(sense, irq_nr); + rzv2h_clear_irq_int(priv, hwirq); + writel_relaxed(iitsr, priv->base + ICU_IITSR); + } =20 - return 0; + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int= hwirq) @@ -391,48 +404,30 @@ static int rzv2h_tint_set_type(struct irq_data *d, un= signed int type) titsr_k =3D ICU_TITSR_K(tint_nr); titsel_n =3D ICU_TITSR_TITSEL_N(tint_nr); =20 - guard(raw_spinlock)(&priv->lock); - - tssr =3D readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)= ); - titsr =3D readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(titsr= _k)); - - tssr_cur =3D field_get(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_wid= th), tssr); - titsr_cur =3D field_get(ICU_TITSR_TITSEL_MASK(titsel_n), titsr); - if (tssr_cur =3D=3D tint && titsr_cur =3D=3D sense) - return 0; - - tssr &=3D ~(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_width) | tien); - tssr |=3D ICU_TSSR_TSSEL_PREP(tint, tssel_n, priv->info->field_width); - - writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); - - titsr &=3D ~ICU_TITSR_TITSEL_MASK(titsel_n); - titsr |=3D ICU_TITSR_TITSEL_PREP(sense, titsel_n); + scoped_guard(raw_spinlock, &priv->lock) { + tssr =3D readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k= )); + titsr =3D readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(tits= r_k)); =20 - writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_k= )); + tssr_cur =3D field_get(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_wi= dth), tssr); + titsr_cur =3D field_get(ICU_TITSR_TITSEL_MASK(titsel_n), titsr); + if (tssr_cur =3D=3D tint && titsr_cur =3D=3D sense) + goto set_parent_type; =20 - rzv2h_clear_tint_int(priv, hwirq); + tssr &=3D ~(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_width) | tien= ); + tssr |=3D ICU_TSSR_TSSEL_PREP(tint, tssel_n, priv->info->field_width); =20 - writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(ts= sr_k)); + writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); =20 - return 0; -} + titsr &=3D ~ICU_TITSR_TITSEL_MASK(titsel_n); + titsr |=3D ICU_TITSR_TITSEL_PREP(sense, titsel_n); =20 -static int rzv2h_icu_set_type(struct irq_data *d, unsigned int type) -{ - unsigned int hw_irq =3D irqd_to_hwirq(d); - int ret; - - if (hw_irq >=3D ICU_TINT_START) - ret =3D rzv2h_tint_set_type(d, type); - else if (hw_irq >=3D ICU_IRQ_START) - ret =3D rzv2h_irq_set_type(d, type); - else - ret =3D rzv2h_nmi_set_type(d, type); + writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_= k)); =20 - if (ret) - return ret; + rzv2h_clear_tint_int(priv, hwirq); =20 + writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(t= ssr_k)); + } +set_parent_type: return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 @@ -474,17 +469,51 @@ static struct syscore rzv2h_irqc_syscore =3D { .ops =3D &rzv2h_irqc_syscore_ops, }; =20 -static const struct irq_chip rzv2h_icu_chip =3D { +static const struct irq_chip rzv2h_icu_tint_chip =3D { + .name =3D "rzv2h-icu", + .irq_eoi =3D rzv2h_icu_tint_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D rzv2h_icu_tint_disable, + .irq_enable =3D rzv2h_icu_tint_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzv2h_tint_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static const struct irq_chip rzv2h_icu_irq_chip =3D { + .name =3D "rzv2h-icu", + .irq_eoi =3D rzv2h_icu_irq_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzv2h_irq_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static const struct irq_chip rzv2h_icu_nmi_chip =3D { .name =3D "rzv2h-icu", - .irq_eoi =3D rzv2h_icu_eoi, + .irq_eoi =3D rzv2h_icu_nmi_eoi, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, - .irq_disable =3D rzv2h_icu_irq_disable, - .irq_enable =3D rzv2h_icu_irq_enable, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzv2h_icu_set_type, + .irq_set_type =3D rzv2h_nmi_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | @@ -495,6 +524,7 @@ static int rzv2h_icu_alloc(struct irq_domain *domain, u= nsigned int virq, unsigne void *arg) { struct rzv2h_icu_priv *priv =3D domain->host_data; + const struct irq_chip *chip; unsigned long tint =3D 0; irq_hw_number_t hwirq; unsigned int type; @@ -516,13 +546,17 @@ static int rzv2h_icu_alloc(struct irq_domain *domain,= unsigned int virq, unsigne =20 if (hwirq < ICU_TINT_START || hwirq > ICU_TINT_LAST) return -EINVAL; + chip =3D &rzv2h_icu_tint_chip; + } else if (hwirq >=3D ICU_IRQ_START && hwirq <=3D ICU_IRQ_LAST) { + chip =3D &rzv2h_icu_irq_chip; + } else { + chip =3D &rzv2h_icu_nmi_chip; } =20 if (hwirq > (ICU_NUM_IRQ - 1)) return -EINVAL; =20 - ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzv2h_icu_chi= p, - (void *)(uintptr_t)tint); + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)= (uintptr_t)tint); if (ret) return ret; =20 --=20 2.53.0