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charset="utf-8" From: Lad Prabhakar Avoid dereferencing pdev->dev.of_node again in rzv2h_icu_probe_common(). Reuse the already available local node pointer when mapping the ICU register space. Signed-off-by: Lad Prabhakar --- v2->v5: - No change. --- drivers/irqchip/irq-renesas-rzv2h.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index da2bc43a0e12..20c0cd11ef25 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -570,7 +570,7 @@ static int rzv2h_icu_probe_common(struct platform_devic= e *pdev, struct device_no =20 platform_set_drvdata(pdev, rzv2h_icu_data); =20 - rzv2h_icu_data->base =3D devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, = NULL); + rzv2h_icu_data->base =3D devm_of_iomap(&pdev->dev, node, 0, NULL); if (IS_ERR(rzv2h_icu_data->base)) return PTR_ERR(rzv2h_icu_data->base); =20 --=20 2.53.0 From nobody Thu Apr 2 06:30:46 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3C2D34C816 for ; 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charset="utf-8" From: Lad Prabhakar Use a local struct device pointer in rzv2h_icu_probe_common() to avoid repeated dereferencing of pdev->dev. Signed-off-by: Lad Prabhakar --- v2->v5: - No change. --- drivers/irqchip/irq-renesas-rzv2h.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 20c0cd11ef25..766b981cf3d8 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -555,57 +555,58 @@ static int rzv2h_icu_probe_common(struct platform_dev= ice *pdev, struct device_no { struct irq_domain *irq_domain, *parent_domain; struct device_node *node =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; struct reset_control *resetn; int ret; =20 parent_domain =3D irq_find_host(parent); if (!parent_domain) { - dev_err(&pdev->dev, "cannot find parent domain\n"); + dev_err(dev, "cannot find parent domain\n"); return -ENODEV; } =20 - rzv2h_icu_data =3D devm_kzalloc(&pdev->dev, sizeof(*rzv2h_icu_data), GFP_= KERNEL); + rzv2h_icu_data =3D devm_kzalloc(dev, sizeof(*rzv2h_icu_data), GFP_KERNEL); if (!rzv2h_icu_data) return -ENOMEM; =20 platform_set_drvdata(pdev, rzv2h_icu_data); =20 - rzv2h_icu_data->base =3D devm_of_iomap(&pdev->dev, node, 0, NULL); + rzv2h_icu_data->base =3D devm_of_iomap(dev, node, 0, NULL); if (IS_ERR(rzv2h_icu_data->base)) return PTR_ERR(rzv2h_icu_data->base); =20 ret =3D rzv2h_icu_parse_interrupts(rzv2h_icu_data, node); if (ret) { - dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); + dev_err(dev, "cannot parse interrupts: %d\n", ret); return ret; } =20 - resetn =3D devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL); + resetn =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); if (IS_ERR(resetn)) { ret =3D PTR_ERR(resetn); - dev_err(&pdev->dev, "failed to acquire deasserted reset: %d\n", ret); + dev_err(dev, "failed to acquire deasserted reset: %d\n", ret); return ret; } =20 - ret =3D devm_pm_runtime_enable(&pdev->dev); + ret =3D devm_pm_runtime_enable(dev); if (ret < 0) { - dev_err(&pdev->dev, "devm_pm_runtime_enable failed, %d\n", ret); + dev_err(dev, "devm_pm_runtime_enable failed, %d\n", ret); return ret; } =20 - ret =3D pm_runtime_resume_and_get(&pdev->dev); + ret =3D pm_runtime_resume_and_get(dev); if (ret < 0) { - dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret); + dev_err(dev, "pm_runtime_resume_and_get failed: %d\n", ret); return ret; } =20 raw_spin_lock_init(&rzv2h_icu_data->lock); =20 irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, ICU_NUM_IRQ, - dev_fwnode(&pdev->dev), &rzv2h_icu_domain_ops, + dev_fwnode(dev), &rzv2h_icu_domain_ops, rzv2h_icu_data); if (!irq_domain) { - dev_err(&pdev->dev, "failed to add irq domain\n"); + dev_err(dev, "failed to add irq domain\n"); ret =3D -ENOMEM; goto pm_put; } @@ -616,12 +617,12 @@ static int rzv2h_icu_probe_common(struct platform_dev= ice *pdev, struct device_no =20 /* * coccicheck complains about a missing put_device call before returning,= but it's a false - * positive. We still need &pdev->dev after successfully returning from t= his function. + * positive. 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charset="utf-8" From: Lad Prabhakar Make use of dev_err_probe() to simplify rzv2h_icu_probe_common(). Keep dev_err() for -ENOMEM paths, as dev_err_probe() does not print for allocation failures, ensuring they remain visible in logs. Signed-off-by: Lad Prabhakar --- v2->v5: - No change. --- drivers/irqchip/irq-renesas-rzv2h.c | 31 ++++++++++------------------- 1 file changed, 10 insertions(+), 21 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 766b981cf3d8..444da7804f15 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -560,10 +560,8 @@ static int rzv2h_icu_probe_common(struct platform_devi= ce *pdev, struct device_no int ret; =20 parent_domain =3D irq_find_host(parent); - if (!parent_domain) { - dev_err(dev, "cannot find parent domain\n"); - return -ENODEV; - } + if (!parent_domain) + return dev_err_probe(dev, -ENODEV, "cannot find parent domain\n"); =20 rzv2h_icu_data =3D devm_kzalloc(dev, sizeof(*rzv2h_icu_data), GFP_KERNEL); if (!rzv2h_icu_data) @@ -576,29 +574,20 @@ static int rzv2h_icu_probe_common(struct platform_dev= ice *pdev, struct device_no return PTR_ERR(rzv2h_icu_data->base); =20 ret =3D rzv2h_icu_parse_interrupts(rzv2h_icu_data, node); - if (ret) { - dev_err(dev, "cannot parse interrupts: %d\n", ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "cannot parse interrupts\n"); =20 resetn =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); - if (IS_ERR(resetn)) { - ret =3D PTR_ERR(resetn); - dev_err(dev, "failed to acquire deasserted reset: %d\n", ret); - return ret; - } + if (IS_ERR(resetn)) + return dev_err_probe(dev, PTR_ERR(resetn), "failed to acquire deasserted= reset\n"); =20 ret =3D devm_pm_runtime_enable(dev); - if (ret < 0) { - dev_err(dev, "devm_pm_runtime_enable failed, %d\n", ret); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "devm_pm_runtime_enable failed\n"); =20 ret =3D pm_runtime_resume_and_get(dev); - if (ret < 0) { - dev_err(dev, "pm_runtime_resume_and_get failed: %d\n", ret); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "pm_runtime_resume_and_get failed\n"); =20 raw_spin_lock_init(&rzv2h_icu_data->lock); =20 --=20 2.53.0 From nobody Thu Apr 2 06:30:46 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5996C37EFE5 for ; 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charset="utf-8" From: Lad Prabhakar Introduce ICU_IRQ_LAST and ICU_TINT_LAST macros to make range boundaries explicit and reduce the chance of off-by-one errors. Extract the TINT information up front in rzv2h_icu_alloc() and validate the resulting hardware IRQ against the full TINT range [ICU_TINT_START, ICU_TINT_LAST]. Signed-off-by: Lad Prabhakar --- v4->v5: - No change. v3->v4: - New patch. --- drivers/irqchip/irq-renesas-rzv2h.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 444da7804f15..ce7d61b14ab6 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -25,9 +25,11 @@ /* DT "interrupts" indexes */ #define ICU_IRQ_START 1 #define ICU_IRQ_COUNT 16 -#define ICU_TINT_START (ICU_IRQ_START + ICU_IRQ_COUNT) +#define ICU_IRQ_LAST (ICU_IRQ_START + ICU_IRQ_COUNT - 1) +#define ICU_TINT_START (ICU_IRQ_LAST + 1) #define ICU_TINT_COUNT 32 -#define ICU_NUM_IRQ (ICU_TINT_START + ICU_TINT_COUNT) +#define ICU_TINT_LAST (ICU_TINT_START + ICU_TINT_COUNT - 1) +#define ICU_NUM_IRQ (ICU_TINT_LAST + 1) =20 /* Registers */ #define ICU_NSCNT 0x00 @@ -508,11 +510,11 @@ static int rzv2h_icu_alloc(struct irq_domain *domain,= unsigned int virq, unsigne * hwirq is embedded in bits 0-15. * TINT is embedded in bits 16-31. */ - if (hwirq >=3D ICU_TINT_START) { - tint =3D ICU_TINT_EXTRACT_GPIOINT(hwirq); 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charset="utf-8" From: Lad Prabhakar Replace the single rzv2h_icu_chip and its dispatcher callbacks with dedicated irq_chip instances for each interrupt region: NMI, IRQ, and TINT. Move the irqd_is_level_type() check ahead of the scoped_guard in rzv2h_icu_tint_eoi() and rzv2h_icu_irq_eoi() to avoid acquiring the spinlock unnecessarily for level-type interrupts. Drop the ICU_TINT_START guard from rzv2h_tint_irq_endisable() since it is now only reachable via the TINT chip path. Signed-off-by: Lad Prabhakar --- v4->v5: - Dropped scoped_guard arround single writel - Used scoped_guard in rzv2h_irq_set_type/rzv2h_tint_set_type to ensure irq_chip_set_type_parent() is called without locking v3->v4: - New patch. --- drivers/irqchip/irq-renesas-rzv2h.c | 174 +++++++++++++++++----------- 1 file changed, 104 insertions(+), 70 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index ce7d61b14ab6..38d48632a5c2 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -169,32 +169,47 @@ static inline struct rzv2h_icu_priv *irq_data_to_priv= (struct irq_data *data) return data->domain->host_data; } =20 -static void rzv2h_icu_eoi(struct irq_data *d) +static void rzv2h_icu_tint_eoi(struct irq_data *d) { struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); unsigned int tintirq_nr; u32 bit; =20 - scoped_guard(raw_spinlock, &priv->lock) { - if (hw_irq >=3D ICU_TINT_START) { - tintirq_nr =3D hw_irq - ICU_TINT_START; - bit =3D BIT(tintirq_nr); - if (!irqd_is_level_type(d)) - writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); - } else if (hw_irq >=3D ICU_IRQ_START) { - tintirq_nr =3D hw_irq - ICU_IRQ_START; - bit =3D BIT(tintirq_nr); - if (!irqd_is_level_type(d)) - writel_relaxed(bit, priv->base + ICU_ISCLR); - } else { - writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR); - } + if (!irqd_is_level_type(d)) { + tintirq_nr =3D hw_irq - ICU_TINT_START; + bit =3D BIT(tintirq_nr); + writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); + } + + irq_chip_eoi_parent(d); +} + +static void rzv2h_icu_irq_eoi(struct irq_data *d) +{ + struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); + unsigned int hw_irq =3D irqd_to_hwirq(d); + unsigned int tintirq_nr; + u32 bit; + + if (!irqd_is_level_type(d)) { + tintirq_nr =3D hw_irq - ICU_IRQ_START; + bit =3D BIT(tintirq_nr); + writel_relaxed(bit, priv->base + ICU_ISCLR); } =20 irq_chip_eoi_parent(d); } =20 +static void rzv2h_icu_nmi_eoi(struct irq_data *d) +{ + struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); + + writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR); + + irq_chip_eoi_parent(d); +} + static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) { struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); @@ -202,9 +217,6 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d= , bool enable) u32 tint_nr, tssel_n, k, tssr; u8 nr_tint; =20 - if (hw_irq < ICU_TINT_START) - return; - tint_nr =3D hw_irq - ICU_TINT_START; nr_tint =3D 32 / priv->info->field_width; k =3D tint_nr / nr_tint; @@ -227,13 +239,13 @@ static void rzv2h_tint_irq_endisable(struct irq_data = *d, bool enable) writel_relaxed(BIT(tint_nr), priv->base + priv->info->t_offs + ICU_TSCLR); } =20 -static void rzv2h_icu_irq_disable(struct irq_data *d) +static void rzv2h_icu_tint_disable(struct irq_data *d) { irq_chip_disable_parent(d); rzv2h_tint_irq_endisable(d, false); } =20 -static void rzv2h_icu_irq_enable(struct irq_data *d) +static void rzv2h_icu_tint_enable(struct irq_data *d) { rzv2h_tint_irq_endisable(d, true); irq_chip_enable_parent(d); @@ -259,7 +271,7 @@ static int rzv2h_nmi_set_type(struct irq_data *d, unsig= ned int type) =20 writel_relaxed(sense, priv->base + ICU_NITSR); =20 - return 0; + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 static void rzv2h_clear_irq_int(struct rzv2h_icu_priv *priv, unsigned int = hwirq) @@ -309,14 +321,15 @@ static int rzv2h_irq_set_type(struct irq_data *d, uns= igned int type) return -EINVAL; } =20 - guard(raw_spinlock)(&priv->lock); - iitsr =3D readl_relaxed(priv->base + ICU_IITSR); - iitsr &=3D ~ICU_IITSR_IITSEL_MASK(irq_nr); - iitsr |=3D ICU_IITSR_IITSEL_PREP(sense, irq_nr); - rzv2h_clear_irq_int(priv, hwirq); - writel_relaxed(iitsr, priv->base + ICU_IITSR); + scoped_guard(raw_spinlock, &priv->lock) { + iitsr =3D readl_relaxed(priv->base + ICU_IITSR); + iitsr &=3D ~ICU_IITSR_IITSEL_MASK(irq_nr); + iitsr |=3D ICU_IITSR_IITSEL_PREP(sense, irq_nr); + rzv2h_clear_irq_int(priv, hwirq); + writel_relaxed(iitsr, priv->base + ICU_IITSR); + } =20 - return 0; + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int= hwirq) @@ -391,48 +404,30 @@ static int rzv2h_tint_set_type(struct irq_data *d, un= signed int type) titsr_k =3D ICU_TITSR_K(tint_nr); titsel_n =3D ICU_TITSR_TITSEL_N(tint_nr); =20 - guard(raw_spinlock)(&priv->lock); - - tssr =3D readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)= ); - titsr =3D readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(titsr= _k)); - - tssr_cur =3D field_get(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_wid= th), tssr); - titsr_cur =3D field_get(ICU_TITSR_TITSEL_MASK(titsel_n), titsr); - if (tssr_cur =3D=3D tint && titsr_cur =3D=3D sense) - return 0; - - tssr &=3D ~(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_width) | tien); - tssr |=3D ICU_TSSR_TSSEL_PREP(tint, tssel_n, priv->info->field_width); - - writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); - - titsr &=3D ~ICU_TITSR_TITSEL_MASK(titsel_n); - titsr |=3D ICU_TITSR_TITSEL_PREP(sense, titsel_n); + scoped_guard(raw_spinlock, &priv->lock) { + tssr =3D readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k= )); + titsr =3D readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(tits= r_k)); =20 - writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_k= )); + tssr_cur =3D field_get(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_wi= dth), tssr); + titsr_cur =3D field_get(ICU_TITSR_TITSEL_MASK(titsel_n), titsr); + if (tssr_cur =3D=3D tint && titsr_cur =3D=3D sense) + goto set_parent_type; =20 - rzv2h_clear_tint_int(priv, hwirq); + tssr &=3D ~(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_width) | tien= ); + tssr |=3D ICU_TSSR_TSSEL_PREP(tint, tssel_n, priv->info->field_width); =20 - writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(ts= sr_k)); + writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); =20 - return 0; -} + titsr &=3D ~ICU_TITSR_TITSEL_MASK(titsel_n); + titsr |=3D ICU_TITSR_TITSEL_PREP(sense, titsel_n); =20 -static int rzv2h_icu_set_type(struct irq_data *d, unsigned int type) -{ - unsigned int hw_irq =3D irqd_to_hwirq(d); - int ret; - - if (hw_irq >=3D ICU_TINT_START) - ret =3D rzv2h_tint_set_type(d, type); - else if (hw_irq >=3D ICU_IRQ_START) - ret =3D rzv2h_irq_set_type(d, type); - else - ret =3D rzv2h_nmi_set_type(d, type); + writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_= k)); =20 - if (ret) - return ret; + rzv2h_clear_tint_int(priv, hwirq); =20 + writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(t= ssr_k)); + } +set_parent_type: return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 @@ -474,17 +469,51 @@ static struct syscore rzv2h_irqc_syscore =3D { .ops =3D &rzv2h_irqc_syscore_ops, }; =20 -static const struct irq_chip rzv2h_icu_chip =3D { +static const struct irq_chip rzv2h_icu_tint_chip =3D { + .name =3D "rzv2h-icu", + .irq_eoi =3D rzv2h_icu_tint_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D rzv2h_icu_tint_disable, + .irq_enable =3D rzv2h_icu_tint_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzv2h_tint_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static const struct irq_chip rzv2h_icu_irq_chip =3D { + .name =3D "rzv2h-icu", + .irq_eoi =3D rzv2h_icu_irq_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzv2h_irq_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static const struct irq_chip rzv2h_icu_nmi_chip =3D { .name =3D "rzv2h-icu", - .irq_eoi =3D rzv2h_icu_eoi, + .irq_eoi =3D rzv2h_icu_nmi_eoi, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, - .irq_disable =3D rzv2h_icu_irq_disable, - .irq_enable =3D rzv2h_icu_irq_enable, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzv2h_icu_set_type, + .irq_set_type =3D rzv2h_nmi_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | @@ -495,6 +524,7 @@ static int rzv2h_icu_alloc(struct irq_domain *domain, u= nsigned int virq, unsigne void *arg) { struct rzv2h_icu_priv *priv =3D domain->host_data; + const struct irq_chip *chip; unsigned long tint =3D 0; irq_hw_number_t hwirq; unsigned int type; @@ -516,13 +546,17 @@ static int rzv2h_icu_alloc(struct irq_domain *domain,= unsigned int virq, unsigne =20 if (hwirq < ICU_TINT_START || hwirq > ICU_TINT_LAST) return -EINVAL; + chip =3D &rzv2h_icu_tint_chip; + } else if (hwirq >=3D ICU_IRQ_START && hwirq <=3D ICU_IRQ_LAST) { + chip =3D &rzv2h_icu_irq_chip; + } else { + chip =3D &rzv2h_icu_nmi_chip; } =20 if (hwirq > (ICU_NUM_IRQ - 1)) return -EINVAL; =20 - ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzv2h_icu_chi= p, - (void *)(uintptr_t)tint); + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)= (uintptr_t)tint); if (ret) return ret; =20 --=20 2.53.0 From nobody Thu Apr 2 06:30:46 2026 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1AF3392800 for ; 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Wed, 04 Mar 2026 03:33:22 -0800 (PST) Received: from iku.example.org ([2a06:5906:61b:2d00:bddd:d1ed:d1ee:a876]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439b03db76bsm27345379f8f.18.2026.03.04.03.33.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 03:33:22 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Geert Uytterhoeven , Philipp Zabel , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 6/7] irqchip/renesas-rzv2h: Add CA55 software interrupt support Date: Wed, 4 Mar 2026 11:33:16 +0000 Message-ID: <20260304113317.129339-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260304113317.129339-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260304113317.129339-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The RZ/V2H ICU exposes four software-triggerable interrupts targeting the CA55 cores (int-ca55-0 to int-ca55-3). Add support for these interrupts to enable IRQ injection via the generic IRQ injection framework. Add a dedicated rzv2h_icu_swint_chip irq_chip for the CA55 region and implement rzv2h_icu_irq_set_irqchip_state() to handle software interrupt injection. Signed-off-by: Lad Prabhakar --- v4->v5: - Dropped gaurd from rzv2h_icu_swint_set_irqchip_state() as we just did a single writel v3->v4: - Made a seprate irq chip for SWINT v2->v3: - Replaced pr_debug with pr_info in the SWINT handler to ensure visibility of the message. v1->v2: - Made CA55 SW interrupt as part of ICU IRQ domain. - Implemented rzv2h_icu_irq_set_irqchip_state() to trigger SWINT. - Updated commit message accordingly. --- drivers/irqchip/irq-renesas-rzv2h.c | 95 ++++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 38d48632a5c2..a75ff3bb3846 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -29,7 +30,10 @@ #define ICU_TINT_START (ICU_IRQ_LAST + 1) #define ICU_TINT_COUNT 32 #define ICU_TINT_LAST (ICU_TINT_START + ICU_TINT_COUNT - 1) -#define ICU_NUM_IRQ (ICU_TINT_LAST + 1) +#define ICU_CA55_INT_START (ICU_TINT_LAST + 1) +#define ICU_CA55_INT_COUNT 4 +#define ICU_CA55_INT_LAST (ICU_CA55_INT_START + ICU_CA55_INT_COUNT - 1) +#define ICU_NUM_IRQ (ICU_CA55_INT_LAST + 1) =20 /* Registers */ #define ICU_NSCNT 0x00 @@ -42,6 +46,7 @@ #define ICU_TSCLR 0x24 #define ICU_TITSR(k) (0x28 + (k) * 4) #define ICU_TSSR(k) (0x30 + (k) * 4) +#define ICU_SWINT 0x130 #define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4) #define ICU_DMACKSELk(k) (0x500 + (k) * 4) =20 @@ -431,6 +436,27 @@ static int rzv2h_tint_set_type(struct irq_data *d, uns= igned int type) return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 +static int rzv2h_icu_swint_set_irqchip_state(struct irq_data *d, enum irqc= hip_irq_state which, + bool state) +{ + unsigned int hwirq =3D irqd_to_hwirq(d); + struct rzv2h_icu_priv *priv; + unsigned int bit; + + if (which !=3D IRQCHIP_STATE_PENDING) + return irq_chip_set_parent_state(d, which, state); + + if (!state) + return 0; + + priv =3D irq_data_to_priv(d); + bit =3D BIT(hwirq - ICU_CA55_INT_START); + + /* Trigger the software interrupt */ + writel_relaxed(bit, priv->base + ICU_SWINT); + return 0; +} + static int rzv2h_irqc_irq_suspend(void *data) { struct rzv2h_irqc_reg_cache *cache =3D &rzv2h_icu_data->cache; @@ -520,6 +546,23 @@ static const struct irq_chip rzv2h_icu_nmi_chip =3D { IRQCHIP_SKIP_SET_WAKE, }; =20 +static const struct irq_chip rzv2h_icu_swint_chip =3D { + .name =3D "rzv2h-icu", + .irq_eoi =3D irq_chip_eoi_parent, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D rzv2h_icu_swint_set_irqchip_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D irq_chip_set_type_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + static int rzv2h_icu_alloc(struct irq_domain *domain, unsigned int virq, u= nsigned int nr_irqs, void *arg) { @@ -549,6 +592,8 @@ static int rzv2h_icu_alloc(struct irq_domain *domain, u= nsigned int virq, unsigne chip =3D &rzv2h_icu_tint_chip; } else if (hwirq >=3D ICU_IRQ_START && hwirq <=3D ICU_IRQ_LAST) { chip =3D &rzv2h_icu_irq_chip; + } else if (hwirq >=3D ICU_CA55_INT_START && hwirq <=3D ICU_CA55_INT_LAST)= { + chip =3D &rzv2h_icu_swint_chip; } else { chip =3D &rzv2h_icu_nmi_chip; } @@ -586,6 +631,50 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu= _priv *priv, struct device return 0; } =20 +static irqreturn_t rzv2h_icu_swint_irq(int irq, void *data) +{ + u8 cpu =3D *(u8 *)data; + + pr_info("SWINT interrupt for CA55 core %u\n", cpu); + return IRQ_HANDLED; +} + +static int rzv2h_icu_setup_irqs(struct platform_device *pdev, struct irq_d= omain *irq_domain) +{ + bool irq_inject =3D IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION); + static const char * const rzv2h_swint_names[] =3D { + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + }; + static const u8 swint_idx[] =3D { 0, 1, 2, 3 }; + struct device *dev =3D &pdev->dev; + struct irq_fwspec fwspec; + unsigned int i, virq; + int ret; + + for (i =3D 0; i < ICU_CA55_INT_COUNT && irq_inject; i++) { + fwspec.fwnode =3D irq_domain->fwnode; + fwspec.param_count =3D 2; + fwspec.param[0] =3D ICU_CA55_INT_START + i; + fwspec.param[1] =3D IRQ_TYPE_EDGE_RISING; + + virq =3D irq_create_fwspec_mapping(&fwspec); + if (!virq) { + return dev_err_probe(dev, -EINVAL, "failed to create IRQ mapping for %s= \n", + rzv2h_swint_names[i]); + } + + ret =3D devm_request_irq(dev, virq, rzv2h_icu_swint_irq, 0, dev_name(dev= ), + (void *)&swint_idx[i]); + if (ret) { + return dev_err_probe(dev, ret, "Failed to request %s IRQ\n", + rzv2h_swint_names[i]); + } + } + + return 0; +} + static int rzv2h_icu_probe_common(struct platform_device *pdev, struct dev= ice_node *parent, const struct rzv2h_hw_info *hw_info) { @@ -640,6 +729,10 @@ static int rzv2h_icu_probe_common(struct platform_devi= ce *pdev, struct device_no =20 register_syscore(&rzv2h_irqc_syscore); =20 + ret =3D rzv2h_icu_setup_irqs(pdev, irq_domain); + if (ret) + goto pm_put; + /* * coccicheck complains about a missing put_device call before returning,= but it's a false * positive. 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Wed, 04 Mar 2026 03:33:23 -0800 (PST) Received: from iku.example.org ([2a06:5906:61b:2d00:bddd:d1ed:d1ee:a876]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439b03db76bsm27345379f8f.18.2026.03.04.03.33.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 03:33:23 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Geert Uytterhoeven , Philipp Zabel , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v5 7/7] irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger Date: Wed, 4 Mar 2026 11:33:17 +0000 Message-ID: <20260304113317.129339-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260304113317.129339-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260304113317.129339-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Handle the RZ/V2H ICU error interrupt to help diagnose latched bus, ECC RAM, and CA55/IP error conditions. Support error injection via ICU_SWPE to allow testing the pseudo error error interrupts. Account for SoC differences in ECC RAM error register coverage so the handler only iterates over valid ECC status/clear banks, and route the RZ/V2N compatible to a probe path with the correct ECC range while keeping the existing RZ/V2H and RZ/G3E handling. Signed-off-by: Lad Prabhakar --- v4->v5: - Dropped gaurd from rzv2h_icu_swpe_set_irqchip_state() as we just did a single writel v3->v4: - Made a seprate irq chip for SWPE v2->v3: - Updated pr_debug to pr_info in the error IRQ handler to ensure visibility of the messages. v1->v2: - Made Error interrupt as part of ICU IRQ domain. - Updated rzv2h_icu_irq_set_irqchip_state() to trigger pseudo interrupt. - Updated commit message accordingly. --- drivers/irqchip/irq-renesas-rzv2h.c | 163 +++++++++++++++++++++++++++- 1 file changed, 161 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index a75ff3bb3846..c3a395637a46 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -33,7 +33,10 @@ #define ICU_CA55_INT_START (ICU_TINT_LAST + 1) #define ICU_CA55_INT_COUNT 4 #define ICU_CA55_INT_LAST (ICU_CA55_INT_START + ICU_CA55_INT_COUNT - 1) -#define ICU_NUM_IRQ (ICU_CA55_INT_LAST + 1) +#define ICU_ERR_INT_START (ICU_CA55_INT_LAST + 1) +#define ICU_ERR_INT_COUNT 1 +#define ICU_ERR_INT_LAST (ICU_ERR_INT_START + ICU_ERR_INT_COUNT - 1) +#define ICU_NUM_IRQ (ICU_ERR_INT_LAST + 1) =20 /* Registers */ #define ICU_NSCNT 0x00 @@ -46,7 +49,15 @@ #define ICU_TSCLR 0x24 #define ICU_TITSR(k) (0x28 + (k) * 4) #define ICU_TSSR(k) (0x30 + (k) * 4) +#define ICU_BEISR(k) (0x70 + (k) * 4) +#define ICU_BECLR(k) (0x80 + (k) * 4) +#define ICU_EREISR(k) (0x90 + (k) * 4) +#define ICU_ERCLR(k) (0xE0 + (k) * 4) #define ICU_SWINT 0x130 +#define ICU_ERINTA55CTL(k) (0x338 + (k) * 4) +#define ICU_ERINTA55CRL(k) (0x348 + (k) * 4) +#define ICU_ERINTA55MSK(k) (0x358 + (k) * 4) +#define ICU_SWPE 0x370 #define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4) #define ICU_DMACKSELk(k) (0x500 + (k) * 4) =20 @@ -97,6 +108,10 @@ #define ICU_RZG3E_TSSEL_MAX_VAL 0x8c #define ICU_RZV2H_TSSEL_MAX_VAL 0x55 =20 +#define ICU_SWPE_NUM 16 +#define ICU_NUM_BE 4 +#define ICU_NUM_A55ERR 4 + /** * struct rzv2h_irqc_reg_cache - registers cache (necessary for suspend/re= sume) * @nitsr: ICU_NITSR register @@ -115,12 +130,16 @@ struct rzv2h_irqc_reg_cache { * @t_offs: TINT offset * @max_tssel: TSSEL max value * @field_width: TSSR field width + * @ecc_start: Start index of ECC RAM interrupts + * @ecc_end: End index of ECC RAM interrupts */ struct rzv2h_hw_info { const u8 *tssel_lut; u16 t_offs; u8 max_tssel; u8 field_width; + u8 ecc_start; + u8 ecc_end; }; =20 /* DMAC */ @@ -454,6 +473,36 @@ static int rzv2h_icu_swint_set_irqchip_state(struct ir= q_data *d, enum irqchip_ir =20 /* Trigger the software interrupt */ writel_relaxed(bit, priv->base + ICU_SWINT); + + return 0; +} + +static int rzv2h_icu_swpe_set_irqchip_state(struct irq_data *d, enum irqch= ip_irq_state which, + bool state) +{ + struct rzv2h_icu_priv *priv; + unsigned int bit; + static u8 swpe; + + if (which !=3D IRQCHIP_STATE_PENDING) + return irq_chip_set_parent_state(d, which, state); + + if (!state) + return 0; + + priv =3D irq_data_to_priv(d); + + bit =3D BIT(swpe); + /* + * SWPE has 16 bits; the bit position is rotated on each trigger + * and wraps around once all bits have been used. + */ + if (++swpe >=3D ICU_SWPE_NUM) + swpe =3D 0; + + /* Trigger the pseudo error interrupt */ + writel_relaxed(bit, priv->base + ICU_SWPE); + return 0; } =20 @@ -563,6 +612,23 @@ static const struct irq_chip rzv2h_icu_swint_chip =3D { IRQCHIP_SKIP_SET_WAKE, }; =20 +static const struct irq_chip rzv2h_icu_swpe_err_chip =3D { + .name =3D "rzv2h-icu", + .irq_eoi =3D irq_chip_eoi_parent, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D rzv2h_icu_swpe_set_irqchip_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D irq_chip_set_type_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + static int rzv2h_icu_alloc(struct irq_domain *domain, unsigned int virq, u= nsigned int nr_irqs, void *arg) { @@ -594,6 +660,8 @@ static int rzv2h_icu_alloc(struct irq_domain *domain, u= nsigned int virq, unsigne chip =3D &rzv2h_icu_irq_chip; } else if (hwirq >=3D ICU_CA55_INT_START && hwirq <=3D ICU_CA55_INT_LAST)= { chip =3D &rzv2h_icu_swint_chip; + } else if (hwirq >=3D ICU_ERR_INT_START && hwirq <=3D ICU_ERR_INT_LAST) { + chip =3D &rzv2h_icu_swpe_err_chip; } else { chip =3D &rzv2h_icu_nmi_chip; } @@ -631,6 +699,48 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu= _priv *priv, struct device return 0; } =20 +static irqreturn_t rzv2h_icu_error_irq(int irq, void *data) +{ + struct rzv2h_icu_priv *priv =3D data; + const struct rzv2h_hw_info *hw_info =3D priv->info; + void __iomem *base =3D priv->base; + unsigned int k; + u32 st; + + /* 1) Bus errors (BEISR0..3) */ + for (k =3D 0; k < ICU_NUM_BE; k++) { + st =3D readl(base + ICU_BEISR(k)); + if (!st) + continue; + + writel_relaxed(st, base + ICU_BECLR(k)); + pr_info("rzv2h-icu: BUS error k=3D%u status=3D0x%08x\n", k, st); + } + + /* 2) ECC RAM errors (EREISR0..X) */ + for (k =3D hw_info->ecc_start; k <=3D hw_info->ecc_end; k++) { + st =3D readl(base + ICU_EREISR(k)); + if (!st) + continue; + + writel_relaxed(st, base + ICU_ERCLR(k)); + pr_info("rzv2h-icu: ECC error k=3D%u status=3D0x%08x\n", k, st); + } + + /* 3) IP/CA55 error interrupt status (ERINTA55CTL0..3) */ + for (k =3D 0; k < ICU_NUM_A55ERR; k++) { + st =3D readl(base + ICU_ERINTA55CTL(k)); + if (!st) + continue; + + /* there is no relation with status bits so clear all the interrupts */ + writel_relaxed(0xffffffff, base + ICU_ERINTA55CRL(k)); + pr_info("rzv2h-icu: IP/CA55 error k=3D%u status=3D0x%08x\n", k, st); + } + + return IRQ_HANDLED; +} + static irqreturn_t rzv2h_icu_swint_irq(int irq, void *data) { u8 cpu =3D *(u8 *)data; @@ -641,12 +751,15 @@ static irqreturn_t rzv2h_icu_swint_irq(int irq, void = *data) =20 static int rzv2h_icu_setup_irqs(struct platform_device *pdev, struct irq_d= omain *irq_domain) { + const struct rzv2h_hw_info *hw_info =3D rzv2h_icu_data->info; bool irq_inject =3D IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION); static const char * const rzv2h_swint_names[] =3D { "int-ca55-0", "int-ca55-1", "int-ca55-2", "int-ca55-3", }; + static const char *icu_err =3D "icu-error-ca55"; static const u8 swint_idx[] =3D { 0, 1, 2, 3 }; + void __iomem *base =3D rzv2h_icu_data->base; struct device *dev =3D &pdev->dev; struct irq_fwspec fwspec; unsigned int i, virq; @@ -672,6 +785,35 @@ static int rzv2h_icu_setup_irqs(struct platform_device= *pdev, struct irq_domain } } =20 + /* Unmask and clear all IP/CA55 error interrupts */ + for (i =3D 0; i < ICU_NUM_A55ERR; i++) { + writel_relaxed(0xffffff, base + ICU_ERINTA55CRL(i)); + writel_relaxed(0x0, base + ICU_ERINTA55MSK(i)); + } + + /* Clear all Bus errors */ + for (i =3D 0; i < ICU_NUM_BE; i++) + writel_relaxed(0xffffffff, base + ICU_BECLR(i)); + + /* Clear all ECCRAM errors */ + for (i =3D hw_info->ecc_start; i <=3D hw_info->ecc_end; i++) + writel_relaxed(0xffffffff, base + ICU_ERCLR(i)); + + fwspec.fwnode =3D irq_domain->fwnode; + fwspec.param_count =3D 2; + fwspec.param[0] =3D ICU_ERR_INT_START; + fwspec.param[1] =3D IRQ_TYPE_LEVEL_HIGH; + + virq =3D irq_create_fwspec_mapping(&fwspec); + if (!virq) { + return dev_err_probe(dev, -EINVAL, "failed to create IRQ mapping for %s\= n", + icu_err); + } + + ret =3D devm_request_irq(dev, virq, rzv2h_icu_error_irq, 0, dev_name(dev)= , rzv2h_icu_data); + if (ret) + return dev_err_probe(dev, ret, "Failed to request %s IRQ\n", icu_err); + return 0; } =20 @@ -776,12 +918,24 @@ static const struct rzv2h_hw_info rzg3e_hw_params =3D= { .t_offs =3D ICU_RZG3E_TINT_OFFSET, .max_tssel =3D ICU_RZG3E_TSSEL_MAX_VAL, .field_width =3D 16, + .ecc_start =3D 1, + .ecc_end =3D 4, +}; + +static const struct rzv2h_hw_info rzv2n_hw_params =3D { + .t_offs =3D 0, + .max_tssel =3D ICU_RZV2H_TSSEL_MAX_VAL, + .field_width =3D 8, + .ecc_start =3D 0, + .ecc_end =3D 2, }; =20 static const struct rzv2h_hw_info rzv2h_hw_params =3D { .t_offs =3D 0, .max_tssel =3D ICU_RZV2H_TSSEL_MAX_VAL, .field_width =3D 8, + .ecc_start =3D 0, + .ecc_end =3D 11, }; =20 static int rzg3e_icu_probe(struct platform_device *pdev, struct device_nod= e *parent) @@ -789,6 +943,11 @@ static int rzg3e_icu_probe(struct platform_device *pde= v, struct device_node *par return rzv2h_icu_probe_common(pdev, parent, &rzg3e_hw_params); } =20 +static int rzv2n_icu_probe(struct platform_device *pdev, struct device_nod= e *parent) +{ + return rzv2h_icu_probe_common(pdev, parent, &rzv2n_hw_params); +} + static int rzv2h_icu_probe(struct platform_device *pdev, struct device_nod= e *parent) { return rzv2h_icu_probe_common(pdev, parent, &rzv2h_hw_params); @@ -796,7 +955,7 @@ static int rzv2h_icu_probe(struct platform_device *pdev= , struct device_node *par =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu) IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_probe) -IRQCHIP_MATCH("renesas,r9a09g056-icu", rzv2h_icu_probe) +IRQCHIP_MATCH("renesas,r9a09g056-icu", rzv2n_icu_probe) IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_probe) IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu) MODULE_AUTHOR("Fabrizio Castro "); --=20 2.53.0