From nobody Wed Apr 15 16:43:14 2026 Received: from canpmsgout09.his.huawei.com (canpmsgout09.his.huawei.com [113.46.200.224]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5603C16DC28; Wed, 4 Mar 2026 04:03:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.224 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772597021; cv=none; b=IqCldKQo7zjNjI5tV2D1B6x6MZw1O6yJhN9LOI62zWft72KvtPBSWlDEjw05BlsCVWugRTA4/NC+UnkeakIpeuIw0WjxtXY6FuzSeQGm3UcOWAMg9oN55F5g1IaXBI4T+5I5AKwImQjK0QLOfKMaXgEXrSrH6dqLknmfQa+j9dg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772597021; c=relaxed/simple; bh=Iy1gzv8iu8sEalneLbR6M5vpvEpvRKihFwTnlkgYNkE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aCeWjwYb3RiN1EV6CHDg5cJDZVNJ42oQWrDMEAd9oWxLhirCCQCbfEs2pZTO43pSXmiPMUCkKwLLEapXiDKZuzSyoYnAzxIuu/OMleFGzQR/Y6pgomLd/MaVsHxoOgntujisk8stMdeL6dNlRScXyMfbhYFSEZDFHJ6KfQ63l+I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=uG6ROz7c; arc=none smtp.client-ip=113.46.200.224 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="uG6ROz7c" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=jfNz3GxGoDicW62LZuiyKNWvvB4I0Mdzip6nEjCed84=; b=uG6ROz7cG1SynSOcfxqOG9HUk2PTlsNNoxEW7RwuCF0Rk3Ry0gZI7HyadMMq6O35RceCou0V0 GftDMr0ZwkWuOJW7isoWqHn0/I1I2Qoc1Gtu0+6OpQsKT2oxtGYbBBMA9lGROXuPs+/DmjVCKV5 L7N/1ujn1Zue5106n5FY5yY= Received: from mail.maildlp.com (unknown [172.19.162.92]) by canpmsgout09.his.huawei.com (SkyGuard) with ESMTPS id 4fQf6Y3NDhz1cyPw; Wed, 4 Mar 2026 11:58:45 +0800 (CST) Received: from kwepemk500005.china.huawei.com (unknown [7.202.194.90]) by mail.maildlp.com (Postfix) with ESMTPS id 3380D40562; Wed, 4 Mar 2026 12:03:36 +0800 (CST) Received: from huawei.com (10.50.163.32) by kwepemk500005.china.huawei.com (7.202.194.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 4 Mar 2026 12:03:35 +0800 From: Yifan Wu To: , , , , , , , , , , , , , , CC: , , , , , Subject: [RFC patch 1/9] selftests/resctrl: Move CPU affinity and resctrl FS setup to child process Date: Wed, 4 Mar 2026 12:03:26 +0800 Message-ID: <20260304040334.765860-2-wuyifan50@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260304040334.765860-1-wuyifan50@huawei.com> References: <20260304040334.765860-1-wuyifan50@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To kwepemk500005.china.huawei.com (7.202.194.90) Content-Type: text/plain; charset="utf-8" Currently, the resctrl_val() function sets CPU affinity and writes the parent process's PID into the control and monitoring groups in the resctrl file system before forking the benchmark child process. This causes several issues: 1. Writing the parent process's PID into the resctrl control group unnecessarily affects the behavior of the parent process, while the control group should only apply to the benchmark child process. 2. Writing the parent process's PID into the resctrl monitoring group introduces the parent process's activity into the bandwidth measurement, affecting the accuracy of the monitoring, which should only monitor the benchmark child process. 3. Since only the child process is monitored, the CPU affinity should also be set only on the child process to ensure that the PMU (Performance Monitoring Unit) can count memory bandwidth from the benchmark process. 4. When the parent and child processes are scheduled on the same CPU, the parent process's activity may interfere with the monitoring of the child process. This is particularly problematic in some ARM MPAM implementations, where memory bandwidth monitoring real-time values. When the child process is preempted off the CPU, this results in inaccurate monitoring. This commit moves the CPU affinity and resctrl FS setup to the child process after fork(), ensuring these settings only affect the benchmark process, thereby maintaining measurement accuracy and making the implementation more portable across platforms. Signed-off-by: Yifan Wu --- tools/testing/selftests/resctrl/resctrl_val.c | 68 +++++++++++-------- 1 file changed, 39 insertions(+), 29 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index 7c08e936572d..85ac96c7cb8f 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -545,7 +545,6 @@ int resctrl_val(const struct resctrl_test *test, cpu_set_t old_affinity; int domain_id; int ret =3D 0; - pid_t ppid; =20 if (strcmp(param->filename, "") =3D=3D 0) sprintf(param->filename, "stdio"); @@ -556,22 +555,10 @@ int resctrl_val(const struct resctrl_test *test, return ret; } =20 - ppid =3D getpid(); - - /* Taskset test to specified CPU. */ - ret =3D taskset_benchmark(ppid, uparams->cpu, &old_affinity); - if (ret) - return ret; - - /* Write test to specified control & monitoring group in resctrl FS. */ - ret =3D write_bm_pid_to_resctrl(ppid, param->ctrlgrp, param->mongrp); - if (ret) - goto reset_affinity; - if (param->init) { ret =3D param->init(param, domain_id); if (ret) - goto reset_affinity; + return ret; } =20 /* @@ -586,10 +573,8 @@ int resctrl_val(const struct resctrl_test *test, if (param->fill_buf) { buf =3D alloc_buffer(param->fill_buf->buf_size, param->fill_buf->memflush); - if (!buf) { - ret =3D -ENOMEM; - goto reset_affinity; - } + if (!buf) + return -ENOMEM; } =20 fflush(stdout); @@ -605,11 +590,26 @@ int resctrl_val(const struct resctrl_test *test, * terminated. */ if (bm_pid =3D=3D 0) { + bm_pid =3D getpid(); + + /* Taskset test to specified CPU. */ + ret =3D taskset_benchmark(bm_pid, uparams->cpu, &old_affinity); + if (ret) + exit(ret); + + /* Write test to specified control & monitoring group in resctrl FS. */ + ret =3D write_bm_pid_to_resctrl(bm_pid, param->ctrlgrp, param->mongrp); + if (ret) + goto reset_affinity; + if (param->fill_buf) fill_cache_read(buf, param->fill_buf->buf_size, false); else if (uparams->benchmark_cmd[0]) execvp(uparams->benchmark_cmd[0], (char **)uparams->benchmark_cmd); - exit(EXIT_SUCCESS); + +reset_affinity: + taskset_restore(bm_pid, &old_affinity); + exit(ret); } =20 ksft_print_msg("Benchmark PID: %d\n", (int)bm_pid); @@ -619,23 +619,33 @@ int resctrl_val(const struct resctrl_test *test, =20 /* Test runs until the callback setup() tells the test to stop. */ while (1) { - ret =3D param->setup(test, uparams, param); - if (ret =3D=3D END_OF_TESTS) { - ret =3D 0; + pid_t wpid =3D waitpid(bm_pid, &ret, WNOHANG); + + if (wpid =3D=3D -1) { + ret =3D -errno; + ksft_perror("Unable to waitpid"); break; } - if (ret < 0) - break; =20 - ret =3D param->measure(uparams, param, bm_pid); - if (ret) - break; + if (wpid =3D=3D 0) { + ret =3D param->setup(test, uparams, param); + if (ret =3D=3D END_OF_TESTS) { + ret =3D 0; + break; + } + if (ret < 0) + break; + + ret =3D param->measure(uparams, param, bm_pid); + if (ret) + break; + } else { + goto free_buf; + } } =20 kill(bm_pid, SIGKILL); free_buf: free(buf); -reset_affinity: - taskset_restore(ppid, &old_affinity); return ret; } --=20 2.33.0 From nobody Wed Apr 15 16:43:14 2026 Received: from canpmsgout07.his.huawei.com (canpmsgout07.his.huawei.com [113.46.200.222]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1BBE37E31D; Wed, 4 Mar 2026 04:03:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.222 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772597026; cv=none; b=TtHt/SAYOePV085PbXYUZY12Mt5D1rhxyZzct4cF8acU7b2EKrzycMArZnw5XogITE24+mmfQrSsKj0y8HNLepBmC9ItZjqvFbqO2qiv5H2LgltmHcQFzy2Ki5lmIGFeFHtvTgodzuyIqsEEuIxyL8E4H7ixiwRG96KSK9nmBW0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772597026; c=relaxed/simple; bh=/b9cQarmDgPBiNp5S4KSO8XSZUfsNyJjluqAS0foRTU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hvwjKOCyhLuAsNJ79L2InpGj2iSOGGQmV4ky9zAL/5kixK2DY3i+r9uBYvhkPmxEpAM1hje2SadYLy59Pff3+QNUJrBBv6R1b4zepDwlB9dyldHktm9jnndlRGzzbvfeeE1SxCcm/EiRq8dBNb9a4F3uF0lzqINbapzLuQE/DX0= ARC-Authentication-Results: i=1; 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Wed, 4 Mar 2026 11:58:46 +0800 (CST) Received: from kwepemk500005.china.huawei.com (unknown [7.202.194.90]) by mail.maildlp.com (Postfix) with ESMTPS id DDF8A40562; Wed, 4 Mar 2026 12:03:36 +0800 (CST) Received: from huawei.com (10.50.163.32) by kwepemk500005.china.huawei.com (7.202.194.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 4 Mar 2026 12:03:36 +0800 From: Yifan Wu To: , , , , , , , , , , , , , , CC: , , , , , Subject: [RFC patch 2/9] selftests/resctrl: Refactor resctrl_val.c for vendor-specific mem bw measurement Date: Wed, 4 Mar 2026 12:03:27 +0800 Message-ID: <20260304040334.765860-3-wuyifan50@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260304040334.765860-1-wuyifan50@huawei.com> References: <20260304040334.765860-1-wuyifan50@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To kwepemk500005.china.huawei.com (7.202.194.90) Content-Type: text/plain; charset="utf-8" Currently, the resctrl_val.c is tightly coupled with X86's uncore IMC counter, which is inapplicable on other platforms like ARM. This commit refactor resctrl_val.c by introducing a structure to support vendor-specific PMU, event and scale. This allows the test to dynamically select the PMU based on the detected CPU vendor, paving the way for supporting multiple vendors and architectures. Signed-off-by: Yifan Wu --- tools/testing/selftests/resctrl/resctrl_val.c | 48 +++++++++++++++---- 1 file changed, 40 insertions(+), 8 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index 85ac96c7cb8f..b0570c615aac 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -10,10 +10,7 @@ */ #include "resctrl.h" =20 -#define UNCORE_IMC "uncore_imc" -#define READ_FILE_NAME "events/cas_count_read" #define DYN_PMU_PATH "/sys/bus/event_source/devices" -#define SCALE 0.00006103515625 #define MAX_IMCS 20 #define MAX_TOKENS 5 =20 @@ -36,10 +33,30 @@ struct imc_counter_config { int fd; }; =20 +struct membw_read_config { + int vendor_id; + const char *name; + const char *event; + double scale; +}; + +static struct membw_read_config membw_read_configs[] =3D { + { + .vendor_id =3D ARCH_INTEL | ARCH_AMD | ARCH_HYGON, + .name =3D "uncore_imc", + .event =3D "events/cas_count_read", + .scale =3D 64.0 / MB, + }, + { + .vendor_id =3D NULL + } +}; + static char mbm_total_path[1024]; static int imcs; static struct imc_counter_config imc_counters_config[MAX_IMCS]; static const struct resctrl_test *current_test; +static struct membw_read_config *current_config; =20 static void read_mem_bw_initialize_perf_event_attr(int i) { @@ -133,7 +150,7 @@ static int read_from_imc_dir(char *imc_dir, int count) fclose(fp); =20 /* Get read config */ - sprintf(imc_counter_cfg, "%s%s", imc_dir, READ_FILE_NAME); + sprintf(imc_counter_cfg, "%s%s", imc_dir, current_config->event); fp =3D fopen(imc_counter_cfg, "r"); if (!fp) { ksft_perror("Failed to open iMC config file"); @@ -176,18 +193,18 @@ static int num_of_imcs(void) dp =3D opendir(DYN_PMU_PATH); if (dp) { while ((ep =3D readdir(dp))) { - temp =3D strstr(ep->d_name, UNCORE_IMC); + temp =3D strstr(ep->d_name, current_config->name); if (!temp) continue; =20 /* * imc counters are named as "uncore_imc_", hence * increment the pointer to point to . Note that - * sizeof(UNCORE_IMC) would count for null character as + * sizeof("uncore_imc") would count for null character as * well and hence the last underscore character in * uncore_imc'_' need not be counted. */ - temp =3D temp + sizeof(UNCORE_IMC); + temp =3D temp + strlen(current_config->name) + 1; =20 /* * Some directories under "DYN_PMU_PATH" could have @@ -328,7 +345,7 @@ static int get_read_mem_bw_imc(float *bw_imc) of_mul_read =3D (float)r_time_enabled / (float)r_time_running; =20 - reads +=3D r->return_value.value * of_mul_read * SCALE; + reads +=3D r->return_value.value * of_mul_read * current_config->scale; } =20 *bw_imc =3D reads; @@ -469,6 +486,21 @@ static int print_results_bw(char *filename, pid_t bm_p= id, float bw_imc, return 0; } =20 +int initialize_measure_read_mem_bw(const struct resctrl_val_param *param, = int domain_id) +{ + unsigned int vendor =3D get_vendor(); + + for (current_config =3D membw_read_configs; + !(current_config->vendor_id & vendor); + current_config++) + continue; + + if (!current_config->vendor_id) + return -1; + + return 0; +} + /* * measure_read_mem_bw - Measures read memory bandwidth numbers while benc= hmark runs * @uparams: User supplied parameters --=20 2.33.0 From nobody Wed Apr 15 16:43:14 2026 Received: from canpmsgout10.his.huawei.com (canpmsgout10.his.huawei.com [113.46.200.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8787537EFE9; Wed, 4 Mar 2026 04:03:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.225 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772597028; cv=none; b=XER/PE+4vsjtGYqOfNANKZgENVQ1JhIfrCnSvwfuYglokK93xUmNp3tz4VW5iS66Q9SjvqVAPQw5/1OUiDie1F3PLbTC8/vbbOQtfmBpk94mIQcWLKypxQe2/eWHD9rStiS064QPdmPfWHK1eXzkbn8e8SlYHvBIVF0BvChkNlg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772597028; c=relaxed/simple; bh=eZ6Qa95y7C/Qq2Ag9Q4FVbZmz8KbwNUm2y87w9RMIWk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WcrXX1zSTnqq3WDWTV5tsOEjdK5vdya+9eegeWQcRre2IizreCQaptI9Eq4bbNy1z5+wrDDB0tvQEe0Y1TN+2JX9JaQUc029byZ0kXgoZ+dUJsh7Bmvpw12xqjFOZAlh4IrurMGj6yiETw3SkqsrNsMFjGtYYdsFzQoDxcNNniA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=raRn0eCJ; arc=none smtp.client-ip=113.46.200.225 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="raRn0eCJ" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=l5MKVeWc1MFu02pEFQ4S+bTlOGPyv37doLYVbksQMw8=; b=raRn0eCJtHLRBC+S2WF3ovAe+oKbIcfnY4BS3Ba4zpHQpNwK6Of7boC15dAo7ZEjcN6C13fqr 7cm2dP8ei3QH8zI+ewFwMh+JL7q2I+MjOypNUyHYOaYFNXKro448Y8ULuxwy5Js1P/RDYiUp5VY 4GiRzjukhfjQ+YWbIC0FE/k= Received: from mail.maildlp.com (unknown [172.19.163.200]) by canpmsgout10.his.huawei.com (SkyGuard) with ESMTPS id 4fQf6c6l3hz1K98S; Wed, 4 Mar 2026 11:58:48 +0800 (CST) Received: from kwepemk500005.china.huawei.com (unknown [7.202.194.90]) by mail.maildlp.com (Postfix) with ESMTPS id 9305D4055B; Wed, 4 Mar 2026 12:03:37 +0800 (CST) Received: from huawei.com (10.50.163.32) by kwepemk500005.china.huawei.com (7.202.194.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 4 Mar 2026 12:03:36 +0800 From: Yifan Wu To: , , , , , , , , , , , , , , CC: , , , , , Subject: [RFC patch 3/9] selftests/resctrl: Use dynamic linked list for iMC counters config Date: Wed, 4 Mar 2026 12:03:28 +0800 Message-ID: <20260304040334.765860-4-wuyifan50@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260304040334.765860-1-wuyifan50@huawei.com> References: <20260304040334.765860-1-wuyifan50@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To kwepemk500005.china.huawei.com (7.202.194.90) Content-Type: text/plain; charset="utf-8" Currently, a fixed-size array is used to store the configurations for all discovered iMC counters, which has several issues: 1. Fixed Overhead: The array is allocated a fixed size, even if the platform has fewer iMCs. 2. Out-of-Bounds Access: On platforms with more iMC counters than MAX_IMCS, the num_of_imcs() function can return a larger number, leading to an array index out-of-bounds access. 3. Reduced Maintainability: The need to statically define MAX_IMCS for different architectures and vendors makes the code harder to maintain. 4. Redundancy: The num_of_imcs() function dynamically discovers the actual number of counters, making the static size declaration unnecessary and redundant. To address these issues, this commit refactors resctrl_val.c to use a dynamic linked list. The num_of_imcs() function now allocates and configures an imc_counter_config structure for each discovered iMC and adds it to a global list (imc_counters_configs). This change ensures that only the required memory is used and prevents the out-of-bounds issue. Additionally, a corresponding cleanup_read_mem_bw_imc() function is added to iterate through the list and free all allocated memory, preventing leaks. All function signatures that previously accepted an integer index have been updated to accept a pointer to the imc_counter_config struct, and the calling code has been updated to traverse the new list. Signed-off-by: Yifan Wu --- tools/testing/selftests/resctrl/resctrl.h | 1 + tools/testing/selftests/resctrl/resctrl_val.c | 132 ++++++++++-------- 2 files changed, 78 insertions(+), 55 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/self= tests/resctrl/resctrl.h index afe635b6e48d..75c595812e7d 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -24,6 +24,7 @@ #include #include #include +#include #include "kselftest.h" =20 #define MB (1024 * 1024) diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index b0570c615aac..68e46c863474 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -11,7 +11,6 @@ #include "resctrl.h" =20 #define DYN_PMU_PATH "/sys/bus/event_source/devices" -#define MAX_IMCS 20 #define MAX_TOKENS 5 =20 #define CON_MBM_LOCAL_BYTES_PATH \ @@ -31,6 +30,7 @@ struct imc_counter_config { struct perf_event_attr pe; struct membw_read_format return_value; int fd; + struct list_head imc_list; }; =20 struct membw_read_config { @@ -38,14 +38,18 @@ struct membw_read_config { const char *name; const char *event; double scale; + int (*num_of)(void); }; =20 +static int num_of_imcs(void); + static struct membw_read_config membw_read_configs[] =3D { { .vendor_id =3D ARCH_INTEL | ARCH_AMD | ARCH_HYGON, .name =3D "uncore_imc", .event =3D "events/cas_count_read", .scale =3D 64.0 / MB, + .num_of =3D num_of_imcs, }, { .vendor_id =3D NULL @@ -53,37 +57,38 @@ static struct membw_read_config membw_read_configs[] = =3D { }; =20 static char mbm_total_path[1024]; -static int imcs; -static struct imc_counter_config imc_counters_config[MAX_IMCS]; +LIST_HEAD(imc_counters_configs); static const struct resctrl_test *current_test; static struct membw_read_config *current_config; =20 -static void read_mem_bw_initialize_perf_event_attr(int i) +static void read_mem_bw_initialize_perf_event_attr(struct imc_counter_conf= ig *imc_counters_config) { - memset(&imc_counters_config[i].pe, 0, + memset(&imc_counters_config->pe, 0, sizeof(struct perf_event_attr)); - imc_counters_config[i].pe.type =3D imc_counters_config[i].type; - imc_counters_config[i].pe.size =3D sizeof(struct perf_event_attr); - imc_counters_config[i].pe.disabled =3D 1; - imc_counters_config[i].pe.inherit =3D 1; - imc_counters_config[i].pe.exclude_guest =3D 0; - imc_counters_config[i].pe.config =3D - imc_counters_config[i].umask << 8 | - imc_counters_config[i].event; - imc_counters_config[i].pe.sample_type =3D PERF_SAMPLE_IDENTIFIER; - imc_counters_config[i].pe.read_format =3D + imc_counters_config->pe.type =3D imc_counters_config->type; + imc_counters_config->pe.size =3D sizeof(struct perf_event_attr); + imc_counters_config->pe.disabled =3D 1; + imc_counters_config->pe.inherit =3D 1; + imc_counters_config->pe.exclude_guest =3D 0; + imc_counters_config->pe.config =3D + imc_counters_config->umask << 8 | + imc_counters_config->event; + imc_counters_config->pe.sample_type =3D PERF_SAMPLE_IDENTIFIER; + imc_counters_config->pe.read_format =3D PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_TOTAL_TIME_RUNNING; } =20 -static void read_mem_bw_ioctl_perf_event_ioc_reset_enable(int i) +static void read_mem_bw_ioctl_perf_event_ioc_reset_enable(struct imc_count= er_config + *imc_counters_config) { - ioctl(imc_counters_config[i].fd, PERF_EVENT_IOC_RESET, 0); - ioctl(imc_counters_config[i].fd, PERF_EVENT_IOC_ENABLE, 0); + ioctl(imc_counters_config->fd, PERF_EVENT_IOC_RESET, 0); + ioctl(imc_counters_config->fd, PERF_EVENT_IOC_ENABLE, 0); } =20 -static void read_mem_bw_ioctl_perf_event_ioc_disable(int i) +static void read_mem_bw_ioctl_perf_event_ioc_disable(struct imc_counter_co= nfig + *imc_counters_config) { - ioctl(imc_counters_config[i].fd, PERF_EVENT_IOC_DISABLE, 0); + ioctl(imc_counters_config->fd, PERF_EVENT_IOC_DISABLE, 0); } =20 /* @@ -91,7 +96,8 @@ static void read_mem_bw_ioctl_perf_event_ioc_disable(int = i) * @cas_count_cfg: Config * @count: iMC number */ -static void get_read_event_and_umask(char *cas_count_cfg, int count) +static void get_read_event_and_umask(char *cas_count_cfg, struct imc_count= er_config + *imc_counters_config) { char *token[MAX_TOKENS]; int i =3D 0; @@ -105,21 +111,21 @@ static void get_read_event_and_umask(char *cas_count_= cfg, int count) if (!token[i]) break; if (strcmp(token[i], "event") =3D=3D 0) - imc_counters_config[count].event =3D strtol(token[i + 1], NULL, 16); + imc_counters_config->event =3D strtol(token[i + 1], NULL, 16); if (strcmp(token[i], "umask") =3D=3D 0) - imc_counters_config[count].umask =3D strtol(token[i + 1], NULL, 16); + imc_counters_config->umask =3D strtol(token[i + 1], NULL, 16); } } =20 -static int open_perf_read_event(int i, int cpu_no) +static int open_perf_read_event(struct imc_counter_config *imc_counters_co= nfig, int cpu_no) { - imc_counters_config[i].fd =3D - perf_event_open(&imc_counters_config[i].pe, -1, cpu_no, -1, + imc_counters_config->fd =3D + perf_event_open(&imc_counters_config->pe, -1, cpu_no, -1, PERF_FLAG_FD_CLOEXEC); =20 - if (imc_counters_config[i].fd =3D=3D -1) { + if (imc_counters_config->fd =3D=3D -1) { fprintf(stderr, "Error opening leader %llx\n", - imc_counters_config[i].pe.config); + imc_counters_config->pe.config); =20 return -1; } @@ -128,7 +134,7 @@ static int open_perf_read_event(int i, int cpu_no) } =20 /* Get type and config of an iMC counter's read event. */ -static int read_from_imc_dir(char *imc_dir, int count) +static int read_from_imc_dir(char *imc_dir, struct imc_counter_config *imc= _counters_config) { char cas_count_cfg[1024], imc_counter_cfg[1024], imc_counter_type[1024]; FILE *fp; @@ -141,7 +147,7 @@ static int read_from_imc_dir(char *imc_dir, int count) =20 return -1; } - if (fscanf(fp, "%u", &imc_counters_config[count].type) <=3D 0) { + if (fscanf(fp, "%u", &imc_counters_config->type) <=3D 0) { ksft_perror("Could not get iMC type"); fclose(fp); =20 @@ -165,7 +171,7 @@ static int read_from_imc_dir(char *imc_dir, int count) } fclose(fp); =20 - get_read_event_and_umask(cas_count_cfg, count); + get_read_event_and_umask(cas_count_cfg, imc_counters_config); =20 return 0; } @@ -189,6 +195,7 @@ static int num_of_imcs(void) struct dirent *ep; int ret; DIR *dp; + struct imc_counter_config *imc_counters_config; =20 dp =3D opendir(DYN_PMU_PATH); if (dp) { @@ -212,14 +219,17 @@ static int num_of_imcs(void) * first character is a numerical digit or not. */ if (temp[0] >=3D '0' && temp[0] <=3D '9') { + imc_counters_config =3D malloc(sizeof(struct imc_counter_config)); sprintf(imc_dir, "%s/%s/", DYN_PMU_PATH, ep->d_name); - ret =3D read_from_imc_dir(imc_dir, count); + ret =3D read_from_imc_dir(imc_dir, imc_counters_config); if (ret) { + free(imc_counters_config); closedir(dp); =20 return ret; } + list_add(&imc_counters_config->imc_list, &imc_counters_configs); count++; } } @@ -240,26 +250,40 @@ static int num_of_imcs(void) =20 int initialize_read_mem_bw_imc(void) { - int imc; + struct imc_counter_config *imc_counters_config; =20 - imcs =3D num_of_imcs(); + int imcs =3D current_config->num_of(); if (imcs <=3D 0) return imcs; =20 /* Initialize perf_event_attr structures for all iMC's */ - for (imc =3D 0; imc < imcs; imc++) - read_mem_bw_initialize_perf_event_attr(imc); + list_for_each_entry(imc_counters_config, &imc_counters_configs, imc_list)= { + read_mem_bw_initialize_perf_event_attr(imc_counters_config); + } =20 return 0; } =20 +void cleanup_read_mem_bw_imc(void) +{ + struct imc_counter_config *imc_counters_config; + struct imc_counter_config *next_imc_counters_config; + + list_for_each_entry_safe(imc_counters_config, next_imc_counters_config, + &imc_counters_configs, imc_list) { + list_del(&imc_counters_config->imc_list); + free(imc_counters_config); + } + list_del_init(&imc_counters_configs); +} + static void perf_close_imc_read_mem_bw(void) { - int mc; + struct imc_counter_config *imc_counters_config; =20 - for (mc =3D 0; mc < imcs; mc++) { - if (imc_counters_config[mc].fd !=3D -1) - close(imc_counters_config[mc].fd); + list_for_each_entry(imc_counters_config, &imc_counters_configs, imc_list)= { + if (imc_counters_config->fd !=3D -1) + close(imc_counters_config->fd); } } =20 @@ -271,13 +295,14 @@ static void perf_close_imc_read_mem_bw(void) */ static int perf_open_imc_read_mem_bw(int cpu_no) { - int imc, ret; + int ret; + struct imc_counter_config *imc_counters_config; =20 - for (imc =3D 0; imc < imcs; imc++) - imc_counters_config[imc].fd =3D -1; + list_for_each_entry(imc_counters_config, &imc_counters_configs, imc_list) + imc_counters_config->fd =3D -1; =20 - for (imc =3D 0; imc < imcs; imc++) { - ret =3D open_perf_read_event(imc, cpu_no); + list_for_each_entry(imc_counters_config, &imc_counters_configs, imc_list)= { + ret =3D open_perf_read_event(imc_counters_config, cpu_no); if (ret) goto close_fds; } @@ -297,16 +322,16 @@ static int perf_open_imc_read_mem_bw(int cpu_no) */ static void do_imc_read_mem_bw_test(void) { - int imc; + struct imc_counter_config *imc_counters_config; =20 - for (imc =3D 0; imc < imcs; imc++) - read_mem_bw_ioctl_perf_event_ioc_reset_enable(imc); + list_for_each_entry(imc_counters_config, &imc_counters_configs, imc_list) + read_mem_bw_ioctl_perf_event_ioc_reset_enable(imc_counters_config); =20 sleep(1); =20 /* Stop counters after a second to get results. */ - for (imc =3D 0; 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Wed, 4 Mar 2026 12:03:37 +0800 From: Yifan Wu To: , , , , , , , , , , , , , , CC: , , , , , Subject: [RFC patch 4/9] selftests/resctrl: Move memory bandwidth measurement init and cleanup to resctrl_val.c Date: Wed, 4 Mar 2026 12:03:29 +0800 Message-ID: <20260304040334.765860-5-wuyifan50@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260304040334.765860-1-wuyifan50@huawei.com> References: <20260304040334.765860-1-wuyifan50@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To kwepemk500005.china.huawei.com (7.202.194.90) Content-Type: text/plain; charset="utf-8" The initialization for memory bandwidth measurement was duplicated across mbm_test.c and mba_test.c. This commit move the memory bandwidth measurement's initialization to resctrl_val.c. It introduces a new common initialization function, including the new vendor-specific configuration setup. Additionally, a cleanup call has been added to the test teardown routines to ensure that resources allocated during initialization are properly released. Signed-off-by: Yifan Wu --- tools/testing/selftests/resctrl/mba_test.c | 11 ++--------- tools/testing/selftests/resctrl/mbm_test.c | 11 ++--------- tools/testing/selftests/resctrl/resctrl_val.c | 8 ++++++++ 3 files changed, 12 insertions(+), 18 deletions(-) diff --git a/tools/testing/selftests/resctrl/mba_test.c b/tools/testing/sel= ftests/resctrl/mba_test.c index c7e9adc0368f..c41914f6a2e6 100644 --- a/tools/testing/selftests/resctrl/mba_test.c +++ b/tools/testing/selftests/resctrl/mba_test.c @@ -19,15 +19,7 @@ =20 static int mba_init(const struct resctrl_val_param *param, int domain_id) { - int ret; - - ret =3D initialize_read_mem_bw_imc(); - if (ret) - return ret; - - initialize_mem_bw_resctrl(param, domain_id); - - return 0; + return initialize_measure_read_mem_bw(param, domain_id); } =20 /* @@ -164,6 +156,7 @@ static int check_results(void) =20 static void mba_test_cleanup(void) { + cleanup_read_mem_bw_imc(); remove(RESULT_FILE_NAME); } =20 diff --git a/tools/testing/selftests/resctrl/mbm_test.c b/tools/testing/sel= ftests/resctrl/mbm_test.c index 84d8bc250539..1d4ef268db5a 100644 --- a/tools/testing/selftests/resctrl/mbm_test.c +++ b/tools/testing/selftests/resctrl/mbm_test.c @@ -85,15 +85,7 @@ static int check_results(size_t span) =20 static int mbm_init(const struct resctrl_val_param *param, int domain_id) { - int ret; - - ret =3D initialize_read_mem_bw_imc(); - if (ret) - return ret; - - initialize_mem_bw_resctrl(param, domain_id); - - return 0; + return initialize_measure_read_mem_bw(param, domain_id); } =20 static int mbm_setup(const struct resctrl_test *test, @@ -123,6 +115,7 @@ static int mbm_measure(const struct user_params *uparam= s, =20 static void mbm_test_cleanup(void) { + cleanup_read_mem_bw_imc(); remove(RESULT_FILE_NAME); } =20 diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index 68e46c863474..75a3d359f16b 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -520,6 +520,14 @@ int initialize_measure_read_mem_bw(const struct resctr= l_val_param *param, int do if (!current_config->vendor_id) return -1; =20 + int ret; + + ret =3D initialize_read_mem_bw_imc(); + if (ret) + return ret; + + initialize_mem_bw_resctrl(param, domain_id); + return 0; } =20 --=20 2.33.0 From nobody Wed Apr 15 16:43:14 2026 Received: from canpmsgout01.his.huawei.com (canpmsgout01.his.huawei.com [113.46.200.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8549937E30F; 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Wed, 4 Mar 2026 12:03:38 +0800 From: Yifan Wu To: , , , , , , , , , , , , , , CC: , , , , , Subject: [RFC patch 5/9] selftests/resctrl: Refactor CPU vendor detection to use lookup table Date: Wed, 4 Mar 2026 12:03:30 +0800 Message-ID: <20260304040334.765860-6-wuyifan50@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260304040334.765860-1-wuyifan50@huawei.com> References: <20260304040334.765860-1-wuyifan50@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To kwepemk500005.china.huawei.com (7.202.194.90) Content-Type: text/plain; charset="utf-8" Currently, the vendor detection is implemented using a series of hard-coded "if/else if" string comparisons, which does not support ARM, as the ARM implementer is indicated by other sequences in /proc/cpuinfo. This commit refactors the vendor detection to be data-driven and extensible. It introduces a lookup table to define all vendor-specific detection rules. This separates the detection algorithm from the data. The new lookup table is implemented as a variable-length array of nested anonymous structs to to map a file to a sequence of string and vendor. This makes the code cleaner, maintainable, and simplifies the addition of support for new vendors (e.g., ARM) in the future. Signed-off-by: Yifan Wu --- .../testing/selftests/resctrl/resctrl_tests.c | 82 ++++++++++++++----- 1 file changed, 60 insertions(+), 22 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testin= g/selftests/resctrl/resctrl_tests.c index dbcd5eea9fbc..419d876a97c2 100644 --- a/tools/testing/selftests/resctrl/resctrl_tests.c +++ b/tools/testing/selftests/resctrl/resctrl_tests.c @@ -23,39 +23,77 @@ static struct resctrl_test *resctrl_tests[] =3D { &l2_noncont_cat_test, }; =20 +#define VENDOR_ENTRY struct {\ + unsigned int vendor_id; \ + void *arg; \ + } + +#define SEQ_ENTRY struct {\ + char *format; \ + VENDOR_ENTRY *vendor; \ + } + +#define DETECTION_ENTRY struct {\ + char *pathname; \ + SEQ_ENTRY *seq; \ + } + +static DETECTION_ENTRY vendor_detection[] =3D { + { + .pathname =3D "/proc/cpuinfo", + .seq =3D (SEQ_ENTRY[]) { + { + .format =3D "vendor_id\t: %s\n", + .vendor =3D (VENDOR_ENTRY[]) { + { .vendor_id =3D ARCH_INTEL, .arg =3D "GenuineIntel" }, + { .vendor_id =3D ARCH_AMD, .arg =3D "AuthenticAMD" }, + { .vendor_id =3D ARCH_HYGON, .arg =3D "HygonGenuine" }, + { .vendor_id =3D 0, .arg =3D NULL } + } + } + } + }, + { .pathname =3D NULL, .seq =3D NULL} +}; + static unsigned int detect_vendor(void) { static unsigned int vendor_id; static bool initialized; - char *s =3D NULL; + char s[64]; FILE *inf; char *res; =20 if (initialized) return vendor_id; =20 - inf =3D fopen("/proc/cpuinfo", "r"); - if (!inf) { - vendor_id =3D 0; - initialized =3D true; - return vendor_id; + for (DETECTION_ENTRY *dentry =3D &vendor_detection[0]; + dentry && dentry->pathname; + dentry++) { + inf =3D fopen(dentry->pathname, "r"); + if (!inf) + continue; + for (SEQ_ENTRY *sentry =3D &dentry->seq[0]; + sentry && sentry->format; + sentry++) { + for (VENDOR_ENTRY *ventry =3D &sentry->vendor[0]; + ventry && ventry->vendor_id; + ventry++) { + snprintf(s, sizeof(s), sentry->format, ventry->arg); + char *res =3D fgrep(inf, s); + + if (res) { + free(res); + fclose(inf); + vendor_id =3D ventry->vendor_id; + goto out; + } + rewind(inf); + } + } + fclose(inf); } - - res =3D fgrep(inf, "vendor_id"); - - if (res) - s =3D strchr(res, ':'); - - if (s && !strcmp(s, ": GenuineIntel\n")) - vendor_id =3D ARCH_INTEL; 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charset="utf-8" Currently, the resctrl selftest suite only support x86 CPU vendors (Intel, AMD and Hygon). This commit adds support for HiSilicon CPUs detection, extending the test coverage, and paving the way for vendor-specific implementation adaptations on HiSilicon platform. Signed-off-by: Yifan Wu --- tools/testing/selftests/resctrl/resctrl.h | 1 + tools/testing/selftests/resctrl/resctrl_tests.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/self= tests/resctrl/resctrl.h index 75c595812e7d..0e91d9704023 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -41,6 +41,7 @@ #define ARCH_INTEL BIT(0) #define ARCH_AMD BIT(1) #define ARCH_HYGON BIT(2) +#define ARCH_HISILICON BIT(3) =20 #define END_OF_TESTS 1 =20 diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testin= g/selftests/resctrl/resctrl_tests.c index 419d876a97c2..3299ae01346f 100644 --- a/tools/testing/selftests/resctrl/resctrl_tests.c +++ b/tools/testing/selftests/resctrl/resctrl_tests.c @@ -49,6 +49,13 @@ static DETECTION_ENTRY vendor_detection[] =3D { { .vendor_id =3D ARCH_AMD, .arg =3D "AuthenticAMD" }, { .vendor_id =3D ARCH_HYGON, .arg =3D "HygonGenuine" }, { .vendor_id =3D 0, .arg =3D NULL } + }, + }, + { + .format =3D "CPU implementer\t: 0x%02x\n", + .vendor =3D (VENDOR_ENTRY[]) { + { .vendor_id =3D ARCH_HISILICON, .arg =3D 0x48 }, + { .vendor_id =3D 0, .arg =3D NULL } } } } --=20 2.33.0 From nobody Wed Apr 15 16:43:14 2026 Received: from canpmsgout03.his.huawei.com (canpmsgout03.his.huawei.com [113.46.200.218]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3581378D63; Wed, 4 Mar 2026 04:03:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.218 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772597023; cv=none; b=tnyt0Igchgp8h0dQd4ettMlFlOV/X1ZEvOCx4Z4+fCtlMP+qgj0bvdeDAjLYVmtPc4u2w0l1uWlVfcC7v3STrh3cc9/YdzdoABoVHzF2iolT+Aonmv8CrDOppHOiwuUL4grEBy4yFgTzfd95Ss3gcgkP8g7h8+pmpYjByq8xBDY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772597023; c=relaxed/simple; bh=2/2PNyS9aDWYQlBYb0+v74fcaJlv0+97uQt1dP68LD4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oAFGhRlbvxxzml1JfX83Ey8F6jyzJnHAN4ViRGbyuMtHCO0KvIyKMcKkrKkhNNX9YiTwakzdtuFfiy/+8hHD9iknSAJ32YkjnU5dGlZHlGRbzeXj6srmxXf9Ol7wLnbwxEeK7+qCdgqNmGSZ8j+esEHQSTbVBhFp+RqjBWbCn4U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=QF297jFb; arc=none smtp.client-ip=113.46.200.218 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="QF297jFb" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=ZQ9wWnEAwMMv/g7eRzDnV2DW+8y/+QLCcLxd0GCgf84=; b=QF297jFbKvG1asuxqe3FXJJ0t7oZhg/SxBhetaFCJg62EqP7B94mII5r2ni+5pc2HP4X5F3wS N5ikcTKs9EWzPtA91tFEVCqA16kKrAmyUG+2/Y6J7kZUr3hwvSdvY9GlBVcyCkX5BxPHbPuvZG+ gH3LIednybvjzVIvmqHgoMc= Received: from mail.maildlp.com (unknown [172.19.162.223]) by canpmsgout03.his.huawei.com (SkyGuard) with ESMTPS id 4fQf6T1C0BzpSwC; Wed, 4 Mar 2026 11:58:41 +0800 (CST) Received: from kwepemk500005.china.huawei.com (unknown [7.202.194.90]) by mail.maildlp.com (Postfix) with ESMTPS id 301C240569; Wed, 4 Mar 2026 12:03:40 +0800 (CST) Received: from huawei.com (10.50.163.32) by kwepemk500005.china.huawei.com (7.202.194.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 4 Mar 2026 12:03:39 +0800 From: Yifan Wu To: , , , , , , , , , , , , , , CC: , , , , , Subject: [RFC patch 7/9] selftests/resctrl: Add support for HiSilicon memory bandwidth measurement Date: Wed, 4 Mar 2026 12:03:32 +0800 Message-ID: <20260304040334.765860-8-wuyifan50@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260304040334.765860-1-wuyifan50@huawei.com> References: <20260304040334.765860-1-wuyifan50@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To kwepemk500005.china.huawei.com (7.202.194.90) Content-Type: text/plain; charset="utf-8" This commit adds support for HiSilicon memory bandwidth measurement by introducing vendor-specific implementations: 1. Counter Discovery for HiSilicon: A new function num_of_hisi_ddrc() is implemented. It discovers the HiSilicon DDRC PMUs in the PMU path, dynamically creating and linking counter structures into the global list for each one found. 2. Support for config Perf Event Attribute: To adapt HiSilicon's perf event configuration, struct imc_counter_config is augmented with a __u64 config field, and get_read_event_and_umask() is updated to parse a "config" token from the event files. The perf_event_attr configuration logic now uses this config value if available, falling back to the event/umask logic for Intel. 3. Resctrl Domain ID Discovery for MB: A new vendor-specific logic is added to get_domain_id() in resctrlfs.c. On HiSilicon platforms, when the resource is "MB", the domain ID is discovered by reading the NUMA Node ID from the CPU's topology path (/sys/devices/system/cpu/cpuX/topology/), as MPAM's Memory Bandwidth resource is scoped to NUMA domains. 4. Bandwidth Calculation Adjustment: The measure_read_mem_bw() function is modified to handle the fundamental difference in reporting between vendors: Intel's resctrl reports a cumulative historical delta value, which must be converted to a rate division by MB. HiSilicon MPAM reports a real-time value, which is used directly. These changes collectively enable the selftests to accurately measure memory bandwidth on HiSilicon platforms that implement MPAM. Signed-off-by: Yifan Wu --- tools/testing/selftests/resctrl/resctrl_val.c | 67 ++++++++++++++++++- tools/testing/selftests/resctrl/resctrlfs.c | 20 ++++++ 2 files changed, 85 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index 75a3d359f16b..2c3df653e6ce 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -15,6 +15,8 @@ =20 #define CON_MBM_LOCAL_BYTES_PATH \ "%s/%s/mon_data/mon_L3_%02d/mbm_local_bytes" +#define CON_MBM_TOTAL_BYTES_PATH \ + "%s/%s/mon_data/mon_MB_%02d/mbm_total_bytes" =20 struct membw_read_format { __u64 value; /* The value of the event */ @@ -27,6 +29,7 @@ struct imc_counter_config { __u32 type; __u64 event; __u64 umask; + __u64 config; struct perf_event_attr pe; struct membw_read_format return_value; int fd; @@ -39,9 +42,11 @@ struct membw_read_config { const char *event; double scale; int (*num_of)(void); + const char *mbm_path; }; =20 static int num_of_imcs(void); +static int num_of_hisi_ddrc(void); =20 static struct membw_read_config membw_read_configs[] =3D { { @@ -50,6 +55,15 @@ static struct membw_read_config membw_read_configs[] =3D= { .event =3D "events/cas_count_read", .scale =3D 64.0 / MB, .num_of =3D num_of_imcs, + .mbm_path =3D CON_MBM_LOCAL_BYTES_PATH + }, + { + .vendor_id =3D ARCH_HISILICON, + .name =3D "hisi_sccl%d_ddrc%d_%d", + .event =3D "events/flux_rd", + .scale =3D 32.0 / MB, + .num_of =3D num_of_hisi_ddrc, + .mbm_path =3D CON_MBM_TOTAL_BYTES_PATH }, { .vendor_id =3D NULL @@ -71,6 +85,7 @@ static void read_mem_bw_initialize_perf_event_attr(struct= imc_counter_config *im imc_counters_config->pe.inherit =3D 1; imc_counters_config->pe.exclude_guest =3D 0; imc_counters_config->pe.config =3D + imc_counters_config->config ? : imc_counters_config->umask << 8 | imc_counters_config->event; imc_counters_config->pe.sample_type =3D PERF_SAMPLE_IDENTIFIER; @@ -114,6 +129,8 @@ static void get_read_event_and_umask(char *cas_count_cf= g, struct imc_counter_con imc_counters_config->event =3D strtol(token[i + 1], NULL, 16); if (strcmp(token[i], "umask") =3D=3D 0) imc_counters_config->umask =3D strtol(token[i + 1], NULL, 16); + if (strcmp(token[i], "config") =3D=3D 0) + imc_counters_config->config =3D strtol(token[i + 1], NULL, 16); } } =20 @@ -248,6 +265,49 @@ static int num_of_imcs(void) return count; } =20 +static int num_of_hisi_ddrc(void) +{ + char hisi_ddrc_dir[512], *temp; + unsigned int count =3D 0; + struct dirent *ep; + int ret; + DIR *dp; + struct imc_counter_config *imc_counters_config; + + dp =3D opendir(DYN_PMU_PATH); + if (dp) { + while ((ep =3D readdir(dp))) { + if (!strstr(ep->d_name, "hisi") || !strstr(ep->d_name, "ddrc")) + continue; + + imc_counters_config =3D malloc(sizeof(struct imc_counter_config)); + sprintf(hisi_ddrc_dir, "%s/%s/", DYN_PMU_PATH, + ep->d_name); + ret =3D read_from_imc_dir(hisi_ddrc_dir, imc_counters_config); + if (ret) { + free(imc_counters_config); + closedir(dp); + + return ret; + } + list_add(&imc_counters_config->imc_list, &imc_counters_configs); + count++; + } + closedir(dp); + if (count =3D=3D 0) { + ksft_print_msg("Unable to find PMU counters\n"); + + return -1; + } + } else { + ksft_perror("Unable to open PMU directory"); + + return -1; + } + + return count; +} + int initialize_read_mem_bw_imc(void) { struct imc_counter_config *imc_counters_config; @@ -382,7 +442,7 @@ static int get_read_mem_bw_imc(float *bw_imc) void initialize_mem_bw_resctrl(const struct resctrl_val_param *param, int domain_id) { - sprintf(mbm_total_path, CON_MBM_LOCAL_BYTES_PATH, RESCTRL_PATH, + sprintf(mbm_total_path, current_config->mbm_path, RESCTRL_PATH, param->ctrlgrp, domain_id); } =20 @@ -579,7 +639,10 @@ int measure_read_mem_bw(const struct user_params *upar= ams, perf_close_imc_read_mem_bw(); fclose(mem_bw_fp); =20 - bw_resc =3D (bw_resc_end - bw_resc_start) / MB; + if (get_vendor() =3D=3D ARCH_HISILICON) + bw_resc =3D bw_resc_end; + else + bw_resc =3D (bw_resc_end - bw_resc_start) / MB; =20 return print_results_bw(param->filename, bm_pid, bw_imc, bw_resc); =20 diff --git a/tools/testing/selftests/resctrl/resctrlfs.c b/tools/testing/se= lftests/resctrl/resctrlfs.c index b9c1bfb6cc02..01b775cfe849 100644 --- a/tools/testing/selftests/resctrl/resctrlfs.c +++ b/tools/testing/selftests/resctrl/resctrlfs.c @@ -139,6 +139,26 @@ int get_domain_id(const char *resource, int cpu_no, in= t *domain_id) if (cache_num < 0) return cache_num; =20 + /* On HiSilicon's platform, the "MB" resource domain is associated with t= he NUMA Node. */ + if (get_vendor() =3D=3D ARCH_HISILICON && !strncmp(resource, "MB", sizeof= ("MB"))) { + struct dirent *ep; + DIR *dp; + + sprintf(phys_pkg_path, "%s%d/", PHYS_ID_PATH, cpu_no); + dp =3D opendir(phys_pkg_path); + if (dp) { + while ((ep =3D readdir(dp))) { + if (!strstr(ep->d_name, "node")) + continue; + if (sscanf(ep->d_name, "node%d\n", domain_id) =3D=3D 1) + return 0; + } + closedir(dp); + } + ksft_perror("Could not get domain ID"); + return -1; + } + sprintf(phys_pkg_path, "%s%d/cache/index%d/id", PHYS_ID_PATH, cpu_no, cac= he_num); =20 fp =3D fopen(phys_pkg_path, "r"); --=20 2.33.0 From nobody Wed Apr 15 16:43:14 2026 Received: from canpmsgout10.his.huawei.com (canpmsgout10.his.huawei.com [113.46.200.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54B0C37F72F; Wed, 4 Mar 2026 04:03:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 4 Mar 2026 12:03:40 +0800 From: Yifan Wu To: , , , , , , , , , , , , , , CC: , , , , , Subject: [RFC patch 8/9] selftests/resctrl: Add support for HiSilicon MBM/MBA test Date: Wed, 4 Mar 2026 12:03:33 +0800 Message-ID: <20260304040334.765860-9-wuyifan50@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260304040334.765860-1-wuyifan50@huawei.com> References: <20260304040334.765860-1-wuyifan50@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To kwepemk500005.china.huawei.com (7.202.194.90) Content-Type: text/plain; charset="utf-8" This commit adds the support to check and test this feature on HiSilicon platform. Specifically, this is because on HiSilicon platform, the mbm_total_bytes counter for MBM/MBA is located in the MB_MON, which is distinct from other monitoring paths. Signed-off-by: Yifan Wu --- tools/testing/selftests/resctrl/mba_test.c | 24 +++++++++++++++++++--- tools/testing/selftests/resctrl/mbm_test.c | 23 +++++++++++++++++---- 2 files changed, 40 insertions(+), 7 deletions(-) diff --git a/tools/testing/selftests/resctrl/mba_test.c b/tools/testing/sel= ftests/resctrl/mba_test.c index c41914f6a2e6..ebed2d2d6ce0 100644 --- a/tools/testing/selftests/resctrl/mba_test.c +++ b/tools/testing/selftests/resctrl/mba_test.c @@ -202,14 +202,32 @@ static int mba_run_test(const struct resctrl_test *te= st, const struct user_param =20 static bool mba_feature_check(const struct resctrl_test *test) { - return test_resource_feature_check(test) && - resctrl_mon_feature_exists("L3_MON", "mbm_local_bytes"); + unsigned int vendor =3D get_vendor(); + bool feature_exists =3D false; + + switch (vendor) { + case ARCH_INTEL: + feature_exists =3D test_resource_feature_check(test) && + resctrl_mon_feature_exists("L3_MON", "mbm_local_bytes"); + break; + + case ARCH_HISILICON: + feature_exists =3D test_resource_feature_check(test) && + resctrl_mon_feature_exists("MB_MON", "mbm_total_bytes"); + break; + + default: + break; + } + + return feature_exists; + } =20 struct resctrl_test mba_test =3D { .name =3D "MBA", .resource =3D "MB", - .vendor_specific =3D ARCH_INTEL, + .vendor_specific =3D ARCH_INTEL | ARCH_HISILICON, .feature_check =3D mba_feature_check, .run_test =3D mba_run_test, .cleanup =3D mba_test_cleanup, diff --git a/tools/testing/selftests/resctrl/mbm_test.c b/tools/testing/sel= ftests/resctrl/mbm_test.c index 1d4ef268db5a..44bb450398e7 100644 --- a/tools/testing/selftests/resctrl/mbm_test.c +++ b/tools/testing/selftests/resctrl/mbm_test.c @@ -161,14 +161,29 @@ static int mbm_run_test(const struct resctrl_test *te= st, const struct user_param =20 static bool mbm_feature_check(const struct resctrl_test *test) { - return resctrl_mon_feature_exists("L3_MON", "mbm_total_bytes") && - resctrl_mon_feature_exists("L3_MON", "mbm_local_bytes"); -} + unsigned int vendor =3D get_vendor(); + bool feature_exists =3D false; + + switch (vendor) { + case ARCH_INTEL: + feature_exists =3D resctrl_mon_feature_exists("L3_MON", "mbm_total_bytes= ") && + resctrl_mon_feature_exists("L3_MON", "mbm_local_bytes"); + break; + + case ARCH_HISILICON: + feature_exists =3D resctrl_mon_feature_exists("MB_MON", "mbm_total_bytes= "); + break; =20 + default: + break; + } + + return feature_exists; +} struct resctrl_test mbm_test =3D { .name =3D "MBM", .resource =3D "MB", - .vendor_specific =3D ARCH_INTEL, + .vendor_specific =3D ARCH_INTEL | ARCH_HISILICON, .feature_check =3D mbm_feature_check, .run_test =3D mbm_run_test, .cleanup =3D mbm_test_cleanup, --=20 2.33.0 From nobody Wed Apr 15 16:43:14 2026 Received: from canpmsgout02.his.huawei.com (canpmsgout02.his.huawei.com [113.46.200.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AA2537E2F4; Wed, 4 Mar 2026 04:03:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.217 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772597025; cv=none; b=MwJ/YcnrtsxJ6/F0bMfW3uN37DxcwwrR/GdGLz+Y1FWC9zwtJzTLnEcsoAGCxkEHBCfLXBwkULDjAgFER7B8SLalplov1St4p5sfXzvs2zMn5NrcpPNreVTldMfSh0BxDVtqUGSIzN4I0edHtHnCAoXazuTGx/yplEGhUeBRFM0= ARC-Message-Signature: i=1; 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a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=1o2MhPh9+ZeE7u/z+qBXrIbJ3flY0UMRQ5CbaMHY31U=; b=DCATHUJpULTz7dfsn5qUeqoLLAroUULOdj+2CCV6u74+I/mE7+TnRMoqyoDUac591cTZhKckm sSImPZ2kTA+chgVVy2XNDchJZcdH9b+7323FeEs8bh4l3NTPnNb7GdDz+xymsp7iW4mAOEdrfQm VNU7ZpRa5wkvRPuxHu+n8+M= Received: from mail.maildlp.com (unknown [172.19.162.140]) by canpmsgout02.his.huawei.com (SkyGuard) with ESMTPS id 4fQf6D2VJxzcbMV; Wed, 4 Mar 2026 11:58:28 +0800 (CST) Received: from kwepemk500005.china.huawei.com (unknown [7.202.194.90]) by mail.maildlp.com (Postfix) with ESMTPS id 7EB14202E6; Wed, 4 Mar 2026 12:03:41 +0800 (CST) Received: from huawei.com (10.50.163.32) by kwepemk500005.china.huawei.com (7.202.194.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 4 Mar 2026 12:03:40 +0800 From: Yifan Wu To: , , , , , , , , , , , , , , CC: , , , , , Subject: [RFC patch 9/9] selftests/resctrl: Add support for HiSilicon CAT/CMT test Date: Wed, 4 Mar 2026 12:03:34 +0800 Message-ID: <20260304040334.765860-10-wuyifan50@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260304040334.765860-1-wuyifan50@huawei.com> References: <20260304040334.765860-1-wuyifan50@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To kwepemk500005.china.huawei.com (7.202.194.90) Content-Type: text/plain; charset="utf-8" This commit adds support for HiSilicon CAT/CMT test by adapting the HiSilicon-specificed implementation. 1. Handle Cache Masking on HiSilicon: On HiSilicon's platform, all cache are shareable, platform-level non-contiguous CAT is not applicable, and the test should default to using the full cache. 2. Extend Non-Contiguous CAT Support: HiSilicon always support non-contiguous CBM. 3. Specify Mount Options for HiSilicon resctrlfs: When mounting the resctrl filesystem on HiSilicon platform, specify "l2" option. 4. Adjust Perf Event Attributes for ARM: ARM performance counters do not support mode exclusion. Signed-off-by: Yifan Wu --- tools/testing/selftests/resctrl/cache.c | 4 +++- tools/testing/selftests/resctrl/cat_test.c | 18 +++++++++++------- tools/testing/selftests/resctrl/resctrlfs.c | 5 ++++- 3 files changed, 18 insertions(+), 9 deletions(-) diff --git a/tools/testing/selftests/resctrl/cache.c b/tools/testing/selfte= sts/resctrl/cache.c index 1ff1104e6575..798aefc6cb29 100644 --- a/tools/testing/selftests/resctrl/cache.c +++ b/tools/testing/selftests/resctrl/cache.c @@ -13,7 +13,9 @@ void perf_event_attr_initialize(struct perf_event_attr *p= ea, __u64 config) pea->read_format =3D PERF_FORMAT_GROUP; pea->exclude_kernel =3D 1; pea->exclude_hv =3D 1; - pea->exclude_idle =3D 1; + /* ARM performance counters do not support mode exclusion */ + if (get_vendor() !=3D ARCH_HISILICON) + pea->exclude_idle =3D 1; pea->exclude_callchain_kernel =3D 1; pea->inherit =3D 1; pea->exclude_guest =3D 1; diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/sel= ftests/resctrl/cat_test.c index f00b622c1460..e5365665a6d3 100644 --- a/tools/testing/selftests/resctrl/cat_test.c +++ b/tools/testing/selftests/resctrl/cat_test.c @@ -245,11 +245,15 @@ static int cat_run_test(const struct resctrl_test *te= st, const struct user_param ret =3D get_full_cbm(test->resource, &full_cache_mask); if (ret) return ret; - /* Get the largest contiguous exclusive portion of the cache */ - ret =3D get_mask_no_shareable(test->resource, &long_mask); - if (ret) - return ret; - + if (get_vendor() =3D=3D ARCH_HISILICON) { + /* On HiSilicon's platform, all cache are shareable. */ + long_mask =3D full_cache_mask; + } else { + /* Get the largest contiguous exclusive portion of the cache */ + ret =3D get_mask_no_shareable(test->resource, &long_mask); + if (ret) + return ret; + } /* Get L3/L2 cache size */ ret =3D get_cache_size(uparams->cpu, test->resource, &cache_total_size); if (ret) @@ -292,8 +296,8 @@ static bool arch_supports_noncont_cat(const struct resc= trl_test *test) { unsigned int vendor_id =3D get_vendor(); =20 - /* AMD and Hygon always support non-contiguous CBM. */ - if (vendor_id =3D=3D ARCH_AMD || vendor_id =3D=3D ARCH_HYGON) + /* AMD and Hygon and HiSilicon always support non-contiguous CBM. */ + if (vendor_id =3D=3D ARCH_AMD || vendor_id =3D=3D ARCH_HYGON || vendor_id= =3D=3D ARCH_HISILICON) return true; =20 #if defined(__i386__) || defined(__x86_64__) /* arch */ diff --git a/tools/testing/selftests/resctrl/resctrlfs.c b/tools/testing/se= lftests/resctrl/resctrlfs.c index 01b775cfe849..7567d3b31efb 100644 --- a/tools/testing/selftests/resctrl/resctrlfs.c +++ b/tools/testing/selftests/resctrl/resctrlfs.c @@ -69,7 +69,10 @@ int mount_resctrlfs(void) return -1; =20 ksft_print_msg("Mounting resctrl to \"%s\"\n", RESCTRL_PATH); - ret =3D mount("resctrl", RESCTRL_PATH, "resctrl", 0, NULL); + if (get_vendor() =3D=3D ARCH_HISILICON) + ret =3D mount("resctrl", RESCTRL_PATH, "resctrl", 0, "l2"); + else + ret =3D mount("resctrl", RESCTRL_PATH, "resctrl", 0, NULL); if (ret) ksft_perror("mount"); =20 --=20 2.33.0