From nobody Tue Apr 7 12:38:52 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83FB038236A; Wed, 4 Mar 2026 21:01:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772658086; cv=none; b=bvRod+hHH+CGd06JP7I/6tSf4tn/4Go2WasRKwuXlqOm60E9j1VdopqTjZHCFtbp5ebKbJEtYhgu57AXAx1Yw6PvyqhdyTocRCGqE6ke0ulWRVH5/F20Lxc5kCx4xMddHL5Y+M99oyN+iyBYT6xc8utVzf8rw4UU2CIiMLe+77M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772658086; c=relaxed/simple; bh=W18nID6Ds1IUWT7XQqyotdnw5GBHgdabgbB7Y0/D6ts=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HSI5SVWiM05yTyOATRgEKh4zqU8KYCvO5Pc4bMrcZMLI02+97KLx/TA1THiV2f6SExoTaKOEP/BwUuIiZjtK9nWUTiCxHcDpJZLXgbDs3LgvDWyJKkWaUDyNVFLsspbQ0EQxZcd91+RIflMqQ6EW0D/2bdxMo4D/Ly6QM2aDCfA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ZTaEiEib; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ZTaEiEib" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1772658082; bh=W18nID6Ds1IUWT7XQqyotdnw5GBHgdabgbB7Y0/D6ts=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZTaEiEib96XOisoUpNam8xd6cwaQ940kp9/BrUyNgvG4tdjK5o8ALs0V84yJiISKG TpfI3JE8tif2OcO5KxjoyJfCV9lnupWKy+G5KCJtJSlY2pWH8DSk3RwGkIIEQ0pzJI OJFjzPeIOcq9BW1EvblTSC4olb8koaN+dj3oKXFW3rcOlzDs59j/KRVZssyCmug64j KbtAqHtVLM0oxoXOVd3rEVh9qY+ekPLTefNsW2v6kqrdKdkXqQ0ruRSInHgBZFoIan 27tEBhP8NKWn+k/mFsv0vtb+KG3Ed7Ew4XisfJqcN/uaLHBFxfipgnfHhK/Zu3Z/4R jhrfjXQVZuFng== Received: from localhost (unknown [86.123.23.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id BFEBB17E1005; Wed, 4 Mar 2026 22:01:22 +0100 (CET) From: Cristian Ciocaltea Date: Wed, 04 Mar 2026 23:00:40 +0200 Subject: [PATCH v5 1/4] media: dt-bindings: rockchip,vdec: Mark reg-names required for RK35{76,88} Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260304-vdec-reg-order-rk3576-v5-1-7006fad42c3a@collabora.com> References: <20260304-vdec-reg-order-rk3576-v5-0-7006fad42c3a@collabora.com> In-Reply-To: <20260304-vdec-reg-order-rk3576-v5-0-7006fad42c3a@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Detlev Casanova , Ezequiel Garcia , Mauro Carvalho Chehab , Nicolas Dufresne , Hans Verkuil Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , linux-media@vger.kernel.org, Conor Dooley X-Mailer: b4 0.14.3 The Rockchip Video Decoder driver expects reg-names to be mandatory for RK3576 and RK3588 SoCs, however the binding does not currently require the use of them. As a consequence, driver would fail to probe with a hypothetical devicetree that doesn't provide the reg-names for these SoCs, but which is otherwise a perfectly valid DT from the binding perspective. Update the binding and make reg-names required for the aforementioned SoCs. While this change introduces an ABI break, the expected impact on potential users would be minimal, if any, since the old SoCs are unaffected, while the video decoder support for these newer variants in mainline driver and devicetrees hasn't been released yet. Moreover, this is also a prerequisite for a subsequent binding update introducing an alternative reg-names order, according to the address-based listing in the vendor's datasheet. Reported-by: Conor Dooley Closes: https://lore.kernel.org/all/20260227-urologist-gratitude-7984733f2d= 41@spud/ Fixes: c6ffb7e1fb90 ("media: dt-bindings: rockchip: Document RK3588 Video D= ecoder bindings") Fixes: a5c4a6526476 ("media: dt-bindings: rockchip: Add RK3576 Video Decode= r bindings") Signed-off-by: Cristian Ciocaltea Acked-by: Conor Dooley Reviewed-by: Nicolas Dufresne --- Documentation/devicetree/bindings/media/rockchip,vdec.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/D= ocumentation/devicetree/bindings/media/rockchip,vdec.yaml index 809fda45b3bd..dc4ebb50b316 100644 --- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml @@ -123,6 +123,8 @@ allOf: minItems: 5 reset-names: minItems: 5 + required: + - reg-names else: properties: reg: --=20 2.52.0 From nobody Tue Apr 7 12:38:52 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C705638657A; Wed, 4 Mar 2026 21:01:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772658088; cv=none; b=Epk+4ejn/GLGOqhvTbnCgCYVJZPbvmCfQ9JK39kCBC5yM+gbruWRlsxAJ+UQXW1Ec/n/nUHg7761bWRuaY5cu7LKKj5nL+GM+s3h55QzV3WFWuXe6Cfp4542rbTLKGwJgrBgMpFB+oFvmNsVL6P9L2iGwCXzNo5Dz75Yxjf7DiE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772658088; c=relaxed/simple; bh=a/HGKKp36P4xwIgVOjxXKaE5Sm+HcFjvPXuxNlLisNk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AgOQElGuvSh+UxJzYd2WbfM/3Lf03S/iUHmGpw0uA4vcMEWZzh/Hh7yDNFJJLkSCGra5NnGJ4F1CzkpMktnStnFFyftgtOv3sngz85rS8pie6M2q3yKBZr1Ln8UNHZG6kIrXR9Bhte3DRFN+M4ygEQNwymExfT4zabsPLP0F02k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=kXMJaybA; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="kXMJaybA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1772658083; bh=a/HGKKp36P4xwIgVOjxXKaE5Sm+HcFjvPXuxNlLisNk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kXMJaybAEGK07Gwif/cj2yrNWjboBQUlWFjrANuL0U+WCHbbaka75eAJCcJe3keeE 0IBEZPUaecdjQZIYxPqGmNXu+2dinO519xQyrz89pMHVr8MbFUh8s8l4N9L2i8EvC3 wjhwG2x5Mf0MOmzydHAvbj9VJ2PU05g6Kn8aW4sYSy6bWJveJrSBhvr6jQVPMfxYv4 +MvBsh961jLAW4hTI1E+dV7KzDK5+g/KxTOKcK7+9kQW0EY9/USv5HASeqT5xu2aFF 5sE4faByX/1jycDkpaNqTafGhTkf+laH3xDMD/yvScINK6vKInXQEenPdxYhsNfiI8 oOveZ5KKhKaIw== Received: from localhost (unknown [86.123.23.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id A683F17E108B; Wed, 4 Mar 2026 22:01:23 +0100 (CET) From: Cristian Ciocaltea Date: Wed, 04 Mar 2026 23:00:41 +0200 Subject: [PATCH v5 2/4] media: dt-bindings: rockchip,vdec: Add alternative reg-names order for RK35{76,88} Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260304-vdec-reg-order-rk3576-v5-2-7006fad42c3a@collabora.com> References: <20260304-vdec-reg-order-rk3576-v5-0-7006fad42c3a@collabora.com> In-Reply-To: <20260304-vdec-reg-order-rk3576-v5-0-7006fad42c3a@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Detlev Casanova , Ezequiel Garcia , Mauro Carvalho Chehab , Nicolas Dufresne , Hans Verkuil Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , linux-media@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.3 With the introduction of the RK3588 SoC, and RK3576 afterwards, three register blocks have been provided for the video decoder unit instead of just one, which are further referenced in vendor's datasheet by 'link table', 'function' and 'cache'. The former is present at the top of the listing, starting at video decoder unit base address. However, while documenting RK3588, the binding broke the convention expecting the unit address to indicate the start of the primary register range, i.e. the 'function' block got listed before the 'link' one. Since the binding changes have been already released and a fix would bring up an ABI break, mark the current 'reg-names' ordering as deprecated and introduce an alternative 'link,function,cache' listing which follows the address-based ordering according to the TRM. Additionally, drop the 'reg' description items as the order is not fixed anymore, while the information they offer is not very relevant anyway. It's worth noting there are currently no (known) users impacted by these binding changes, since the video decoder support for the aforementioned SoCs in mainline driver and devicetrees hasn't been released yet - it landed in v7.0-rc1 while all DTS updates resulting from this will be handled before v7.0 is out. Fixes: c6ffb7e1fb90 ("media: dt-bindings: rockchip: Document RK3588 Video D= ecoder bindings") Fixes: a5c4a6526476 ("media: dt-bindings: rockchip: Add RK3576 Video Decode= r bindings") Reviewed-by: Nicolas Dufresne Reviewed-by: Krzysztof Kozlowski Signed-off-by: Cristian Ciocaltea --- .../devicetree/bindings/media/rockchip,vdec.yaml | 20 ++++++++++++----= ---- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/D= ocumentation/devicetree/bindings/media/rockchip,vdec.yaml index dc4ebb50b316..42022401d0ff 100644 --- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml @@ -28,16 +28,20 @@ properties: =20 reg: minItems: 1 - items: - - description: The function configuration registers base - - description: The link table configuration registers base - - description: The cache configuration registers base + maxItems: 3 =20 reg-names: - items: - - const: function - - const: link - - const: cache + oneOf: + - items: + - const: link + - const: function + - const: cache + - items: + - const: function + - const: link + - const: cache + deprecated: true + description: Use link,function,cache block order instead. =20 interrupts: maxItems: 1 --=20 2.52.0 From nobody Tue Apr 7 12:38:52 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87EA038422B; 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Wed, 4 Mar 2026 22:01:24 +0100 (CET) From: Cristian Ciocaltea Date: Wed, 04 Mar 2026 23:00:42 +0200 Subject: [PATCH v5 3/4] arm64: dts: rockchip: Fix vdec register blocks order on RK3576 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260304-vdec-reg-order-rk3576-v5-3-7006fad42c3a@collabora.com> References: <20260304-vdec-reg-order-rk3576-v5-0-7006fad42c3a@collabora.com> In-Reply-To: <20260304-vdec-reg-order-rk3576-v5-0-7006fad42c3a@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Detlev Casanova , Ezequiel Garcia , Mauro Carvalho Chehab , Nicolas Dufresne , Hans Verkuil Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , linux-media@vger.kernel.org X-Mailer: b4 0.14.3 When building device trees for the RK3576 based boards, DTC shows the following complaint: rk3576.dtsi:1282.30-1304.5: Warning (simple_bus_reg): /soc/video-codec@27= b00000: simple-bus unit address format error, expected "27b00100" Since the video decoder support for the aforementioned SoC in mainline driver and devicetrees hasn't been released yet (just landed in v7.0-rc1), fix the issue by providing the register blocks using the 'link,function,cache' listing, which follows the address-based order as shown in the vendor's datasheet and, implicitly, ensures the unit address points to the primary register range. Fixes: da0de806d8b4 ("arm64: dts: rockchip: Add the vdpu383 Video Decoder o= n rk3576") Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index 49ccdf12ef7e..45eb0d053a6f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1281,10 +1281,10 @@ gpu: gpu@27800000 { =20 vdec: video-codec@27b00000 { compatible =3D "rockchip,rk3576-vdec"; - reg =3D <0x0 0x27b00100 0x0 0x500>, - <0x0 0x27b00000 0x0 0x100>, + reg =3D <0x0 0x27b00000 0x0 0x100>, + <0x0 0x27b00100 0x0 0x500>, <0x0 0x27b00600 0x0 0x100>; - reg-names =3D "function", "link", "cache"; + reg-names =3D "link", "function", "cache"; interrupts =3D ; clocks =3D <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>, <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>, --=20 2.52.0 From nobody Tue Apr 7 12:38:52 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A30F388E4F; Wed, 4 Mar 2026 21:01:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772658089; cv=none; b=ulA0Ub9Y5Eap5U5ZRW9zD/N2bFVVDCZcowECnnyF/UuorQAoULPk1gi4OubLzaHLlfZBwSEXyeotNiuEv8ie2pxZUy43zfWYIxl33I4kjGhsKjP6eHt7PZkkLLGaWyVDvdzCWr0BGs6nUS3/55dKhUgK3GlhD1g/c6htWizFA0w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772658089; c=relaxed/simple; bh=7Pu/j2FA1dbN74NgBoJXDOll0xaVUjyO78TNdm4qOyU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lyVTP4u5UwATz2bqCz68KX7cmCBtiTKPVOH5W6j4JxzX4TQT+corvcmfapPABhfXPHTV1GKaqaWct0Vo47MMjEQ9kjNK9M8pf4aViYp8ctVUUJZFRbkF7ckARqGAjWWKGiFF5qcp7UB513BaKqS0FdVF/2TQTCLx/JtnRrlQgh0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=eyoxGK4j; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="eyoxGK4j" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1772658085; bh=7Pu/j2FA1dbN74NgBoJXDOll0xaVUjyO78TNdm4qOyU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=eyoxGK4jaK4/GknPSu/Bfp9WaLDZ/lpe9uRdvOqV5iiQslMZwIMhHnLQNBi3/vzBy DlnyRf/Yy/jha5dRa1DXk3lSNAtX+GgGSSJZLWRvH5AFxPN2ITum3fI4n6dc3idz6O sKjgbTF7bch0ddMaRGSRkNALIG5x+yRrLNzUV0ho2XhFi12/n+6AQ5ad2LZykVK6OV VOlEJ3WVZV/MlN9VuG5PrP54HK48FuJhFLl6P+iUx6j6Ua79ktHwgpQO3Geug7Ml9u pTBAzQzORXrKjWSRf3NIrREsc2nL0oLB8SpaM9Xjf3hB9LnsswJc2WxmVwJFBNwfNk xiHDC9ffTrjiw== Received: from localhost (unknown [86.123.23.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9752F17E129E; Wed, 4 Mar 2026 22:01:25 +0100 (CET) From: Cristian Ciocaltea Date: Wed, 04 Mar 2026 23:00:43 +0200 Subject: [PATCH v5 4/4] arm64: dts: rockchip: Update vdec register blocks order on RK3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260304-vdec-reg-order-rk3576-v5-4-7006fad42c3a@collabora.com> References: <20260304-vdec-reg-order-rk3576-v5-0-7006fad42c3a@collabora.com> In-Reply-To: <20260304-vdec-reg-order-rk3576-v5-0-7006fad42c3a@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Detlev Casanova , Ezequiel Garcia , Mauro Carvalho Chehab , Nicolas Dufresne , Hans Verkuil Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , linux-media@vger.kernel.org X-Mailer: b4 0.14.3 With the introduction of the RK3588 SoC, three register blocks have been provided for the video decoder unit instead of just one, which are further referenced in the vendor's datasheet by 'link table', 'function' and 'cache'. The former is present at the top of the listing, starting at video decoder unit base address, but the binding got this wrong initially, i.e. the 'function' block got listed before the 'link' one. Since the video decoder support for the aforementioned SoC in mainline driver and devicetrees hasn't been released yet (just landed in v7.0-rc1), address the problem by providing the register blocks for vdec0 & vdec1 nodes using the 'link,function,cache' listing, which ensures the unit address points to the primary register range. This aligns with a similar fix for RK3576, where DTC also complained about the bus address format. Fixes: f61731bd6062 ("arm64: dts: rockchip: Add the vdpu381 Video Decoders = on RK3588") Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 7fe9593d8c19..b95129f85aba 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1355,10 +1355,10 @@ vepu121_3_mmu: iommu@fdbac800 { =20 vdec0: video-codec@fdc38000 { compatible =3D "rockchip,rk3588-vdec"; - reg =3D <0x0 0xfdc38100 0x0 0x500>, - <0x0 0xfdc38000 0x0 0x100>, + reg =3D <0x0 0xfdc38000 0x0 0x100>, + <0x0 0xfdc38100 0x0 0x500>, <0x0 0xfdc38600 0x0 0x100>; - reg-names =3D "function", "link", "cache"; + reg-names =3D "link", "function", "cache"; interrupts =3D ; clocks =3D <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_C= A>, <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; @@ -1387,10 +1387,10 @@ vdec0_mmu: iommu@fdc38700 { =20 vdec1: video-codec@fdc40000 { compatible =3D "rockchip,rk3588-vdec"; - reg =3D <0x0 0xfdc40100 0x0 0x500>, - <0x0 0xfdc40000 0x0 0x100>, + reg =3D <0x0 0xfdc40000 0x0 0x100>, + <0x0 0xfdc40100 0x0 0x500>, <0x0 0xfdc40600 0x0 0x100>; - reg-names =3D "function", "link", "cache"; + reg-names =3D "link", "function", "cache"; interrupts =3D ; clocks =3D <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_C= A>, <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; --=20 2.52.0