From nobody Mon Apr 13 21:41:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0E742848A0; Wed, 4 Mar 2026 13:49:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772632155; cv=none; b=qd/x4j7PL7gV5h2Ux80xXWK2N/faLcd2k5a+NI6asmBMW4NU8yf6Mp9G2dbnytIqMxjEWKHe0WThwE0WIdvfm+HHddgqpUKq0RBQZD+aEHug6Mcym7RLj6fj2W5GS5ii+fybmA+0ItuR2kpu18VcHLTzQNC44dBAhr6oLox72co= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772632155; c=relaxed/simple; bh=MxzsAapppLE+8dV2RbQr3gOSjRpPALVoD/deaZcnxTE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=O1/2s2+kJfS0BaQ76tHSQ3d4QtXkEHkcZsLpPkJJQirm6DjUweiI4qOrd0WklJp8+gdK/F1yCEdpqhIAlzU0Wa/LNTELb+2kCPEV8kIM+orcDso6SW6/savwsY2ORQTqNjQj4AijXPYwih48NvMDR1N2Y5ri16U6d8DlOmSvfwI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YL1NFCVf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YL1NFCVf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1D2F2C2BCAF; Wed, 4 Mar 2026 13:49:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772632155; bh=MxzsAapppLE+8dV2RbQr3gOSjRpPALVoD/deaZcnxTE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=YL1NFCVf3XXvWn/HrD9/Kwb7G5EcH5zbSVoFZoLx09V2O4Prk3kxTz5kR174PKEPb qZoyBMyXBRNBxLSMF4ngl8+VhJ8Z6ztw0QqFdu+venZ06tzEAcyZghkUrEAlB3EpWB /SGA8jbvM86Vh7TkYa5nQjb5a/izZzLVRc9KfGYJ2lIAp7um7Xh/STxn/cZd8aJVNZ kL1ovk5rix08ok0Mq9C6UGRT8FzrqA1xJx/5DJc18FlDNJDNNQCiN0BrEnzJM2Lfe4 IU+PrZlZT0n5TTxt2QDwODFFPcSm/tH+k+DKeF2NsICRgXmlb6W989ccc2mdNY3lML qZBewG3iaK3xw== From: Konrad Dybcio Date: Wed, 04 Mar 2026 14:48:27 +0100 Subject: [PATCH 1/5] clk: qcom: dispcc-glymur: Fix DSI byte clock rate setting Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260304-topic-dsi_byte_fixup-v1-1-b79b29f83176@oss.qualcomm.com> References: <20260304-topic-dsi_byte_fixup-v1-0-b79b29f83176@oss.qualcomm.com> In-Reply-To: <20260304-topic-dsi_byte_fixup-v1-0-b79b29f83176@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Taniya Das , Dmitry Baryshkov , Luca Weiss , Dmitry Baryshkov , Ajit Pandey , Taniya Das , Jagadeesh Kona Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772632145; l=1502; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=Ts2BJkKZit7+6I3gWjETShyTjCfuuBSpIfDPQ8kJcTE=; b=Oh0bbCKVfqcCa6PbzquX5UrHTrJm0RcibjGEGKn+eUkSO+5eYJRBsJ8WnCvult2dg+f3Otmsr VEGts4q1OM/C+w1D5v61aMde9Rft52eCuPk5fb2S1vfPb9yl8gaoARB X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The clock tree for byte_clk_src is as follows: =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80byte0_clk= _src=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82 =E2=94=82 byte0_clk byte0_div_clk_src =E2=94=82 byte0_intf_clk If both of its direct children have CLK_SET_RATE_PARENT with different requests, byte0_clk_src (and its parent) will be reconfigured. In this case, byte0_intf should strictly follow the rate of byte0_clk (with some adjustments based on PHY mode). Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue. Fixes: b4d15211c408 ("clk: qcom: dispcc-glymur: Add support for Display Clo= ck Controller") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Taniya Das --- drivers/clk/qcom/dispcc-glymur.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-glymur.c b/drivers/clk/qcom/dispcc-gly= mur.c index 94053452e871..a8c3cbf591d1 100644 --- a/drivers/clk/qcom/dispcc-glymur.c +++ b/drivers/clk/qcom/dispcc-glymur.c @@ -747,7 +747,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk= _src =3D { &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; @@ -762,7 +761,6 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk= _src =3D { &disp_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; --=20 2.53.0 From nobody Mon Apr 13 21:41:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BD637080D; Wed, 4 Mar 2026 13:49:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772632160; cv=none; b=HGSAKulvCbr2974908TwZOnclph4nZH3lH2Oq2fPneeaeV6Fr9BjvbLta7JqeNdfhLIjAXlWHNoglzE5tsxgNqBXvTWicI7TT8P3UxRNfZFm4BR0aQMjMkjz8Bt/Fj4QsBRSmp+VxjjbFtHbDlj3sHeFp7QpX4MXrOyFT7+LLjI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772632160; c=relaxed/simple; bh=1d34+Yly/nC8wD0SX1hTAVOvXfMo2MjYJGnARV4R/GM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HsINe1zXOYo9EPhILKJ+0qL7fYC9sLOOuvS0VxG0Cc8O17zlu0cB1cW1RQto1gRO02X6sHgiH9r8G0pfAStZDIRg944cQVWPNIQdKNF/X0baPwOw72L+VuXEM/06gOKrmAN9Gb21jV+VZ0FStru6N2WScHZ+9pcJ2A9Y0lLLDeY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fiGYFin3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fiGYFin3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CB0A5C19423; Wed, 4 Mar 2026 13:49:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772632160; bh=1d34+Yly/nC8wD0SX1hTAVOvXfMo2MjYJGnARV4R/GM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=fiGYFin3dilAj1lR04O9UZBgksNah2KJBpsu19LNaNg/KidSQolElgnGwNC3eFPrj SxRHg4Iy5878+UHfLmxgzHBCIOAQy6kuijUboaqU0tTan9bMi49jjiyy5K8DQnx84U JxCAMpb1Dfl+6GV26lQbtcy4KD5l8ZYParapr0nw3kHhhzHYPpliSdBLY+M+BUvNOF 458ISEVBgOVNznoeycbjvUu3oUTMEcEnWsh5GTDmDfpYGvw7INJzRLQcqHSOhFfU4X HMHEBaXqz0FDgu/MAcqYZWJRNUE/vt4uAypyCQqo8Ehe3nekaTDZOpFiV1IgRfszhO l7iBpYXP6JGxw== From: Konrad Dybcio Date: Wed, 04 Mar 2026 14:48:28 +0100 Subject: [PATCH 2/5] clk: qcom: dispcc-kaanapali: Fix DSI byte clock rate setting Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260304-topic-dsi_byte_fixup-v1-2-b79b29f83176@oss.qualcomm.com> References: <20260304-topic-dsi_byte_fixup-v1-0-b79b29f83176@oss.qualcomm.com> In-Reply-To: <20260304-topic-dsi_byte_fixup-v1-0-b79b29f83176@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Taniya Das , Dmitry Baryshkov , Luca Weiss , Dmitry Baryshkov , Ajit Pandey , Taniya Das , Jagadeesh Kona Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772632145; l=1520; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=kh9a965RiZDaMq+xJBTBHJIKwlkkIHQYu8/VBDgz1rc=; b=N7ZjRVpbPEWd90O2G6h5lUBtTZnVHywfKGa93LkY6NgV2IAaUtf043OwDV2ALLM99+Jp9ZBPd uinO/uyg1WnB7t6PiaKL2JvfT2hI4+Ux4lP5cgFlPw4I6iJKMO2VG+4 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The clock tree for byte_clk_src is as follows: =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80byte0_clk= _src=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82 =E2=94=82 byte0_clk byte0_div_clk_src =E2=94=82 byte0_intf_clk If both of its direct children have CLK_SET_RATE_PARENT with different requests, byte0_clk_src (and its parent) will be reconfigured. In this case, byte0_intf should strictly follow the rate of byte0_clk (with some adjustments based on PHY mode). Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue. Fixes: 6c6750b7061c ("clk: qcom: dispcc: Add support for display clock cont= roller Kaanapali") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Taniya Das --- drivers/clk/qcom/dispcc-kaanapali.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-kaanapali.c b/drivers/clk/qcom/dispcc-= kaanapali.c index baae2ec1f72a..c1578cd07041 100644 --- a/drivers/clk/qcom/dispcc-kaanapali.c +++ b/drivers/clk/qcom/dispcc-kaanapali.c @@ -800,7 +800,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk= _src =3D { &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; @@ -815,7 +814,6 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk= _src =3D { &disp_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; --=20 2.53.0 From nobody Mon Apr 13 21:41:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80D2B269D18; Wed, 4 Mar 2026 13:49:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772632164; cv=none; b=Lse4WZACY78vaazZOrg7Wu/cYovR0B+SfDbHRy+mqv24Sv9yZGhFGuM6lR0vE9V0bDHwUlo1Y6mggL9uXgEFSAy/VoiD254hPZWUzot3o12nLa2OuFqeCFn2xn1m6Z/fWcMhqdrjfga2D0XMzXGw32H55tNLg/QdLLluwA4I5Ww= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772632164; c=relaxed/simple; bh=vdYSfYe+LY9za3MB3co5bUMVIiBopfdC/Z3KkpRvdaA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hv2340Zm8EIkml+5Ul1cTIJmZAG5bLV2P0b5vlUoU7ZqNlbzDJZL8a4eyPHU1PHsOzZ0hGWZcPrhe4rXu9gwvciPPBHGHQXt/xDoqhZ6gCeSR27a64CdZD/n8LOMDJQ/llRHUj8u0c9kPh7Apn3flx1AkQU972D4JP702hDM+0A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MzbY0BTm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MzbY0BTm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AF498C19423; Wed, 4 Mar 2026 13:49:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772632164; bh=vdYSfYe+LY9za3MB3co5bUMVIiBopfdC/Z3KkpRvdaA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MzbY0BTmTuplRqCm0bOoOT1HfCvdDRceRiIGD3nVCeEMK5SK10kMbVWfV2Mi6M2SI +eoBQ+iVQF6hItLJWzOihWVf+LQ7d2cosoaTpJadaXu1IwpbvDn/cw8X5uEKCoWJDc KATfkaCnnza2NjjugMU/McYI/cvV8wo7JkHcO27VXb0AAqxerSmqTmgZmh3TpjwIU3 +tukt7J40BRmFFFQZfwtY2QTjBLfwtiB8mo5m3jfl4XqqjJSiuWiIQzeaJ/IfBSNNY qXT3yz+Xu/MUyOXNJBP4IzwpBD4rg3IZyXi1gwKHLNhBELqkEoLTUw0lTSAcLo72UZ sgOCCv6FSzEGA== From: Konrad Dybcio Date: Wed, 04 Mar 2026 14:48:29 +0100 Subject: [PATCH 3/5] clk: qcom: dispcc-milos: Fix DSI byte clock rate setting Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260304-topic-dsi_byte_fixup-v1-3-b79b29f83176@oss.qualcomm.com> References: <20260304-topic-dsi_byte_fixup-v1-0-b79b29f83176@oss.qualcomm.com> In-Reply-To: <20260304-topic-dsi_byte_fixup-v1-0-b79b29f83176@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Taniya Das , Dmitry Baryshkov , Luca Weiss , Dmitry Baryshkov , Ajit Pandey , Taniya Das , Jagadeesh Kona Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772632145; l=1261; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=MF0JanTEWxNV/9f4S+Pk8kCafN/XJm2+GOsaJMVSqXg=; b=UZ5YCWXGwUbb3exjQ+pczZ6HMtnXaWWlPxhb6Vq8EvQS0dtDwOTkNjsC6EYJu9I8UDMTQ+ZPb 7rHPTGN3XgTCE9/Dn7fE5L3HUv7gKy/HMPR3FuHVVZDQcg+ZcoEIa/l X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The clock tree for byte_clk_src is as follows: =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80byte0_clk= _src=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82 =E2=94=82 byte0_clk byte0_div_clk_src =E2=94=82 byte0_intf_clk If both of its direct children have CLK_SET_RATE_PARENT with different requests, byte0_clk_src (and its parent) will be reconfigured. In this case, byte0_intf should strictly follow the rate of byte0_clk (with some adjustments based on PHY mode). Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue. Fixes: f40b5217dce1 ("clk: qcom: Add Display Clock controller (DISPCC) driv= er for Milos") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Taniya Das --- drivers/clk/qcom/dispcc-milos.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-milos.c b/drivers/clk/qcom/dispcc-milo= s.c index 95b6dd89d9ae..339cb1c63ba7 100644 --- a/drivers/clk/qcom/dispcc-milos.c +++ b/drivers/clk/qcom/dispcc-milos.c @@ -394,7 +394,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk= _src =3D { &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; --=20 2.53.0 From nobody Mon Apr 13 21:41:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E8F617B50F; Wed, 4 Mar 2026 13:49:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772632169; cv=none; b=Sy0re27Xt6myVT117eZzhpOvDok1kkKVfmnxiUJ9Z3tw2N5BVd5FyCkNFk+4GlK8ECqIOU6vzPneyRXMVPwiG7sEHqFI8pcE6ae0A13rxNbvWWadz/AYQkZwqD4aeMMYLXQyRfsMurNmjl1lcv2mFEAkN5yw5V13+iohQ1e/luU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772632169; c=relaxed/simple; bh=tXwAaUpiFy+aG+PKAec0mM+sb+k0tJWs9XuvpcWNvfI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iEfW5vhY+fKI2LY4VQCAmW45EH0yZtejet+DKEmU4CpzpccD5YZ+FlXg0Yla2EkjCX5x1/JyiXRl7Wv61epAhVeCWJng6U7wjBXI3f4zYjEPCFav9bJFpqYCGf8+wcE7R8fT8O3ktmvArL6rgq2vFlC7tXKQy7gCu7dEgWpBkec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lfUqqGv8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lfUqqGv8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AE2FBC19423; Wed, 4 Mar 2026 13:49:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772632169; bh=tXwAaUpiFy+aG+PKAec0mM+sb+k0tJWs9XuvpcWNvfI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lfUqqGv8c8bDUBcuydVKxN3NK74r6X+tdTEdr6ZmZkWb2OHD68taoga9Y/KRy2X96 MaHlr348yHx6ewXSjC2pKT9tugJq9XoxNc0iDK24gqd/oUEx3+C13XU2Tzd2EsMejC ZmFkm603kJ+ibhzBtgTwayo6ONLdSiza6MTn5f+wn/D9fuxISKm720MvAkZbOdmnwJ +AxvjS4H/a07xq4FFChG/RWI1VuPpUHYbl3BIxPPdedpW4W1tTUQZMsU2Mq2ZH63IA vvYCA4AP6my/edXOLP5TFkejzA9SbQcUMPwPvIV+QBrB2qr75IMO0tAys4ymKaoQOa bLKRTXDvacvuQ== From: Konrad Dybcio Date: Wed, 04 Mar 2026 14:48:30 +0100 Subject: [PATCH 4/5] clk: qcom: dispcc-sm4450: Fix DSI byte clock rate setting Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260304-topic-dsi_byte_fixup-v1-4-b79b29f83176@oss.qualcomm.com> References: <20260304-topic-dsi_byte_fixup-v1-0-b79b29f83176@oss.qualcomm.com> In-Reply-To: <20260304-topic-dsi_byte_fixup-v1-0-b79b29f83176@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Taniya Das , Dmitry Baryshkov , Luca Weiss , Dmitry Baryshkov , Ajit Pandey , Taniya Das , Jagadeesh Kona Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772632145; l=1248; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=IxpK8d4RGXEmZFXhHwoyNDlr2/yhORAj+x+P56/8HxA=; b=va9MXHuCX2ae9W74QtJ2JLtqpFs91IDwASe8+S7jPFZmdDD1MK3SZt+c3V9MhnyP/Usrl1M85 Fg8R8GCekYKD4L/ZBL1vISBdFIMrPWaQK9mRHhpkr+j50tiR+Jq1OGm X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The clock tree for byte_clk_src is as follows: =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80byte0_clk= _src=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82 =E2=94=82 byte0_clk byte0_div_clk_src =E2=94=82 byte0_intf_clk If both of its direct children have CLK_SET_RATE_PARENT with different requests, byte0_clk_src (and its parent) will be reconfigured. In this case, byte0_intf should strictly follow the rate of byte0_clk (with some adjustments based on PHY mode). Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue. Fixes: 76f05f1ec766 ("clk: qcom: Add DISPCC driver support for SM4450") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Taniya Das --- drivers/clk/qcom/dispcc-sm4450.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm4450.c b/drivers/clk/qcom/dispcc-sm4= 450.c index e8752d01c8e6..2fdacc26df69 100644 --- a/drivers/clk/qcom/dispcc-sm4450.c +++ b/drivers/clk/qcom/dispcc-sm4450.c @@ -335,7 +335,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk= _src =3D { &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; --=20 2.53.0 From nobody Mon Apr 13 21:41:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4ED523A2548; Wed, 4 Mar 2026 13:49:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772632174; cv=none; b=eXdkHh8S8CUkHLV7dlerm/jjVG1RgizjfwjWg097VaL2W5oYR7TUdkcsKfFbZ4dZGAr5JisSumVcGZY3WLFoREP7j9/4PNcq6TLW10f4mCDwcWrSkKsGLbBEWdXtKtqrxuuc4+StNjnmnL2TeZcaB6hS0vbuHltXfvAb2rxMNvA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772632174; c=relaxed/simple; bh=/zvBIzViXCnmWq7gAFkzLYQ4qp66HHM4tREbVGDHlSw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KeqNgdNvjdiGdEyzuo7vYuYJPyp64qfyN1QFL1GuCVQDRBT5/x8M3WT+KrHZCDKXHzOIQDrEXt6B6D2jVyao5UnQjl8bdQu7istwDf+VPezIyrvweRyaOZZizu4IBaj9j+Zt2svSfuw/BmWIY1wiS2zuUIJwLRygeWgWShhiq6s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=O+86SidY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="O+86SidY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A00A5C19423; Wed, 4 Mar 2026 13:49:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772632174; bh=/zvBIzViXCnmWq7gAFkzLYQ4qp66HHM4tREbVGDHlSw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=O+86SidYVzgGfADskDgfvB9b5U8U+FxSxiNUoKu8oyOI/n4tBjrh95ceJ8QrnYpFR RwM5lTc7Pfas5+ls5dhoQ4Ww7gKWr16wZ72vm0SZMtAHr4MZ2Bmb6q85SVC4ks7nfS 0pMoTFlFCIYWvwf2XNk3CLI0BxLvHqO2W4mlnMTCViLPmG5cOuYTeJriQl128B+tS4 YswAD4k5LMiTkbi/5D/wxBH4J7MGAi03t/BywaugEVqnWi1ywMtqFASnMYnY+toftT OX11fO7vMB6RzHnihbQobran38jw8LlT/r9affLAvbROeDVNr5jYqIeyTAbxp3uhc8 CHT0IWQ0fIlQA== From: Konrad Dybcio Date: Wed, 04 Mar 2026 14:48:31 +0100 Subject: [PATCH 5/5] clk: qcom: dispcc[01]-sa8775p: Fix DSI byte clock rate setting Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260304-topic-dsi_byte_fixup-v1-5-b79b29f83176@oss.qualcomm.com> References: <20260304-topic-dsi_byte_fixup-v1-0-b79b29f83176@oss.qualcomm.com> In-Reply-To: <20260304-topic-dsi_byte_fixup-v1-0-b79b29f83176@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Taniya Das , Dmitry Baryshkov , Luca Weiss , Dmitry Baryshkov , Ajit Pandey , Taniya Das , Jagadeesh Kona Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772632145; l=2287; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=NNT+5t8wCjqytWn7XBoP1TYWjfPiD/E23LUsV9YkTNA=; b=WEO9Ka/BxSEUArJaB1rInGNmXKWVrM9V4zbtrmVWlmwGGr+eiwmmhuOTxza5W7eRlUfryn5bE rNe01NO0vMtC/WJDxyJYH/pDw60eg5vdBXjLujslVoOzSmlp7lb+xF3 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The clock tree for byte_clk_src is as follows: =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80byte0_clk= _src=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82 =E2=94=82 byte0_clk byte0_div_clk_src =E2=94=82 byte0_intf_clk If both of its direct children have CLK_SET_RATE_PARENT with different requests, byte0_clk_src (and its parent) will be reconfigured. In this case, byte0_intf should strictly follow the rate of byte0_clk (with some adjustments based on PHY mode). Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue. Fixes: e700bfd2f976 ("clk: qcom: Add support for Display clock Controllers = on SA8775P") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Taniya Das --- drivers/clk/qcom/dispcc0-sa8775p.c | 2 -- drivers/clk/qcom/dispcc1-sa8775p.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/drivers/clk/qcom/dispcc0-sa8775p.c b/drivers/clk/qcom/dispcc0-= sa8775p.c index aeda9cf4bfee..b248fa970587 100644 --- a/drivers/clk/qcom/dispcc0-sa8775p.c +++ b/drivers/clk/qcom/dispcc0-sa8775p.c @@ -591,7 +591,6 @@ static struct clk_regmap_div mdss_0_disp_cc_mdss_byte0_= div_clk_src =3D { &mdss_0_disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; @@ -606,7 +605,6 @@ static struct clk_regmap_div mdss_0_disp_cc_mdss_byte1_= div_clk_src =3D { &mdss_0_disp_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; diff --git a/drivers/clk/qcom/dispcc1-sa8775p.c b/drivers/clk/qcom/dispcc1-= sa8775p.c index cd55d1c11902..9882edbb79f9 100644 --- a/drivers/clk/qcom/dispcc1-sa8775p.c +++ b/drivers/clk/qcom/dispcc1-sa8775p.c @@ -591,7 +591,6 @@ static struct clk_regmap_div mdss_1_disp_cc_mdss_byte0_= div_clk_src =3D { &mdss_1_disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; @@ -606,7 +605,6 @@ static struct clk_regmap_div mdss_1_disp_cc_mdss_byte1_= div_clk_src =3D { &mdss_1_disp_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; --=20 2.53.0