From nobody Thu Apr 9 19:21:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9352B39183B; Wed, 4 Mar 2026 11:05:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772622332; cv=none; b=o4T8dzD39ZfZa9ET+J7PoJ+tmVzIIw1V53XMa4fCrqlRdHCegL82Etv5H9vWGcSDa0gyKUtvQBdGf9YixnRvd3fgMY1gHUdnZ7MdPvhiGeLaDqyA757ZBead7UzclGpFO3BlondZhX3LS24KnNIZh94wCP/mTD0XcS1snHree5Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772622332; c=relaxed/simple; bh=0U86WNo0Z1KPyrYfx+eFGzAexTHQ6Omrg+jGefNkr5M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=raXw3Qmzd0OJS0bunaCGHEfzFymcex09ulEQsGFGztQrt7WtiMqNpRmgdl7d3c03LsDwid78YgFGlbM9QBxTyR4KhasAEz5+VWHfWBw13Z1oHGkUgO71wqf24Ioj93dpDqCZIO8jznzsAZ7x4K7z56dNIzDZXy7lnG4qYcIaYOQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tuQhPifV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tuQhPifV" Received: by smtp.kernel.org (Postfix) with ESMTPS id 559B4C2BC9E; Wed, 4 Mar 2026 11:05:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772622332; bh=0U86WNo0Z1KPyrYfx+eFGzAexTHQ6Omrg+jGefNkr5M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=tuQhPifVWB+XJqH/T2lIQJYWkOA8PvUPLTu1S/tkLu3rEQ1VbUEMfF7iKrKcZnn2C R6losqzAC+8p5OiHgIVXwbtNCisobnvT7e2fQUA0RM+U25ZsseH0OcEcXPwTBWAHEZ KeCd5UGkTq8JBdb7QYFVsuLSa2lFTLBApgZTyLMl2wyEdsDWC1RL+XILRb1+pTPG8H d+nCRyE/F7YXnFvK7FIaxcg5oZaYRYd16+Lwk3urICPUrApxeMtNqX8DpIA5pod6lD lpsNEytlv4Oj674Xhu+t9gAPBa192FQm4Rx/ebtcTHPmutsX6UPr5NvclfcZz/dILs YGw/OW68Qakxw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43243EB7ECF; Wed, 4 Mar 2026 11:05:32 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Wed, 04 Mar 2026 12:05:27 +0100 Subject: [PATCH v4 1/4] arm64: dts: rockchip: assign pipe clock to rk356x PCIe lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260304-rk3568-bri-r2-pro-fix-pcie-v4-1-37abd7ba29d0@ixit.cz> References: <20260304-rk3568-bri-r2-pro-fix-pcie-v4-0-37abd7ba29d0@ixit.cz> In-Reply-To: <20260304-rk3568-bri-r2-pro-fix-pcie-v4-0-37abd7ba29d0@ixit.cz> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Frank Wunderlich Cc: Martin Filla , Charalampos Mitrodimas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2523; i=david@ixit.cz; h=from:subject:message-id; bh=nJWr1cG55C7TfO8lmuP7iO4pkz7D7P5warAqQ5V7GaM=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpqBH5+76cstljDcdJQqO27u9npzazHz0WHktMs RATNgGZiVSJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaagR+QAKCRBgAj/E00kg ctxBD/wIdVOClRo0Xr9QvWclph7PqoDR44+VURYr41+YD/4RlyzAe/948Bu4XS2V4Ujyp+TfGH7 Jmnd831Htg/1Y/2nOK8Jfd5Dc7QFK+pihhm7IOy3AR9g54sz7ddaAvdRGz/xa6sh2zMO2U4JZQw ud8Z6oJsy3xJTeS11PTH8UUTQkjcnalAqsxQQPgtD+BShRVHQEPMvplR8TDyo8VVherlOjt7jdI bKI09/HIOLQKDh6hG9cCStcfRZpV6CinHfNMTdPHTtDOb6LdUC0a3SIdOxXcG+nxzRoJajGFkbW mBuk1ijJngCropAIITQGS7d1ROhXx4+m6ehxMFrjF2NNyd4tbuSBJ1LlQZdWIrDS5kSPwTfA6Us pX3v3XmIe0RLgcVkxzURUWjNA96va95xQnviXhAJwiBW3S3CVJTcXxW2LCxSFQ92d+X2Zdcn0t/ 0liNFDU1E8k2Ght8tBN5DQgB2lQgnRKDBdy7+CgEPwh0SJDtqJgauDNjiH3aQN7Cfg+UAAFl1Tq wEh8uNOoGXiLcrjaVjLD80e8BsCxfuXBeylgIcaW8vykJlb7mPtHenVOMUwAgeegFTND9tktZS1 T+4wQAbotfwUYigrPhhUE7rs+0EQ8IsZnaJOTmkBRFnqyqE3HbInprZNMvOmmyu/Ybw4om9BafU fwqmyGml7G0cjtg== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg These clocks are used by PCIe lanes, but we're missing from the definition. Suggested-by: Charalampos Mitrodimas Signed-off-by: David Heidelberg Reviewed-by: Shawn Lin --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++---- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 6 ++++-- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts= /rockchip/rk3568.dtsi index 658097ed69714..3bc653f027f1f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -155,9 +155,11 @@ pcie3x1: pcie@fe270000 { bus-range =3D <0x10 0x1f>; clocks =3D <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, - <&cru CLK_PCIE30X1_AUX_NDFT>; + <&cru CLK_PCIE30X1_AUX_NDFT>, + <&cru CLK_PCIE30X1_PIPE_DFT>; clock-names =3D "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; + "aclk_dbi", "pclk", "aux", + "pipe"; device_type =3D "pci"; interrupts =3D , , @@ -208,9 +210,11 @@ pcie3x2: pcie@fe280000 { bus-range =3D <0x20 0x2f>; clocks =3D <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, - <&cru CLK_PCIE30X2_AUX_NDFT>; + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&cru CLK_PCIE30X2_PIPE_DFT>; clock-names =3D "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; + "aclk_dbi", "pclk", "aux", + "pipe"; device_type =3D "pci"; interrupts =3D , , diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk356x-base.dtsi index 68b48606f6010..15741acac6274 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1020,9 +1020,11 @@ pcie2x1: pcie@fe260000 { bus-range =3D <0x0 0xf>; clocks =3D <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, - <&cru CLK_PCIE20_AUX_NDFT>; + <&cru CLK_PCIE20_AUX_NDFT>, + <&cru CLK_PCIE20_PIPE_DFT>; clock-names =3D "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; + "aclk_dbi", "pclk", "aux", + "pipe"; device_type =3D "pci"; #interrupt-cells =3D <1>; interrupt-map-mask =3D <0 0 0 7>; --=20 2.53.0