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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4160d26d9absm18006952fac.16.2026.03.04.00.22.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 00:22:03 -0800 (PST) From: Qiang Yu Date: Wed, 04 Mar 2026 00:21:59 -0800 Subject: [PATCH 5/5] arch: arm64: dts: qcom: Add support for PCIe3a Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260304-glymur_gen5x8_phy-v1-5-849e9a72e125@oss.qualcomm.com> References: <20260304-glymur_gen5x8_phy-v1-0-849e9a72e125@oss.qualcomm.com> In-Reply-To: <20260304-glymur_gen5x8_phy-v1-0-849e9a72e125@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772612517; l=9719; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=CePg7dQ0vJpQa3SXW4kxYjj7WXb0JcqLC2YXxOGT+EE=; b=hCMaiSxdCo4DP4ycMiEX8qExZXO+VWfrot14h1UEc+CNTH/sh60qtKwcYATrjo6Yvs93Hl0a/ TCg/nQgzIGUBTltURCUkg0rC/IqzpqKk5iCjr9KPXChhVBs46IdZV8X X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA0MDA2NCBTYWx0ZWRfX9t+pPpNqgBNa JEsMkmze3cPRNHk0qidXljKQAOnASVgQl2+dT+Oso13L/YqxfnVYwW22lhEhvcmL6VBVYaRKXgz jzDnG/iCWzbaQ1H1YRBlWYpggdPWoqlkO2czfVABbeG6I7nnNQOLzrEs595/sdcb2jmUomRdk2N ++uIyMdKIf9+KPMY2er233xJX1O7Kgt+H8vky61uklTrb6iMzXj2hqQl/i7TW5JbaPVu34RbqKh 15U5dSpFxCYpmIL3dDxrbwXmcoSPrO5gCO4zvhiElxc2ORlgNpI0YGuyBPNmV2tj+oTt/9xa6rl MLA+lCO1oq12tNd90UgowY5aNYuHOaIPH60wliSusSbnc36s3BNVJ2wd2tWtrVEAhpP5OrQ3xQT EQ6ssY9FWRVKZMvLf592HYoWgrJ7ML/AyJU7RlCb27f5+iwV9BJiKvF7Q3I8sami6wtCA4cyc4p ufEoKphTcL2zlvUdIog== X-Authority-Analysis: v=2.4 cv=VYv6/Vp9 c=1 sm=1 tr=0 ts=69a7ebac cx=c_pps a=+3WqYijBVYhDct2f5Fivkw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=hXbwWmyv05DepBt-Dp8A:9 a=QEXdDO2ut3YA:10 a=eYe2g0i6gJ5uXG_o6N4q:22 X-Proofpoint-GUID: BnFI7mEev7SdcFxzLItKdqgVHzaAHLVw X-Proofpoint-ORIG-GUID: BnFI7mEev7SdcFxzLItKdqgVHzaAHLVw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-04_04,2026-03-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 bulkscore=0 adultscore=0 spamscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603040064 Describe PCIe3a controller and PHY. Also add required system resources like regulators, clocks, interrupts and registers configuration for PCIe3a. Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/glymur.dtsi | 314 +++++++++++++++++++++++++++++++= +++- 1 file changed, 313 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index e269cec7942c85447892c0661f83171eded94f3b..9b8037007c61b9fd1090ec10f6c= 8a8c1b414b7ca 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -736,7 +736,7 @@ gcc: clock-controller@100000 { <0>, /* USB 2 Phy PCIE PIPEGMUX */ <0>, /* USB 2 Phy PIPEGMUX */ <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ - <0>, /* PCIe 3a */ + <&pcie3a_phy>, /* PCIe 3a */ <&pcie3b_phy>, /* PCIe 3b */ <&pcie4_phy>, /* PCIe 4 */ <&pcie5_phy>, /* PCIe 5 */ @@ -2360,6 +2360,318 @@ pcie_west_slv_noc: interconnect@1920000 { #interconnect-cells =3D <2>; }; =20 + pcie3a: pci@1c10000 { + device_type =3D "pci"; + compatible =3D "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x70000000 0x0 0xf20>, + <0x0 0x70000f40 0x0 0xa8>, + <0x0 0x70001000 0x0 0x4000>, + <0x0 0x70100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70000000 0x0 0x70300000 0x0 0x3d00000>, + <0x03000000 0x7 0x00000000 0x7 0x00000000 0x0 0x40000000>; + bus-range =3D <0 0xff>; + + dma-coherent; + + linux,pci-domain =3D <3>; + num-lanes =3D <8>; + + operating-points-v2 =3D <&pcie3a_opp_table>; + + msi-map =3D <0x0 &gic_its 0xb0000 0x10000>; + iommu-map =3D <0x0 &pcie_smmu 0x30000 0x10000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 848 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 849 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 850 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 851 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks =3D <&gcc GCC_PCIE_3A_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_west_anoc MASTER_PCIE_3A QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_3A QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + resets =3D <&gcc GCC_PCIE_3A_BCR>, + <&gcc GCC_PCIE_3A_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc GCC_PCIE_3A_GDSC>; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555 + 0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + eq-presets-32gts =3D /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + + status =3D "disabled"; + + pcie3a_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x8 */ + opp-20000000-1 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + opp-level =3D <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x8 */ + opp-40000000-2 { + opp-hz =3D /bits/ 64 <40000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <4000000 1>; + opp-level =3D <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <984500 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x8 */ + opp-64000000-3 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x8 */ + opp-128000000-4 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <15753000 1>; + opp-level =3D <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <15753000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x8 */ + opp-256000000-5 { + opp-hz =3D /bits/ 64 <256000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <31506000 1>; + opp-level =3D <5>; + }; + }; + + pcie3a_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie3a_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie3a_phy: phy@f00000 { + compatible =3D "qcom,glymur-qmp-gen5x8-pcie-phy"; + reg =3D <0 0x00f00000 0 0x10000>; + + clocks =3D <&gcc GCC_PCIE_PHY_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3A_PIPE_CLK>, + <&gcc GCC_PCIE_PHY_3B_AUX_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "phy_b_aux"; + + resets =3D <&gcc GCC_PCIE_3A_PHY_BCR>, + <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr", + "phy_b", + "phy_b_nocsr"; + + assigned-clocks =3D <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + power-domains =3D <&gcc GCC_PCIE_3A_PHY_GDSC>, + <&gcc GCC_PCIE_3B_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie3a_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + pcie4: pci@1bf0000 { device_type =3D "pci"; compatible =3D "qcom,glymur-pcie", "qcom,pcie-x1e80100"; --=20 2.34.1