From nobody Thu Apr 2 12:13:32 2026 Received: from MRWPR03CU001.outbound.protection.outlook.com (mail-francesouthazon11011051.outbound.protection.outlook.com [40.107.130.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E43153542D8; Wed, 4 Mar 2026 11:34:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.130.51 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624093; cv=fail; b=pJlXt+Z78xm8GOSscoF/Rry40VPMu4dYeTl3J2ORJXrhGF20fqOF1IJOfVwwxkqXODoM71wZX+PkxwnvRn1s2bxMtfqY3+Fpsc/lS+6AjFCaq3xrdLkYkP2goJmiTcUtLN58OJaivX7QBOQN91+4/kU2ZH1nsJ+PoFD1A07kMVU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624093; c=relaxed/simple; bh=xdKnbX/USz/50VxM3bQS8xJotg78rpvnjETnVvMEKHA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=KNQ0X0dzLYXShUzyxbA7AT3JaQx7hvrfCl5uyhf6Cqu6XuqaxJD0vAOYkh4vZu70cD45ahsNHd5gRhEvRj0kSyJnEVOX1r7TMeGeLneM33/dez3UkCeIlc9BC4hdVS9QhtitaIk2eO0ECTDVYSoSSkFkJJZlnG2cZ67yPOKu3A0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=eC1FyJUg; arc=fail smtp.client-ip=40.107.130.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="eC1FyJUg" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=xktP9cl5J0XXg1e1KeWhc+71zvmCtMQPYGtVxTzxpcFC2lxQuvetmMYjb1W4EsJOKQDQWpP72i8BaYqRYhZ/I4w60kg4tK5OTXOiCkVkDbUzdMm34CPVQkqrmfTVSaJXuooARK5ui9SOpH6y2P+vpPDNnnaQbteiN5CIJ88S8wF3u/s/bKestqKP737nRxpTqjXDqQv1k/9df48owPmsskRFkdjtQ3ZQNx4wfCpK4QJ/0omawUJpwGs9jZSS5icjsADMFNVBOSk9yFQbr2XjOJ+8Yd0C3JIUB3tAEjfJ1Ud8zNpi//JeFUnz/2SbEta07ioT95VVnktt1zQo+RBsMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bkkMlRHRMa0R1vMZ0wcCMT9hJOHlKA1WbEGTSAhUed4=; b=GoirUmK/+gzaCRyyY8sfIN1/fgj8JDr8ytCsQpMUJallhxAWrHajPmlWhOUai0QkcLbXLj6k+8U8mylgDzFGhJk2rU5JzAg1mq53md9KOfhG6ctXmeDD765q5mAevSeJSjgW4VGAZkRiyG3bhx4qG3UueIIjhEz0o14tT3O+knhmI2e0zZR8e4IYuXgjmdFHtVng/X531ApFJr/RVKToAPiIhMCHee+XKEuWD6ReN63jmmcclCct+rHr4LylgiSVUreomEUjaor4TSAvXW2AUIDwsNW0KG2DRx9QBHGuQftW+MAbHmQIn4IbbyyIQolfq8cRjngUH5OtWPq/0wa72g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bkkMlRHRMa0R1vMZ0wcCMT9hJOHlKA1WbEGTSAhUed4=; b=eC1FyJUgiaZBYITC/PaNm+PiXGh+yw8ymm43rIu26N/W5UzvhfF2jPKpvi9sh3GCcT2/fvW6yUK9OjmsqoJRJjCuD4gjig/L/WTgngvhmdDjayeqgJrhJKlgQrvsLHNwTCmYR2i0wRVYRkJipazFj5UpbEog7tJZVJ33InX0oPn+lF9PlTPIsTXSry1AOht/COlrlx5XA15k0ndqeG5L4ZjPBE116PanuGGj2+NKIRYzfo8bfZcXjeNGsI/A3cFoU1hMmXlFSCMIICMjRQOSRQ69oLsj3ctpKhOi40aFZJDJIf3f8DnE/CgFSZTa4tB6ezyCD1VA6KQLQxJgWkknuw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) by AM0PR04MB7188.eurprd04.prod.outlook.com (2603:10a6:208:192::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.22; Wed, 4 Mar 2026 11:34:46 +0000 Received: from GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2]) by GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2%5]) with mapi id 15.20.9654.022; Wed, 4 Mar 2026 11:34:46 +0000 From: Laurentiu Palcu To: imx@lists.linux.dev, Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Vasut Cc: dri-devel@lists.freedesktop.org, Frank Li , Ying Liu , Laurentiu Palcu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 1/9] dt-bindings: display: fsl,ldb: Add i.MX94 LDB Date: Wed, 4 Mar 2026 11:34:10 +0000 Message-ID: <20260304-dcif-upstreaming-v8-1-bec5c047edd4@oss.nxp.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> References: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AS4P190CA0014.EURP190.PROD.OUTLOOK.COM (2603:10a6:20b:5de::18) To GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV1PR04MB9135:EE_|AM0PR04MB7188:EE_ X-MS-Office365-Filtering-Correlation-Id: 882d20a8-a457-4b18-ac8d-08de79e209ad X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|19092799006|366016|376014|7416014|921020; X-Microsoft-Antispam-Message-Info: spyGv88X4MkbLr8Jaaa59NCb4tWm/R88ACd7kUlLSKg20zmdcH9mBNDhSw1bgc/4gX4wxhft9SOa65IzumkdmKQ4p4MGrQJBwyOBAbRFrbJW/yOh/tkcyNzPxxFH+wMq792+KN00vC6DyF3KvedHTr3NXxpOGvnLmOhGnkqSnQo6t1O20wvpI6DX0wOKX7I6CtXKdkFbNWpmPjD7M0qha8SB//0JgGI4WO9ryk7/BterNEpu6bpx8qAkJ6CyZ255boS9in7gGLB41+3LOSOxa+0cRrAKCna4YNXbV5O731VyVmGN6S2wKy+mVa3zH/Y52YihO4Rwvxl2Qnwvae7wSZuZfXs5ERDlPYGRgwBT1g7TXjS1HmIjRNdxau4CTwE7UBt6jJ34JxSR+JN06GNcFaO5lyGivErSf+VjGGOtTp7gUEPUdH/Fu6EjK0s/4wi4t2RBIQ8Y3aKtDXS6cO6JEkc7iBo5dy155SXjrk9MTN80LnzhcFpL4n4CW6dZSPkAEafeQvEnj3m0YKhspjwrcqgk0SToAbalbuY/sBlvDsfGrOX2QBpkI2JRG9GVygz9VWuayYrHJxh56a8d+P5kwxfAesxNXjl54d7IsUI6q6s+PAJw+tp1Exty21LiJtwHMTnszlcg25u95k3c3ktg8A8IWdqDSNpjYgwM/UDcTcy2OrAoN2jvpTwlisRsERtVKThHojRwRM8I4gYR+o79QYuVsMak84PX3WoNdjyklddjd2Z7iqCMIIkXxVyPiNLwidkH0Ycq/POz60l+NHhsHA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:GV1PR04MB9135.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(19092799006)(366016)(376014)(7416014)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?TGRjMmdIMXNUUDU0b2g3SFA5ZFhOYkc3aytKU1Q1bUtsc0lZUmRBR1dYNmNn?= =?utf-8?B?RW1tYUlJSlluQzkvQ1NlSXdRMGJkcFFNTkJUTEQzVVV4MExXb2ZSbDB1MEdO?= =?utf-8?B?TTQxeDhlcnRJZWFWZjNjWWkvNDdkdisrOEJZRWNYM3BWMmJhOWd0enByZzEy?= =?utf-8?B?UFlaTXhUNjV1bHRwZjN0UzBvek4yZC9UZjdGalQ0QStqMWlxL1JZQmJpVk1t?= =?utf-8?B?SU93TDV0Y0NlZE1IUlFSNEpxY1NtRjBCYVJVRWo5UWRtNlpSa1NSVzlXOERn?= =?utf-8?B?STRHSHV1QnNYbXNhNzB1eTIyVlFZTzZabWFvZXRKMVcxY0hTU2RORzltbW1j?= =?utf-8?B?dGxJbFVwOFVyQml0TFpmdEYwWWVXcFV5RlNXOVZJbG8wcjFoUzdEaUVrZnVO?= =?utf-8?B?YmFSTE5BYmZyZmppZ0JXK3FvT2JON1hDM0lCb3V4eDliamc2ejdjamlrck1w?= =?utf-8?B?T1FXeW9nZDRWb3FaYnk4bVBSOVllOHVIanJScXhocTY2ZDRFaWdIcFZ6cGRH?= =?utf-8?B?YWtmdm45QStkWGtPWUlhTVp2NlYyTDRIWjY2Zm5QTWlod0pEYjZqa05VeVp1?= =?utf-8?B?L2IvdkRmMjdaZS9NMHdoU2VUQ2NsQWF2YkxMWDlkd2ZRaFozeWkycHFxTWln?= =?utf-8?B?eXh6dEFJY2tOMk0xeFNuWDM1ZWkrVjQ2emEweFBlcDhwQUNvVzFLOEVOY2I3?= =?utf-8?B?dFlGcnlVbzNycDFNc2JxcTErd0dnVGozVG84Z213U0M1MHFHSWJZV2Q4SEhr?= =?utf-8?B?aUZqV0oyMWRhUE9UTng3RFkreXM1UndTNmRzb2xYMHNheGd4ODhpd0M2S1E5?= =?utf-8?B?UHhsUDRoV2hTUFdvajN5MnlXQ1QrS3AzWVA4SVFuVWxsOTQ2ZmFyRkVzU1U3?= =?utf-8?B?Wnp2dGtZdmpYM1VBWWk1c0Y1U0xCOFcvcVFjVHZXSGR6Y3gvNnpWK2dqNUZL?= =?utf-8?B?TGpQemFMSklkNnlpZVRzcFdBNy9Nd1ZxR0pTNm5VZWE0R05keitQMEFyMit4?= =?utf-8?B?VlJ3SDd1ZXoxLzhLWHF3K1dQdHRGKzFlNXc4QUdXODVzdlVUeFRWa256V0V6?= =?utf-8?B?WHFJZTR6MGYxM0l5NG5tUnlFNlVsLzZPNjNRRzI4UFM0YlA4eWRnMy81RDZO?= =?utf-8?B?V0crbHFtYnN0UUQ3SGZnTGJ4Q0tPTGVSVXdObDhEV2wvdkhnVTNxRzFwY0JD?= =?utf-8?B?UUZsMndoYmR2NlZibWc5TU5veWhEOE5ZekRScXgrT1ZQUGR6V2dIMG5abU1o?= =?utf-8?B?TjV3YXFXMWYwb2RlNndoSUFtVnErNEkwVEVoRGRVODBpZHNZZ2l6bkVMQjd2?= =?utf-8?B?TU5aZW5GMTh6bUZPQy9nM1ZWQTVYK0wvVUxPLzYyNGJtc1NOT0VPUWJ2RXFv?= =?utf-8?B?RkVXM2k2aXdlRE9QSzN4aSt4Y05LdGVBK0JseEtSaVhSems5YVRxUDJHck9n?= =?utf-8?B?QXRwOFlDNTNiUTRIZUsxdU1TREs2ZWdDcjd1bGpxVDNBREdyTzlEeDc5ZVBV?= =?utf-8?B?c2xmcjhmRmE0ekFaZ1RDNWRveFJDQVlQc3N3RCtkaHh5WFpaVUh6UFROTlF5?= =?utf-8?B?UkFSQ2lJZlpvVWtOT3BGSy9IdEkxVVR6NU5wRVNZUm5lWlBIakVmZm1mRWZk?= =?utf-8?B?K01JdVUvODdvSm9reEUrK2xaTXNLcVRqYUNCVG10eVFXdzNpMFBaLzhDZkxK?= =?utf-8?B?NzZnZGFkSjZuZThwZVh3WnRmckxqM3djekZsV2FkZHJiOFgwamR1REtZcFYr?= =?utf-8?B?YlFGeVErMVlVSjNXYkFGY3YwMlRJQVkvbGEvYkJLQ05LUlFuZitMUnFzaDI3?= =?utf-8?B?MU1PSE1xSlljTjZjSktHT3VNY01KTjN3Sm1IeThjdzlVTmg4cXJyM2oyam1p?= =?utf-8?B?dTI5bkZNMUtMMWRuTlFITURWMGJlQk9FMkxCd2E4NnpqT1I2Mks3ODVTSkoz?= =?utf-8?B?MnJYSE5DbERPeVlrYXNTU2RuTlZKYzczVS9PaDUwSTlaK1E5QmM4UnlQYkN1?= =?utf-8?B?a2ZTWEpxVXBBR3YvcFc4L3RpNHRFeUdINTNveUMrczhMNVIwZ2VmNHlXOThL?= =?utf-8?B?eEpuNngwMzZNRzJDL2s4OHlZSFNNc2pyMEx4VnA4N0VCRnRvLzRkRU12cDYw?= =?utf-8?B?V2RrMXF5eCtjUlltQmpYQzFjRE9QSUhtdmRwY05HbFFabFRnbmIzRk9TMTh1?= =?utf-8?B?SzI1ZlFoL0N0bE8wZ0ZXVkhSaGdoTUJ1L1V3MGUvb1h6THlyclI4alpCVkRV?= =?utf-8?B?QklXK0F2OERmakVmVHJUa3BHQUdQWDhwVWtrZGtBVzZBWGxaREVhYkJDQU05?= =?utf-8?B?aHJ5U3FFTGxQbU92UXp4UlRwSlMxMmFGMGRvdStKVzlTVlg3RGpDUitoZkxX?= =?utf-8?Q?UVXpnzuyJ/0ZpKF0=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 882d20a8-a457-4b18-ac8d-08de79e209ad X-MS-Exchange-CrossTenant-AuthSource: GV1PR04MB9135.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2026 11:34:46.6238 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Q4N9LT9NpN96dAIGYoWj/MiCL0WAgZ75CDudeYzZpni+FIKGiVLHlYiOizn5/sKBvEGELD8IFEV2maJeO3N8lQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB7188 i.MX94 has a single LVDS port and share similar LDB and LVDS control registers as i.MX8MP and i.MX93. Signed-off-by: Laurentiu Palcu Reviewed-by: Frank Li Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml = b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml index 7f380879fffdf..fb70409161fc0 100644 --- a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml +++ b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml @@ -20,6 +20,7 @@ properties: - fsl,imx6sx-ldb - fsl,imx8mp-ldb - fsl,imx93-ldb + - fsl,imx94-ldb =20 clocks: maxItems: 1 @@ -78,6 +79,7 @@ allOf: enum: - fsl,imx6sx-ldb - fsl,imx93-ldb + - fsl,imx94-ldb then: properties: ports: --=20 2.51.0 From nobody Thu Apr 2 12:13:32 2026 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11011036.outbound.protection.outlook.com [52.101.70.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0A153537FB for ; Wed, 4 Mar 2026 11:34:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.70.36 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624095; cv=fail; b=bShh2CkpX2nmpLmWigXExdmRBxJWmJ6ZfYBj1looGx0TAVUJK1PrfqNufJYbC2zlu3GlcHToWhq93l/mikTzyIroFWoZAE7EKNvm+LYYvtjMy0Jj9cah8RqI3Xy/Ru1Cro6lmg0Yvm4cBBXulLHjkPkGjv0C3sVvE8E0j9SCilc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624095; c=relaxed/simple; bh=rV2LVDHGlu0wa7rzvS7U62mvcL875UZa+c1FOlIPbAw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=dSx9vEX5xpKcNkoJNHVs4JCPIOXAIAv8O0cFZueIDccLQLMs9aND4fjcOgDFsACadsI8fduEmN4lDWEUwwf8SavMHrmvzK7tf5E5sfUfFdi9iMhJBgAWSczJjx9NGAqrTrNi30+ZimcpvWGhRlsSuB2KPUYnLW344AKd1rQQdCk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=Ti3BLpNR; arc=fail smtp.client-ip=52.101.70.36 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="Ti3BLpNR" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=d2KWjkZWHqbz80Yku879GRwttDapKDMjDg8n4eluOqyhe7lvLoFqRdiEzA8YM6q1S4TVVIlqhb9+0atv3xf/gDyUPiFYrg4V0mi6f6nHzvS75yWs50h3xHSxlFRgBGsQpW+4sRELUZVEQEsiRlIKr9Rd89nSF4GKO6ESsY4w+4Q3K4gJWe2E8k00Dxy4v7jy/lz2jsbVvG6j6WQol2ApP2lzN3yyeNnqZfGBFw1VK/bgWWkU5767ZKJMatVkoHpmQjk9iEkv9sxJTWAK4Cy/Hw8TvYTqvXObPvOsixyGk53WVXpnQjar7p3C5d/NW54ZVOPrQjVTzYU3XOvWFn7GBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QWdCjO0SJm+5xS0VRNeFWFIrAQQtO2QJBM7dLKYc18I=; b=Mk48tz0P8Q2g9IZ6rush5693/YLL/qsVkHQg2ZeOZFKvY3Yre4ICGtVhew8vHQYZZGRseXgnmMpjGgBPwoFAkyYyCsPIlUN4JfR0MBREuGx9DYkhmi5XFrEH7ww6EgTnFTtVTgnkOHErAmVX/3/d+I8rg7FlK4jFsylJoEvcBpCs5924KfK8V71kNFwSlN4+Qybzm3pDShjodMgom08HYYkdN80cA3teHtQ//bBPVZe2LP5L5lnsagLudukSYfkP17uRYFDxIXMedEMZvHCfsyZZ8LjAiM2uxUJNB3O2SjMUihjXRA96317yH4lmOeSHl9dcWL8QX83XlY5uezpu0A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QWdCjO0SJm+5xS0VRNeFWFIrAQQtO2QJBM7dLKYc18I=; b=Ti3BLpNRVcIGo4+qEXKTPCvURUNHJk9gd3ZaCSbN+Ms0hPZ85oAFcHKhE8W1+eTiBr7MxiC00E03/qrEZlHWYpUnkF2rI0ugoWkpiocs7iApF/gWZrWvFctSAYoD870FSug9zcijAMfuszUFeQLjAzgaMFz8WJW63md6kP/vK0x6z+fWEGK39xOTUfLo1d5fmSS2PePTGulIWp3IASWF983M9JTT0kgdggrfY5+RAuyUuPobL11qRh+wKZyNPh5XbaceGgCJCuBz2oW9bpdeBb8xzH/voGwc+tcv4tO6C1ibRkWQuNfJ5UlEudrkVXs+DnQjr6p2syp+hRE/c0BK6w== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) by GV1PR04MB10522.eurprd04.prod.outlook.com (2603:10a6:150:1ce::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9678.17; Wed, 4 Mar 2026 11:34:49 +0000 Received: from GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2]) by GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2%5]) with mapi id 15.20.9654.022; Wed, 4 Mar 2026 11:34:49 +0000 From: Laurentiu Palcu To: imx@lists.linux.dev, Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, Frank Li , Ying Liu , Laurentiu Palcu , Dmitry Baryshkov , Francesco Valla , linux-kernel@vger.kernel.org Subject: [PATCH v8 2/9] drm/bridge: fsl-ldb: Get the next non-panel bridge Date: Wed, 4 Mar 2026 11:34:11 +0000 Message-ID: <20260304-dcif-upstreaming-v8-2-bec5c047edd4@oss.nxp.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> References: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AS4P195CA0027.EURP195.PROD.OUTLOOK.COM (2603:10a6:20b:5d6::16) To GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV1PR04MB9135:EE_|GV1PR04MB10522:EE_ X-MS-Office365-Filtering-Correlation-Id: d9c1f177-1bb1-4885-6b5d-08de79e20b36 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|19092799006|376014|366016|921020; X-Microsoft-Antispam-Message-Info: ftld1/nC4djRwuN+mqmGfgIda6ItROFZuTpBEf2qTwhMTluznxfmGQhVzUe4+VXhACa92rfIw2ei5qJj7Vv/TQFK/YUS4nAX7Isjd0P56NTe5jDOk2EoZOdMOgqimWUZoLcFw6UYvT38aelCW0Xhy8wp1ngF84wKyructdtOGuJAB9RWhXtZSwTVESAtqBFWRfYsYg6l0dE0F3MjBF5n3iUiiMm1GRAAI5KS9Gph0pZUDeiw/JxdRSdGKUnVDtbjL9NF0NDGUYsUR+xf9Edi9PaSwhNzZLIMjfuCmWjTA1Ik8mf4ALlJPm83oStJOXbYSz8XXGft95Tuu10JOGdpozylVFhKLMphWBvOKEhSPRKA85oEy/jBnIYUO1MGu/Lh7ISlVlAQU/athWGyL7UGEO8U1iMZfZM7RGjYenvcUfMke4CqBggSpG44TZJz2drZiSeOq22vI6VSujPBWyurShI03LmZZIscbbvgPeZwBGc4/BHHx8uOL8e79SsLVNaFQWvjlCHCWsCWWg0OW2iByer9e3hgRYuh9K1wX5nSsdvqJbzM+ahowRqHVxuwjHw1NGc+DMPaglWfH6JecE+2T4HXv8uy0TFVwmWAhhCVCk/YOKByd2XmSk6jC4tPeawPqAwq00H+1t2rVyEsFNZ+/HuHvV4N70zOGK7Gc5ObCIpSD2FMj5pxTCVm4RlQBf8cwVdVPg9Zz7MddiqxqF11vGMmTB5JH/83a3mOHC9Nzms7Qcx4gEDVHQxluJ9Zt7D/EjSXpoQ/jK9Vo12tG8S5Nw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:GV1PR04MB9135.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(19092799006)(376014)(366016)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?L28rZmswdzBEcm85ODZkOStXekF4YnpEdWNqL3RGNnFkc1dJT3dJdHY4NlJl?= =?utf-8?B?c3YyN1RwTXF0L0M0c3dYWEgrMTlTZFV3dVd2RVpBcmxNdURNeDI4SzdIVGc5?= =?utf-8?B?QllmK0Z0OXZsRnNGTXZPVGpWTW9KYnVFUGhTYSthamNaUmcvMWZiQzN2N2lF?= =?utf-8?B?S0o4bjg2Q3hIZVFzcTZZT2NUNUF6OHdTL0VtclZoVW4wYVh4SUR0bzNCTUha?= =?utf-8?B?QjFmWFFicmhmTUVLY2ZabWVTaW40MWd3U3JRc3lOd2NyYkd3NE1GR2ROQVJa?= =?utf-8?B?dit2dm83ZFp6UE1kcU1YZk5DLzBQbWFTYWJaN0ljQUZhWU1oTk1TV0QzOE1D?= =?utf-8?B?MkRzSlI1Mldzc21nY2FjaXMvTk5QREp5R2pnSXAvSnZUTDBOZUNxQ2Q5SHZx?= =?utf-8?B?SzQ5VlJiTVk4NndGZUdBdHloaXNSTTYzV1doSzNPRThxMmR5NUgxbFUwN2gz?= =?utf-8?B?ZUxIR214a0k4dmJPTVIrZFNvRmVudm9UamZrcVM1VTF3VE84Y1VGYnk3aDUz?= =?utf-8?B?TFcyQi9qY0dCcEFNT0VEanYvRzlTVTBKa245Syt5bFljWGpNZGVHWHFCZWRl?= =?utf-8?B?amhpNWJnUHlPM0k3eEJhbHpaemhURG9UUVgvY0RCc2cxRm4wVzZMRVFTMlZG?= =?utf-8?B?ZnQrU0grRTFacktEeVloRW5uOWQ2Y216ME42NzVVMXVpak4wZG9TS2wyNFRW?= =?utf-8?B?d3lzbFRnWmRKNVJESFVuZFdINnZ3aUt0azdOTm5IVU1yOTUxWCtpQjFOYnp2?= =?utf-8?B?c2dRR3pLTzd5bVV3SEZoRk5qZFp3eHFNT1F2RFlzYjU2WHVnNDVpOTdzdjlI?= =?utf-8?B?OTA2TGJMSitoOEQ0Nm5RMmVOMDlRR21QeDgzWk9ZR3NLY3REUDVQNnNjYWth?= =?utf-8?B?aE5DeS9JckJvRFJRVFdiQlNYMGhjSXhSWGpvcUZBQ1NDa2pKVmFYdTRPcXhG?= =?utf-8?B?Y0xjRzFXOGM0Y0FLTXYrL0VxSkdFMjAzaFRqOEk0SUthb04wNXI1YjJLQi9C?= =?utf-8?B?c29yKzl0bEFQWEhrQkNxUG1jaW9Mc0h1Y3BZTlR6QlU0b0RBYmxUMTZPdFBT?= =?utf-8?B?ZVJzQ3dDOUtGelk3TlIwQ2hxVHpsOGdPV2h2eWVZWG9RajY4Y0FVaUtFMTE3?= =?utf-8?B?Vnd1MXYwMjhIY2VWNTlvL3IzMWhmQjArb0FQc0h4elBXb1gvWkIvMGNjTTNz?= =?utf-8?B?U2VqUmdvTlp0enZQYWZnYVdZUnBLUVRuL21aejVZOC9rdDBNNjBTdUpMdkFU?= =?utf-8?B?ZXlPa0IvM0UwVHNPWTVJTXZEODhTUWhrNnl2VWRnZDJDR2N0ek5raTltRHFn?= =?utf-8?B?ZDB2UjgyeHp6MnBQYjRYc3R0WlZlOHFKL2tXU29DRzNJRVNEYmU0Q1I1aTU4?= =?utf-8?B?b3pUM1UwWFIzOFJXTytYNFdWVzgvcCt3dVBHb0NkRWRUUzN2RXV2WHFMb3do?= =?utf-8?B?TmVSVXl5SmJCUTA4UlFRSjI2K3lvTkNwKzc4cU40M1V2aFdZelNXUWtRVVp2?= =?utf-8?B?RkNWZS9GVHpaNVluOHA4NnVEWkgvT3dUSlQ4TGc4MkRsUUJSK0oyWWR6WTZl?= =?utf-8?B?K0dUdEU3VDVnT2NVdGQ5dzBlaUNDcGhTcm9tN0xrRkhjL3hMbmFlK3YySUw4?= =?utf-8?B?SjVGd2Z0WUwvQy9yOXFKY2xkdmJDTXJqL0tEdDk5c1BibnJ5emlKSnZMQnBn?= =?utf-8?B?R2R3Y0J4QXorUGpMdVM4SEF5RThGUkQ2cERhaHdoMWRSTkRqWDNDTzM4T2ps?= =?utf-8?B?UEVKTzhlYVhQRXQrem52anVma2NodjN1UTc0alFveVo0d0RFUjdYZVpQdlJE?= =?utf-8?B?Y1F3cWpJamNPZmN1djNaTk9oN3R4VmltR21CMlhrZTYrOGR4aEg0YjNqK2dR?= =?utf-8?B?dWxhV1JJaGMrQkFaaWk1cDIrdi90WU00Q2h3QlByb0Q1MzBxT1FXeWNrc0hM?= =?utf-8?B?bVE4azFJUjY2OTF3bk1udHVQeGE0TzJGVW1nbDVndi81dUFmYkVFanZoL3dh?= =?utf-8?B?dEd0SW1DQXIxK2VkQWlUN3J6VEZYMjRycDZEdzJKVzIrMjluTDVQajdTM0lx?= =?utf-8?B?MkFDUXc3MFJEYy9pOU85RlU4UXJvTTMzTzJ5eTVpTFM1NWNURllZaTZLR2Zu?= =?utf-8?B?amI3Z0VhbzVsSHB6QlhTbjlXeG05am9vdTFQTlcwNlFmU1kvSC9nYVRzV2Vu?= =?utf-8?B?Nys4RHdnaVZGNExEelRzOS9pMWo3cGhkUjVidGNmQStVY1V3eStPaUxoY2hZ?= =?utf-8?B?Y1Vhbmg1RnBPelhUUnhMTUpWQ1ZiRUZIQklXd0MrUWVCSWNFWTNweDZ6dkJP?= =?utf-8?B?VW1DVTZNNXBUNXphV3JhaFhGTmIrczNaaHlhdCtQSUIvd0MzVGdrSC91Mng0?= =?utf-8?Q?CXuHoVQ6eztVN5Ho=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d9c1f177-1bb1-4885-6b5d-08de79e20b36 X-MS-Exchange-CrossTenant-AuthSource: GV1PR04MB9135.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2026 11:34:49.2590 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4rr09NcfkrmFDYy6KtxHhA9I9vf7MQ3dP8r10SVSICY2x2P3AvhPf9/pQ5aM383Yay6Kc4Rwa5NtkTzj4vxY6A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR04MB10522 From: Liu Ying The next bridge in bridge chain could be a panel bridge or a non-panel bridge. Use devm_drm_of_get_bridge() to replace the combination function calls of of_drm_find_panel() and devm_drm_panel_bridge_add() to get either a panel bridge or a non-panel bridge, instead of getting a panel bridge only. Signed-off-by: Liu Ying Reviewed-by: Dmitry Baryshkov Reviewed-by: Frank Li Reviewed-by: Francesco Valla Signed-off-by: Laurentiu Palcu --- drivers/gpu/drm/bridge/fsl-ldb.c | 31 +++++++++++-------------------- 1 file changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-= ldb.c index 7b71cde173e0c..d59f26016de26 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -15,7 +15,6 @@ #include #include #include -#include =20 #define LDB_CTRL_CH0_ENABLE BIT(0) #define LDB_CTRL_CH0_DI_SELECT BIT(1) @@ -86,7 +85,7 @@ static const struct fsl_ldb_devdata fsl_ldb_devdata[] =3D= { struct fsl_ldb { struct device *dev; struct drm_bridge bridge; - struct drm_bridge *panel_bridge; + struct drm_bridge *next_bridge; struct clk *clk; struct regmap *regmap; const struct fsl_ldb_devdata *devdata; @@ -119,7 +118,7 @@ static int fsl_ldb_attach(struct drm_bridge *bridge, { struct fsl_ldb *fsl_ldb =3D to_fsl_ldb(bridge); =20 - return drm_bridge_attach(encoder, fsl_ldb->panel_bridge, + return drm_bridge_attach(encoder, fsl_ldb->next_bridge, bridge, flags); } =20 @@ -296,9 +295,7 @@ static const struct drm_bridge_funcs funcs =3D { static int fsl_ldb_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct device_node *panel_node; struct device_node *remote1, *remote2; - struct drm_panel *panel; struct fsl_ldb *fsl_ldb; int dual_link; =20 @@ -321,36 +318,30 @@ static int fsl_ldb_probe(struct platform_device *pdev) if (IS_ERR(fsl_ldb->regmap)) return PTR_ERR(fsl_ldb->regmap); =20 - /* Locate the remote ports and the panel node */ + /* Locate the remote ports. */ remote1 =3D of_graph_get_remote_node(dev->of_node, 1, 0); remote2 =3D of_graph_get_remote_node(dev->of_node, 2, 0); fsl_ldb->ch0_enabled =3D (remote1 !=3D NULL); fsl_ldb->ch1_enabled =3D (remote2 !=3D NULL); - panel_node =3D of_node_get(remote1 ? remote1 : remote2); of_node_put(remote1); of_node_put(remote2); =20 - if (!fsl_ldb->ch0_enabled && !fsl_ldb->ch1_enabled) { - of_node_put(panel_node); - return dev_err_probe(dev, -ENXIO, "No panel node found"); - } + if (!fsl_ldb->ch0_enabled && !fsl_ldb->ch1_enabled) + return dev_err_probe(dev, -ENXIO, "No next bridge node found"); =20 dev_dbg(dev, "Using %s\n", fsl_ldb_is_dual(fsl_ldb) ? "dual-link mode" : fsl_ldb->ch0_enabled ? "channel 0" : "channel 1"); =20 - panel =3D of_drm_find_panel(panel_node); - of_node_put(panel_node); - if (IS_ERR(panel)) - return PTR_ERR(panel); - if (of_property_present(dev->of_node, "nxp,enable-termination-resistor")) fsl_ldb->use_termination_resistor =3D true; =20 - fsl_ldb->panel_bridge =3D devm_drm_panel_bridge_add(dev, panel); - if (IS_ERR(fsl_ldb->panel_bridge)) - return PTR_ERR(fsl_ldb->panel_bridge); - + fsl_ldb->next_bridge =3D devm_drm_of_get_bridge(dev, dev->of_node, + fsl_ldb->ch0_enabled ? 1 : 2, + 0); + if (IS_ERR(fsl_ldb->next_bridge)) + return dev_err_probe(dev, PTR_ERR(fsl_ldb->next_bridge), + "failed to get next bridge\n"); =20 if (fsl_ldb_is_dual(fsl_ldb)) { struct device_node *port1, *port2; --=20 2.51.0 From nobody Thu Apr 2 12:13:32 2026 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11011036.outbound.protection.outlook.com [52.101.70.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E1B234C806 for ; Wed, 4 Mar 2026 11:34:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.70.36 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624096; cv=fail; b=sRSC2EyYCYEs6V7bS6v2Yoy62wpGXr8Cp4rHbhaUHTXl8a4PYt6yA24Jrwdm6HqyT+HflhvXjAOR35qBrNgM+q3Oa7Czp9ojFoR+IJDFNq7V16k0L0+wkn5qGXP07bQs7hmJCJfOS95rVFljxqm5tNPxYlTPIlBbyKwV9TkP4uM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624096; c=relaxed/simple; bh=M1Kof+SkR/G8Mvn8PzsNJnXcuLT1M6h4wh0hpzYvr8k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=MTvEAqeDrNSzD8h/0+IWl7+E/iN4mifdM1xMYseuviwWh64zr2rBAq6Xga/bBR0FL0oLNvSq+Te5GLb0SmFHb8tLXz3XEoOH642DHsV41lkEm3B5kdcNjVl6H/3V5gw0Y0V+AGzzO3vptexIGuaLAoi+d9yOTM9LBML2gt2B5tA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=NTgP0Ck4; arc=fail smtp.client-ip=52.101.70.36 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="NTgP0Ck4" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=l8MIfY0QaeExkLeJKEKzDjYvUpINaRSK35DPA3EniHXcDRA0EuiOKq6du1TvortU5fBzJucbRrUgIL8tS8Xn/83dPWvW/N2Emt2XcM20TvOYmLfcvqxvPykIXXXdodeX/EGu22jG+3NVuc2HqlaaWo3tgwcWBGNDk8/kz86fSYoWnuWX+DIO7M4PW4dt5xxwi4Kqdn5XbTwRozAcCXrIf/3SpC7b6T3LxCrBOQvWfJcTkAcDak7nR5L/L4DJApTHwqalMzwKsBvvVUa4N1bmREB4etVitnT9/F2MjyjWuz1xX4gyRUsnk+jL0mo9o46c4OeEcxhQwKPkM8ILhCpsdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=SNXG+ait2nZRsSrx3nzG2yAV5zGXsK+gK6cL6TLSDuM=; b=S3/ngKzoDk7iK3FBTVTpqO1dN2K9CIXotd1R0KXny43y0STnHEPv0XCC5kGCn0kuZ/rTSFMrYFvyNG9bbkyngyz8FU+ef8ydBvwgwllpjCmz89XDEKiyFWqJ+Xs/VH1Qir7erMmB6o9z8m/wXTdXufGlaGf+cxqj/q1p3Sxgs/yliZkDOreQbqh+VeAbXccgFGSVOO5nrvBh1u+XZtFiOxLn9D4aPnOfLB/B2RVsv3+SdO7gq+NtiY7hGQTVJ4K7R/tOJm/lwGWFXgjVb2UgoxAUokj52/ffnd9GAGGdiw83XZ0a9qqZDw8J3ZR+iJLQD/i6DITTBjJBq8IXahhYnA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SNXG+ait2nZRsSrx3nzG2yAV5zGXsK+gK6cL6TLSDuM=; b=NTgP0Ck4TnGSSiRXIxcXR8tUaLMX3aLli65WFyDzq9dtx9H5A2ZrQa9Cf+Wf32zDAmqdajjRZV0z9tSCBU7jBpT1g5d/tsAqB3YdwgMvkzxxSuqUpltIGVcSAlmJ7IbOkpLKFYeVE0LFMuuM1tsTWoBecj+Kbv9BXQt6MS2d43wEiC+33Oq3ZhqU7RXRwwErlnH77pWSXqszyLM/OvrStRp4q8PKNa/l8SOfN4V9P+XQPHs3/LKRTqSlki3hHBj+wgBe192jl0CDjb6XBVeJMgw8f1Ehi0+CPxvc876NcTTQlUCpD9ffN1zpkeTmRwC/wpFUsONoxWBX5iwdP+LFag== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) by GV1PR04MB10522.eurprd04.prod.outlook.com (2603:10a6:150:1ce::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9678.17; Wed, 4 Mar 2026 11:34:51 +0000 Received: from GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2]) by GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2%5]) with mapi id 15.20.9654.022; Wed, 4 Mar 2026 11:34:51 +0000 From: Laurentiu Palcu To: imx@lists.linux.dev, Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, Frank Li , Ying Liu , Laurentiu Palcu , Luca Ceresoli , linux-kernel@vger.kernel.org Subject: [PATCH v8 3/9] drm/bridge: fsl-ldb: Add support for i.MX94 Date: Wed, 4 Mar 2026 11:34:12 +0000 Message-ID: <20260304-dcif-upstreaming-v8-3-bec5c047edd4@oss.nxp.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> References: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AS4P192CA0047.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:658::19) To GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV1PR04MB9135:EE_|GV1PR04MB10522:EE_ X-MS-Office365-Filtering-Correlation-Id: 3473d6bd-34e1-495b-3a6e-08de79e20cc4 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|19092799006|376014|366016|921020; X-Microsoft-Antispam-Message-Info: G3LDiOWNYeLeKWSKTgWDlvvFLWz1EnC+6WXHmHS9gQ79189cJTfFoKHVzES829eravN0GHIheMekcEQwSJ4R35PNGuCKAy1JRWEniP95kUT2H6rPvud5/zIrqfq/UajtFnD0UO9KZaCmV/rzYSLly7HEEIPM74GcgdPYjEwKuXLj/bSerpX7J9QsNGedP4M3jxHpD+lgXs+SoRwDDguXOu+16mBWpA21W3zjgcxpa/SquJZlTDB+DrPM6g+Cv7tTKi1VhBJLebgZ8/GFXpVhxpeWS9W1K9S5gwX5uQ2u+ubZ8DEf/eOjHal7Wvewlqt0qvLM4mEucMR5UqYKafqOvxK0unNDs5YhZ1cdOrRhXgARngPfTJsz00Q9T90iwv3gv5vRD2zFwsFG30ZPkF91nX0+NrXc+E5SMnsubjCbWuacQ509WGZuQzvfs8E/F8BVkPCRNJ0ktgsGfRtoXAPgHwSMyLKgYBpqy3rz88N1gp+E3Ob2e18cCeA2rdXFrxjM36gRbAf4c1bkUATc/ebB06UnVJAaCHspSyigq0K4d8ZZa3yq3rEb6raGJdqXppGlMqp3D8gB89SHE159mjJxYOkwSn+mWm2hDpLRK8eAkamM5UH1z7Q0paaMzK1rpF+NhE1TH4n80y7hk2tCPGh56qK16ftaf60YheCe62o3VGeRHt5t7VoUyp4sSZd8997mLcU5d9JPzP9ZWEBK4fsB9/a3gymAYrAJVeloxt19Ek4ZLdqqgkC8dxgoPkgSulfhrsikTmHq/eE9qZPfEC5Wzg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:GV1PR04MB9135.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(19092799006)(376014)(366016)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?UjI4eXZOalpRSmFVcDA5aTRWb1VRUTRMU2VjcmxXN2dDT1E4SXozRUVqRkZQ?= =?utf-8?B?Qk8xSkJUN3N1SjNaZnh6TTl5VjVlMndRVDM0UE5OM2xlOWdWelg4MWVSNUw0?= =?utf-8?B?OUhaS3J3Q0xkRWVPK2ZCYXRkdzBIbHFUa3JIWHVzNGhGcGhFSE95VmZlQmVO?= =?utf-8?B?ZktSRGh2N2xQdTFOeDhCK3NoNk5YUUJCZDlyVU5GWDV0REdvSzVZQ0xTdGJq?= =?utf-8?B?anJhY25jUjcxc2ZTU2ducXcxcmIxNkJOeGFlT29GbWNnWVZJUUxYbkF0VEc4?= =?utf-8?B?aks0UGVxREE3NUhycGJpdHlYN0xBYlQvV3FIdlpSN2JjMnNpL0ZIRUplbi83?= =?utf-8?B?eGtLb1NaaFp1TGZObzc5UW9sa2FDWUVQd1VvT2F6QUd0NkhNRVlaakhlV3JZ?= =?utf-8?B?ZCt4Y3EvalVpZUpUUU9SQVlJOXFLV2RDRjRLeG5BaXNwWWwyQ092eThpRWF6?= =?utf-8?B?ZmxtY3NMcmd6UjdtOXBpVDdBb2ZQS01LMVFKMzZqc2FiUyt4MHYzWUNhRnRy?= =?utf-8?B?cU1ORTMyQkNNVEVRbkFKNUhUSG9SZmcwU1hnV09wblppWnAzZFNSOUlmd2hJ?= =?utf-8?B?Ym00QkYxZXRXdXVESnN0S3pNcFEyNDFvdjMwdnNOTVFFYU9oVC9uN2hQUEZ4?= =?utf-8?B?ZzFEeDBsck5HUkRYL0hlUEtyQXV6MER5R0NRUU1HeDhvcjczdk1IUmtIT1Bn?= =?utf-8?B?SkJBb016Rk9IMG5IWE1ubEtqWlBUSG1ONjRSS1Z6N29lWWlwQmVvcGtzNWta?= =?utf-8?B?UWtnVnlXMDNFV0F6b0hBeGd1RnhDMnhUVnpGSG1oZEIwcEdFa3RqbVAwMzE5?= =?utf-8?B?VTdZcVNwWkhtcnRxWlQ4cytGRjZ3aTF3aWY2MTJQaElkVDFFTzVIZWlvVFVq?= =?utf-8?B?R1lsSmhyZDE0OHBXTHlhVWw1dXg2enR1WEtVUm9tbHc0dGxxdUt3QTBwT3JH?= =?utf-8?B?aEJ2eVdpaWlHQS9aQS9uakRIN1dsN2tXZmw3NjcyZHF3YXFidDByaTFXQjdr?= =?utf-8?B?TlZTa05BWVRyelZvdmlvemttZllXY2dBa0lrK1VkME1QVXZwUjRJSE5IOStv?= =?utf-8?B?ZUZUTTNJMkFGL25RQ2ZIWDB0b3hqQWdFSWM3Y29DaFkrWDJLY1RYTUs0c0J6?= =?utf-8?B?VFFZL20zU1gxbWQxYzJneGdQb09CSDhaS3dzMUd4VnZneFcyQWlmOG9oWFEv?= =?utf-8?B?NXpvaUVhTWNpdm5uamZnWkZLT0dMOWU1cDZhZVhGK2dLVXFlZjMxUW1ObGs2?= =?utf-8?B?TkNCT0s4SUFYNGpmZmp6VFlqZ3RTN0N4L1lCbExrc09DYVhKZE9iVEFRUzY5?= =?utf-8?B?ek9nRVVxREFqZldab0Q2S04wSTk1bnNoQkFJUFEvR1AwclUrOElRK0Ywblo1?= =?utf-8?B?VUlicFFxV3ZvaGlsc0gvZ3BpOWNYdUZQcjhGQzZjN0crRkZ5aWMwelBXUXZy?= =?utf-8?B?VzNXMTJYTGZZQ2Q1SzEvdHFhYisvUGo0WklPVzZnK0VjelMwcFcrd3NFT3Jo?= =?utf-8?B?WmNZT1RjeGd0clRhOEhTZmx6WGpTdmxIcWhoNDRxTmMzNHcrNUtiSnZFMjRI?= =?utf-8?B?ZUVveHBZZEpmZ2c2bWcrb1doVnY2bkF0dDByS2QwclhxNHhQbnliZlpuTm9M?= =?utf-8?B?TDZOd3ZUdDNuMnNjS1FaTzVxVnRhTi85Wk01MER5OFcxdG1zd2F2ckViS0Y0?= =?utf-8?B?L1V6VGZhaHJDTzI3UVAyZ084aXM1ZUtrd2syYmFDcGdFbDN4eEYxaWFPRUJJ?= =?utf-8?B?VUxNTHJRYmI0NXhSODdZUjIvYU8yWkpVYks2OTUrelh4bVlTZlZCMmNFYXlW?= =?utf-8?B?SmV6M1gyenBSWm5wYUJ0Y1lNZUhIOFNYcjJuTVZHQTE1M3VnajMyN0hZYXVn?= =?utf-8?B?WmlWWjdFbFlRM2NTalNQUVAzZklTMFdYek1YczhocnpHUFZLend5R08yMGlU?= =?utf-8?B?UzNLQVlYaG44QmE2VndsekRHTDlBUVY2bDEwRU5RaWgzRjREaXFuMndvVTZ6?= =?utf-8?B?L2J1VWFkVjhrOWNVNE9GWS9FVnpVdWFwZzBpSGM3cTQzWXNTbUN5d0ZqbUp4?= =?utf-8?B?UXgvSjI1aUtKeHRYVVhVcXQrRjg0NlJXT0EyNE9aMGUzNkY2aDJOcXZHaEta?= =?utf-8?B?cEE4OXBCQ3l1Qnk4UlpvcVR3WGlrMHIrWU41dUNtcnd1ZVlFYVRRb0Rpd1Vq?= =?utf-8?B?NWlGVndXZGFSbVpZZ3NaQStuSW9OZHBUOFlQNEJkWUJtT2xXbXlHZWJkeXdD?= =?utf-8?B?T0puTUNuUjlxRTg2VHowMXhtUzF3cklIL0JGcUF1c0NybHJadmVBS204K2FZ?= =?utf-8?B?QWVZSlZIM0dtUU1RZkxlVzArN1AxVDBrREoxNXVnTGZvNFVBcmNGbXo2WWs1?= =?utf-8?Q?7cq7GZ6A76xqmmzQ=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3473d6bd-34e1-495b-3a6e-08de79e20cc4 X-MS-Exchange-CrossTenant-AuthSource: GV1PR04MB9135.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2026 11:34:51.8539 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: e/+HfGPNOOb6Nrvolbta2Ir8tJ4k7ruWXfb2ixSPBXA+up02jYNqe0xeqcbgyY+3mfWMAgUmLP3fPg7mStYXbw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR04MB10522 i.MX94 series LDB controller shares the same LDB and LVDS control registers as i.MX8MP and i.MX93 but supports a higher maximum clock frequency. Add a 'max_clk_khz' member to the fsl_ldb_devdata structure in order to be able to set different max frequencies for other platforms. Reviewed-by: Frank Li Reviewed-by: Luca Ceresoli Signed-off-by: Laurentiu Palcu --- drivers/gpu/drm/bridge/fsl-ldb.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-= ldb.c index d59f26016de26..1b8f65a817a25 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -57,6 +57,7 @@ enum fsl_ldb_devtype { IMX6SX_LDB, IMX8MP_LDB, IMX93_LDB, + IMX94_LDB, }; =20 struct fsl_ldb_devdata { @@ -64,21 +65,31 @@ struct fsl_ldb_devdata { u32 lvds_ctrl; bool lvds_en_bit; bool single_ctrl_reg; + u32 max_clk_khz; }; =20 static const struct fsl_ldb_devdata fsl_ldb_devdata[] =3D { [IMX6SX_LDB] =3D { .ldb_ctrl =3D 0x18, .single_ctrl_reg =3D true, + .max_clk_khz =3D 80000, }, [IMX8MP_LDB] =3D { .ldb_ctrl =3D 0x5c, .lvds_ctrl =3D 0x128, + .max_clk_khz =3D 80000, }, [IMX93_LDB] =3D { .ldb_ctrl =3D 0x20, .lvds_ctrl =3D 0x24, .lvds_en_bit =3D true, + .max_clk_khz =3D 80000, + }, + [IMX94_LDB] =3D { + .ldb_ctrl =3D 0x04, + .lvds_ctrl =3D 0x08, + .lvds_en_bit =3D true, + .max_clk_khz =3D 165000, }, }; =20 @@ -275,7 +286,7 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge, { struct fsl_ldb *fsl_ldb =3D to_fsl_ldb(bridge); =20 - if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 160000 : 80000)) + if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 2 : 1) * fsl_ldb->devdata->= max_clk_khz) return MODE_CLOCK_HIGH; =20 return MODE_OK; @@ -384,6 +395,8 @@ static const struct of_device_id fsl_ldb_match[] =3D { .data =3D &fsl_ldb_devdata[IMX8MP_LDB], }, { .compatible =3D "fsl,imx93-ldb", .data =3D &fsl_ldb_devdata[IMX93_LDB], }, + { .compatible =3D "fsl,imx94-ldb", + .data =3D &fsl_ldb_devdata[IMX94_LDB], }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, fsl_ldb_match); --=20 2.51.0 From nobody Thu Apr 2 12:13:32 2026 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11011036.outbound.protection.outlook.com [52.101.70.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AF8536607C; Wed, 4 Mar 2026 11:34:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.70.36 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624103; cv=fail; b=PXMU9TCzSazFsRn/ZUbLhB4k0V181oOpNLGuQPeJCDZwCzDdrtwrEFhddz4RT6ZroKd0AW8LGxqaivlbCSnr/X07Xe7ZcvVIUUxaWJXZoTmMR0ul+8bxofkZ87ryjfaLA/HP63+MgRnsDrq6Kli31Bv7ggFXgAuOefC2eHHTsAQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624103; c=relaxed/simple; bh=kQmuZdXF4HIGtfSD28tvBH9GcCt+IMCjkH4l09t9/Dw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=pDTqz5hlZF227o8HtknU0CgNRQCGQbA5nz87MQXtB3HQrZBZG13R5K+fKTsdOvbwM62kWlfMc5LcgKxAHv+tBTbwAIbXTnVyK3+J/ErBJyYQzUA1ObsXBYBZzgWtNAhZI8wPWo5ZhVuFc8A5jJmDkQBoj1pKgCxhYiINHQRC9YE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=BMPLsKde; arc=fail smtp.client-ip=52.101.70.36 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="BMPLsKde" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=YRvpPQOBHxf62XNAWxotFRRyZgQGs+MuKhgUdSxxWx1UVrYoSG0iP+CDcLLru8g8voWc+JTQrZiMylyCJsdMPnck4lEJos0tmQ0aTHgmvWCQFyA+Vut5dl3hcGRaY+4mzuSOR3r9Xcab5OfEGnQ1HM6ekJvyV7BkYzdu9obOAXXOO/4x9MfoU4MbOQFf5tyIRHf8wwYe9qrPUG1WeQ1eAAqo5baQPHOiwdDBAlMRrm73Hxnsm9iFNp55ruVMoyCB0Pi2zRr9GP9fxunbrCw7SXpZ2tseuFgB3ufFmkL5/hyVExG0T+hWdUFs8We3PwePeG8o16Ql2h9xD5n6N1lH8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+SvoUIV1vrrnj54TCf/SH4TMhaZacQZY+lg/xaNaxyE=; b=SPsRrl3ouCsiXT++bZVBfvS/9YGHzOW2WW5w6dNUI3Xyly0SJ1+h5iFeh1TjkHePN7KusJUFFqKWqbzKTvFL3H1hGPXNGbWpLgH+ZFacLJ4yhspW7uxnb8fWxAiqaYpaRvFuyL36RqD333SpkrCW1ZWDMHX9yJrkd+fKZ6dADwPXseCkoWPDKO8B311XiqRZO3ZrP3uSgAeORcgmAAAicDgsdCoUTf3H/Wi87HNQeaYW23bRHdMTP5c6RhCYyUHnsD2l0GurgK/Fy2sambwIc6iU15/CWgCricV6cqOOcxGzKjXcqCH7a7h7V1njihTKdfaIfvZzrt5x371azh6jpg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+SvoUIV1vrrnj54TCf/SH4TMhaZacQZY+lg/xaNaxyE=; b=BMPLsKdeKjuH+5wrNNFnR6q1M3vaW50ERQ9YerBFGr/mZ/BewcbMdWHC6lLkU8ckvzwqQLkPA4Gud4E2l2I6oupfGuuwrfASHMpJb5T0E3iRTIIrlGA8HsAi12JjpvD0sKXU6kLvI3szZXwIaa/wv1phmsnupemKkbRAFaEsmC4L8sLG5qqSZxwLNwjqnsVxPRYFyFSmi7J7nKi/2EDckwDKZNNlawqCpAK0WzXiFD1xd+hTqrB05n6sghcHzg7ezGuS/UzEi57Zao/A+w6NSKNrDbJ7TSjOLCirPhfc9Hcs/1rhB8XctbnfzHEplKKdwSd3xtipLaJgFEBkJuVonw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) by GV1PR04MB10522.eurprd04.prod.outlook.com (2603:10a6:150:1ce::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9678.17; Wed, 4 Mar 2026 11:34:54 +0000 Received: from GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2]) by GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2%5]) with mapi id 15.20.9654.022; Wed, 4 Mar 2026 11:34:54 +0000 From: Laurentiu Palcu To: imx@lists.linux.dev, Philipp Zabel , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: dri-devel@lists.freedesktop.org, Ying Liu , Laurentiu Palcu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 4/9] dt-bindings: display: imx: Add i.MX94 DCIF Date: Wed, 4 Mar 2026 11:34:13 +0000 Message-ID: <20260304-dcif-upstreaming-v8-4-bec5c047edd4@oss.nxp.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> References: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AM8P191CA0020.EURP191.PROD.OUTLOOK.COM (2603:10a6:20b:21a::25) To GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV1PR04MB9135:EE_|GV1PR04MB10522:EE_ X-MS-Office365-Filtering-Correlation-Id: bd76fd06-dc9a-4d26-5106-08de79e20e65 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|19092799006|376014|366016|921020; X-Microsoft-Antispam-Message-Info: I9RiuGOvlnXgOMymv/kG5ruQ8MKBq7zJBuq/7gxxTOhsJOR3zXJnBRpRpwpCmA9PpaxF39tml5tbTvOp2S21XMXl+/EhNNaJbZp1ncl5lxcMoC4sjUSGDeIKrsvEC6AKuVfg8lJoBb8w5ge0gBHsmuyzr4IACljr/l6HDgCMbFdQAEiYQjukLBHhePFKgbA0bXzV/XXnJJkd3YmJXFZJUGh1maX2LSTR6fNdZM8juwVM5UbVnFG5mMIJUsUlpHARCtmRuQJGvpdreokrS+ZmGeng2oLc4jsWaitIOmnTlSnzp1U81U/U4iVYS5a8wjEfk3LFPJNDfLK6S47e+CboI97a463OTPG//UXef7BBGCCxriAjyzBtVyybHabA+LvK1x/kzmChn9DqXpStEEbtHq8izRITZpTdl8lVf2E7YP08FTWBsePlWNG89xH6ShWRyon2VIQ9fgIPIIzzLz0Wx7FcxlyL8FLpVIZv6PFK+2nbhIYWWCoKVop66cy1NC4N+cApaeCANJma0D/DmVgLC/GLtlttphre/mBS6YyHYNwVsHoyUMg1kbTtoC4reP7EcW74pfth1ZDjfTBw3+qJRihbX54kU8nImKOz3ICWmga5adkCdDmEKDT4roGPUQBPyG5ilg8kR1eQC5SpzEXY/nhAbPEjpSmXpQmsS/n2CUtomvtC6zCBEJNMcIkgqxUUGOQ/yKW1NrWgH/uAEchoZ4sXy7NOTKwpNxfZlRNLsxDeLQkIDrXjre/MA5EmhBy1 X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:GV1PR04MB9135.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(19092799006)(376014)(366016)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?N0pkdWRxUUE0cklscERmamNkR1FFY1FXZnpSTXp0QXhOYk8zOXdZTkYyRXlx?= =?utf-8?B?bnQvdjZWdUpjWmhqUHFsd0grVlh6aWQyckhCY0E0U25iQjJESTFoUHBuN242?= =?utf-8?B?US9aZWVuRUdSeUVyam1UNzc1SGxkS0JNNWJYNFhpWmNvSEZtaEN3bWdYVUNS?= =?utf-8?B?bWdlSXd1em91WitIcnk1dDVGNWprRmZJeDBrUG5ZRnZHdmtBenE2ZnZrVVRu?= =?utf-8?B?WERNNHR4QkpMRWQ4N1hibTh5bHBxOWhZRDBlMGZvZDRBeWoxbGdTYVMyQklI?= =?utf-8?B?TnI4c0lJWnBSelBCbWx4VjQzaURVRHEwdzRydks4cVlzYVhyZmlHUHRXNGNT?= =?utf-8?B?Z1g2bTkyZVlraU5JMmhZenBIbzJITVhqU3RaSEdidUNPYlFJdFZWKzA2RDdU?= =?utf-8?B?VDhvN1JjYzhpTTFiWURaVXdBaVZnUnJVdW9QMVRiOE1MTDhjTGg4TzFmWVlu?= =?utf-8?B?NXBUNzBhVjR6cTNFbnZQZzNnanpyc0d0Z2ZUaEVKdml4MWM5Qzd5NkNrWVhx?= =?utf-8?B?OHFwSnJlV2ZmZWJVVkZ4eFYyMVNsMWJVaVo1YTZtcVFsanpsQnh1V1NkbWtl?= =?utf-8?B?c0FlS25DZ0ROVlc3akF6SFdSTzRpWk91ZU1zRCtiYjBNc0hkcEhMRVVWNVBy?= =?utf-8?B?MHZuZ3JVT3pFRnBXMngxOUEvalBzdld1QVpveVR4NVR4WlZEL3l5S2hrVVpP?= =?utf-8?B?alZ4RjJuZlhOd245bXdRMHdtNGppMnkrZS9CK0RpR0NxV2lteXhUdWsxQTQw?= =?utf-8?B?akdueFFLMXJ0ckdKRHU4bWMvZU51NVdZRTd5eFlSdzYvdWFvNU1GV0dPWStQ?= =?utf-8?B?Mzdmdzg0dXlZVzFPZWZNMkM3STFGZXBtTkpwYmpGSFhZcndISUpkYUJPN0c4?= =?utf-8?B?YnBPUVVJenArRkxITWJyNng4R1czNVVENUlKby92elZqR2tWMmUwVk5pVm01?= =?utf-8?B?cXpnVTNhZWNFb0xzZzQxS0gvNTY2MUdpV0pFM0hzMHVGNHduWERsVFc2bEdW?= =?utf-8?B?WlFxcUI3RW10TjR4Q3liQkZaelJxUExhQjNRYXdNQjdNYk1qZlU0bzdQN29W?= =?utf-8?B?VVZWYnFRb0xENW9PWm9XbTM0SXk1bjU1bEJZVVNLU0o3M250VHBHcUtZZ05T?= =?utf-8?B?ZDdBT1YvdlpKV2l4WFExZy9ESzVMWnFrdFNDVWFYdGxLQ0VBL3hjSTlnSVNx?= =?utf-8?B?QUgwMU5ObW1iMG9pVXM0TmVuOFhzTWxHTGs1a0lMeUpSOVRkZlhWajRWSjky?= =?utf-8?B?OEJDMUVFb2FzaE94R0dhUjlZNzM4K2tDaitvN2Voa1pNWXZKdS9Md1Q3YVZO?= =?utf-8?B?RUZNZThPUDI5TTJkSExUOTVzUSsvWUFQQnZlZkZwNTBrQU5GVERKMm9abUlW?= =?utf-8?B?RFF0TmVOZDlLaTM0dnAvLzVCWnFPeEF2aDBFM3dHZ0xmaHJiSUxsSERVakQ5?= =?utf-8?B?L1FGMm03R1Q4MWpwK1d5TUxKa1N3dnR3NDVkL1hheFAvY1V3eVlRa05mbDdq?= =?utf-8?B?SjJua2Q0b2ZpZjVsb2NSNEc2alBkS0h6c0xKdGpUQTdvN1kwMjJwT0hRcEV4?= =?utf-8?B?YVdRS0dpMFlqVFc2bENXcU93OG1leks0Ym5iNXEvTDUrUDlVaDVZcWhPZmdq?= =?utf-8?B?eGpMZ01ydmM5VC9MajAraFVaaXhBTmVvOWZKeHIwTkdudEYxak5ra0dYT0Rh?= =?utf-8?B?Q0xzaXhzTXdQMXUwQWlQeHcvQXpGTnJXOVFwcDJQeEpYRmd4eEZQb3hXT2JW?= =?utf-8?B?cngvYUlmdkpEUmowMGJrMFc0cmZHU1lkMVZkS1pXM2JldXVGM0kxaXMxaUU4?= =?utf-8?B?OWNwR3FUR2NvWUlnOXgyeTB4My9pTjRBbXVoZ0JJVDVtcWJnTm51K3dObUdj?= =?utf-8?B?Z0JSU0E1KytIdkVOelVFRFdiTzEvZHJsSkdnK3BrZEdFRFpZaHRubmF3VDBX?= =?utf-8?B?TzhnVDhYVkpBL0k1UzBGS3A1YTdmeU1CSkZCTHgyNWZoMGxBcW8rTkNKdlpS?= =?utf-8?B?ME90UDFaWDhtSGd4L1dnSTFzc29lcXFWQlhlME5aL01BQnA1elY2UlpmN0Ew?= =?utf-8?B?SmNmbWRIUUtwdWZQUmVEckR1VXozQU8wcVZtOS9oN01lMkhUZ3kxR0FENHpT?= =?utf-8?B?aG1ZMTdMNXV0VHgwTDE5SjlRU0VtR09CQlJKVitEM3FUcTErTVNuSTBraEho?= =?utf-8?B?Tk51SENpL1h0K21WVFBiaUVvRWFmUk9QN1dzay9ML05RMDFWdVh6cUpLbno1?= =?utf-8?B?ekJvSTRMNHdIS0xaTkdPZGpIeDIxUlRjMldMV3Ywa20ySVVZRVN2ZGdDZjJr?= =?utf-8?B?NlVrT01pWktYdjJXNWFNNFRnbWY3RWI0ZFNQNUduM28vNzNRbzZYbkhEeE5s?= =?utf-8?Q?YuISVpkYyW4Nwakw=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: bd76fd06-dc9a-4d26-5106-08de79e20e65 X-MS-Exchange-CrossTenant-AuthSource: GV1PR04MB9135.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2026 11:34:54.5497 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: B1AzXgdaki5dykuYNVpsBwG3SNGhCpHrXTwywOyuOp/aNWxY/CPDpjNPP/cFdmxDgPnV77XhPa1xH2wiqJGPjQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR04MB10522 DCIF is the i.MX94 Display Controller Interface which is used to drive a TFT LCD panel or connects to a display interface depending on the chip configuration. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Laurentiu Palcu --- .../bindings/display/imx/nxp,imx94-dcif.yaml | 82 ++++++++++++++++++= ++++ 1 file changed, 82 insertions(+) diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.y= aml b/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml new file mode 100644 index 0000000000000..fb25300e25529 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2025 NXP +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/nxp,imx94-dcif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX94 Display Control Interface (DCIF) + +maintainers: + - Laurentiu Palcu + +description: + The Display Control Interface(DCIF) is a system master that fetches grap= hics + stored in memory and displays them on a TFT LCD panel or connects to a + display interface depending on the chip configuration. + +properties: + compatible: + const: nxp,imx94-dcif + + reg: + maxItems: 1 + + interrupts: + items: + - description: CPU domain 0 (controlled by common registers group). + - description: CPU domain 1 (controlled by background layer register= s group). + - description: CPU domain 2 (controlled by foreground layer register= s group). + + interrupt-names: + items: + - const: common + - const: bg_layer + - const: fg_layer + + clocks: + maxItems: 3 + + clock-names: + items: + - const: apb + - const: axi + - const: pix + + power-domains: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Display Pixel Interface(DPI) output port + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + +additionalProperties: false + +examples: + - | + #include + + display-controller@4b120000 { + compatible =3D "nxp,imx94-dcif"; + reg =3D <0x4b120000 0x300000>; + interrupts =3D , + , + ; + interrupt-names =3D "common", "bg_layer", "fg_layer"; + clocks =3D <&scmi_clk 69>, <&scmi_clk 70>, <&dispmix_csr 0>; + clock-names =3D "apb", "axi", "pix"; + assigned-clocks =3D <&dispmix_csr 0>; + assigned-clock-parents =3D <&ldb_pll_pixel>; + power-domains =3D <&scmi_devpd 11>; + port { + dcif_out: endpoint { + remote-endpoint =3D <&ldb_in>; + }; + }; + }; --=20 2.51.0 From nobody Thu Apr 2 12:13:32 2026 Received: from DB3PR0202CU003.outbound.protection.outlook.com (mail-northeuropeazon11010027.outbound.protection.outlook.com [52.101.84.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37472371D1A for ; Wed, 4 Mar 2026 11:35:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.84.27 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624109; cv=fail; b=YOB92j9upStzhDrKjB+p+OfbWu153wBdoMV73fTnEkfbI/vyyXh0h2oJ6m7g7FHNtR30v7gJRQWgGijB3wf2ijeNXP8BSarke968F3L/eO+duDtpMbkIquw+ZNMpLnnpXrmNGDnQmH05Qipb+3mVdQTrPwTiDGn6sYsvUtO1Pgc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624109; c=relaxed/simple; bh=AKkGNfp86MPJMKJjEggyFOESF4PcYC/309rEa29Tum8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=k8ums3ES+orWyTWY0cq+TrcwyUhk9PXF4q5dcnfHwM68DtDJfOYZaa75+z6dCoKorc85DkxVZfvYeJHg+cJ4NNLdnPRClZB0jTslsEEFtRijYqrsSrMYg4GNUQIWpAXE4VSr/yKGcx0cuuqMTpHd3YTXQjaAFwEY1oNG9C1RJs4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=Uw8cQ4Fs; arc=fail smtp.client-ip=52.101.84.27 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="Uw8cQ4Fs" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=QrSs/zq4GuTN+mxVfpzF5TDm+Sjqf5b0JpNp0p0ZQbYxqwFZwkWz4Vex6tJdUGk90sMY3jJVkCdN2oXPNKETGd45umQspmI1K9Ohxo2Z4nrP0MwJvgh799MnXdhia8MgJsqLqm+QUsRwjhpSDJ+ZSEEDTFiptSz91jTij9dUOY8M8RGIEznFfumA4HslIqfAUOeMK5RX4Q830shwD7298dIncGgWeBQjL3jJwZ5D7P8GrBETF4zfUZ/ua7SjqTrmMc2MazHTa0/CKSAElEdNwKxBKLvQtaI1SwDh6PUrnqB60IG7klxJhGiicMVKqMI0B3vDu6h5eEXY0yzrbiXTMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=RK2Qv6MpRObBG/rUzHbcSayjv4srFavQsjmb96lz3ZU=; b=P9wXbQy5hOaXVRhA/2qqNGD3ZHsAFDJOUrdCQWwUxksa4iSQWzNm47KBDhvLzgk9ABfM2N3XcX9g55EpX4KU509Ww+SKWYgkbYPlu0RXLeLHMM8jrHodtOoBaPeVJ/hgs23WdWy16nhYFhAUpj212NuJD9E2UflRH8+v3cuOxemH1ExGD/bYQThVJa5UQ3klikHpOCE+U4cah4/+RpVc2dLKcR/52G8FQ5V2aQhaBHA2VuXPD3XHcpYQzItHvpSfZJkgAiMlXLYJwpItR0C62WAPfmRz/7EdSyNoTlhttTNAHkasLFKnm5rd3+jODtmo0R+Q20MO9PqUjx70rfwwQA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RK2Qv6MpRObBG/rUzHbcSayjv4srFavQsjmb96lz3ZU=; b=Uw8cQ4FsWZEMltVs10osJWrujabHKC17CW/OVqNBA9oAU+oWAdmT9q3m74jrgOxC/L7612frBmNJrdwmA+g8igyVJt8khHm48MVmW19yhCf5+usEdIDYU3X3t+sUv5hJDvc6b8eZIlmyyvB67FotbNq1D7KL5ZYxl2jkUWH900qA7Q4DiMr74lLWoXTVP8hqIeX9HLeVwoAHRK1I+m3nfvD3RAxT2mV/pyrOQO45re9pyQV7gCcdjkgKoHvgRWJGI6IJ50GEP5wRzMYuSls0L99HCGRKbT32ruCWVgbttKWeUFL/q+D980JMb5nYWjdfVMB3R/uECPGEuadf8tm8bw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) by GV1PR04MB10522.eurprd04.prod.outlook.com (2603:10a6:150:1ce::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9678.17; Wed, 4 Mar 2026 11:35:01 +0000 Received: from GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2]) by GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2%5]) with mapi id 15.20.9654.022; Wed, 4 Mar 2026 11:35:01 +0000 From: Laurentiu Palcu To: imx@lists.linux.dev, Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: dri-devel@lists.freedesktop.org, Ying Liu , Sandor Yu , Laurentiu Palcu , Luca Ceresoli , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 5/9] drm/imx: Add support for i.MX94 DCIF Date: Wed, 4 Mar 2026 11:34:14 +0000 Message-ID: <20260304-dcif-upstreaming-v8-5-bec5c047edd4@oss.nxp.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> References: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AS4P192CA0049.EURP192.PROD.OUTLOOK.COM (2603:10a6:20b:658::22) To GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV1PR04MB9135:EE_|GV1PR04MB10522:EE_ X-MS-Office365-Filtering-Correlation-Id: 711db806-a4d3-4a89-8c99-08de79e211ee X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|19092799006|376014|366016|921020|18082099003; X-Microsoft-Antispam-Message-Info: d8u/QimKs0LblJRyFtwCnQpdD7X16+Ddpz9RRFbg9NyfMVzKS8A2Vv4pE0AI9AfbcE87L94c1kBCQscBzqMLx8KLHYCKQIoweBOU4d7nrQpBycod6vsvaRg7vorL4irFlJIyd3CFu7pB37RN+rbJKZ6kvS2o32RRrtNcJhrCenv5WHShRusLHV5e5aZvIT1bMEFSJgdkwfBL9ApAVLrvldabEvwl5GUy4ZymmOfYtdkLMBkTs/mYNU3snH5D437sD6KzcJypmuAT2gBum0s5cXuzjlgIZ5i49Z+IeZZ3tzkjPF9OxdFAUOyw9OmqTXns2PAM+1xXfJaE+uTHxBoRxYtp0IM2An3+1joCY/iCgAKPRHxmLPzwMdf2iyKcUT/Mn4e6ZWjA85eP5OqHD8BqeywkGwy5kytfpbiIjK6MRGGJdncGse7D0+nmYfLnaZ1E2OgI1rHotymPr2AwNrSWQSSxgm3zLKfDdfjQ47Yl03P+tkd1vod6L5qjYs9eIoPb3f3yt5GMShvFrILW+iithCp2Y+AjaGWztdk/jcMnQgpwKBCAFRKj6SYbMUowlDshvKKGOOTW3Axj0OHSvZLswT8PQAUxNhA0tX+E9T18iOw3VEdSAYgGI0rnk9LVC5qJhwSvaRtvVqK1VsqmLdxUR7CPNqPIjKnOjmsspG8NDEutz/FQgvJb5R668rE/PaTctknJnF2bJI3GfbQaaeH25cuILJPa0vlpfp3+UpsloHJjIzklD1SArd4FgA2NMgIT2ruHH8MSq6tA8YyNpAYueA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:GV1PR04MB9135.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(19092799006)(376014)(366016)(921020)(18082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?SHVValQvT2tMcWQzM05hQzN4RjJkaDdFbDR5SVRUeEIwK3V4R1dlUFRhUEdB?= =?utf-8?B?VVhPaDdsclRuMDJBR2RLNnpnNTlGRnNvWW5OQ3hCRzRvT0lXYklmYWFlVEUz?= =?utf-8?B?aWV5ZEs5b2cwVlhIdS9KK1NFa2t1TWdPY21TTkRaSXlERUl4ZGZzMmp5dFJ1?= =?utf-8?B?Mm11SVk3OE80ZVdKTEg1M3J0VEZvRzJtMFM1UVo0ZEtNOUtBdWVnZ1hMS1cw?= =?utf-8?B?Y1h3b3hIVW45R3p4SzdjL0JxZmo2VGVvVU5HcWtnNG9Tb29aZWE1L3M4MTNM?= =?utf-8?B?ME00cUlON1VhdHZXSmpDTzg0SWgyYnFNdG16LzcvVzJDNU9pNUM1MXZReUxY?= =?utf-8?B?UU5zdklyMHEzMDRTY0lkRE5Db0hab0JGSjZTT3pUaFA4dHJnQXRFYlN4TWlI?= =?utf-8?B?VFJkWXc0UEp4QWExSzEvRXRPbC83RXdnTXBEZ2RGc3ZydkNBTnNpNEVTdGVa?= =?utf-8?B?UGJEVFZVVXZpektXZ0JWeEN4aWpHOENialpJWmlmZXVSbnhKVW55YjZkaTd6?= =?utf-8?B?d1lVNGhxUHR5NjdNYXhTUE1Ld1VmWU5hS01yZkNTU3Y3ZndXVWJyZU5iTkxP?= =?utf-8?B?VFB6RGxlZ0pWNTBlRHZ0M0xiOElRb2p1YkdLOEFoUTd3WTlyQlNRS2pUd0h4?= =?utf-8?B?Q3hQMEtGdEJSM0J0Rjc1bHRUclpnZDEwbDhzTDI2blR0ek1iNHgwaXgrRkYr?= =?utf-8?B?YitSRU05THV4Q3R4R1dsUUhobEJ0YW5ua1F1MGtZbG1kTWlKeVRrUjI5eU1l?= =?utf-8?B?bFVGT0QxRHZlYm5GN1JQcFBtT0dPd3hNWFo2WGx3akJaTmdDQ3pzMllHTmMv?= =?utf-8?B?a3lBdGdJaHcrVFF0NHZvUUdnb2FMdFV0MmVVdk9qenlMM1hyQjFpWEM2N3V1?= =?utf-8?B?Q1d5UVJvWWFESkljK21vUTZIa2N0Q1lHTXl0ejIrV25Za0tmTXZtdkpKOXQw?= =?utf-8?B?enFpT0hxVVNxbFY5SlgrYS85TGtDYkxHeHVwc21XeDl6cVB3NUdmUjJmSmY3?= =?utf-8?B?a2NZazkrOUVueElwZDdMMjU4NEpGNFVVdXRYZHBSaDRVYjk0K3B1RENvbllX?= =?utf-8?B?Y1ZXMitNa1pZa25JekNDRDRFeVZCMFAyd3A0dGZpSVFoaDlST3dIOHo0eTZH?= =?utf-8?B?MVpibXlsbEUzckk2bWx0bVlrU0FwOWs3U3A0cUhLM1RTcDN5U1c1Z1E1ZDJF?= =?utf-8?B?MmpVTDgrUGYxdWpJaloyK240UXQ1eFVoWHVCbHdMNzhiNG1ucWRZVEQwdjRy?= =?utf-8?B?YWdCaDVMWHhzSitlUzRYOHA1dlI5S3YwRFlSOTB3WHFpR0xZanJvNTJIVkEz?= =?utf-8?B?cEswNERUMDkyNFFyMW5oZ3k4d2RLaWZUeUhscjloSzU2d1p3WmQxTytOb0ow?= =?utf-8?B?L01qL1Q1dURlMzRhUS8rOWFjd2ZJZDdOa2VaSk43aDlLd0dlTDRjcUxUNUds?= =?utf-8?B?RnNCcUdrZ25YSGdWeG55cjBXcmhxOUlRNWpmYTNVbG9WM0o1dDZDdGF3SmtI?= =?utf-8?B?TVQydnl5c1lZOEVXR2xqbUxQb0hnTzZUMlNOYzRVejBwL1J0MmIzSkIzbFhz?= =?utf-8?B?L2pkUm9BOHVJektrZ1NxZmd1KytjSEU2MTA3NG5Xd2U2N3pSR21aUFdTVEpG?= =?utf-8?B?V1ZMNDFscVVKVjZyU2FZUEg4ak9PYU55c0QzQ0t4NUM3K2ZzNU4wZFNEa052?= =?utf-8?B?S0s3Nk1OOHBuNGEvc3BBWkw5VmJ2ZU5qVXo1RGQraWhGMmhDaTdrR29EdFZI?= =?utf-8?B?NmVJSFlOblBvZ3pnWXZtblFPM1QvRnZIaFNsdmV0NW1vNlQ2SWthcmZMVEtp?= =?utf-8?B?Y0dURDU4UG5Nd25XUkdlcTJNdm1uQ2N6L0lFWDExcmlsK3VYZXVENTZpRUNR?= =?utf-8?B?MUpYd0R3VStwVVcxcjBka1dHYWVNVDlTV3hVaWpZTU5HZTM5amVQWTJva25p?= =?utf-8?B?T1FlN0Jwamt0QXRseFU2YU1tcXpvYVZOSzhpeWEySEtueU5JajdjR2QvU01j?= =?utf-8?B?TmlGYlkrWXVHQnVsQnVUY3p1dzJENFRsK1dKTTRsTWl4VGRPeWd5bG1QTGJD?= =?utf-8?B?dG1sSVY1NmVKQlpVT3R6cFdqMlhkTi9XNHovT3pCcWt4SzZiWENkUTNpRWls?= =?utf-8?B?KzR3ZXhNRTkveUV1Mmt4b29TMjh5WHdEUk80RExoTGlKaVpubW9mVk12RFpW?= =?utf-8?B?VER6VWJNNTFGNXBJY2NXcEJ3bjVGek1SSUhzdFYvWUxteDJZTDZpZmxyNExz?= =?utf-8?B?aWtXT3JQNUpvNmtTRzlSRHMwclBJVEYrZ2Y1dkFOUzVZeHdUbzFvTWJrdnJw?= =?utf-8?B?ZFZKQkZBUWZOUFNWT2x1NkdJR2xqZmRKYVVxc2VCUUIwemdEUVB3cG5WTmx2?= =?utf-8?Q?h6CmEW2o/1zW4/7Q=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 711db806-a4d3-4a89-8c99-08de79e211ee X-MS-Exchange-CrossTenant-AuthSource: GV1PR04MB9135.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2026 11:35:01.0339 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: cenhDeJ/DZS0/kM/iXuPKVcgsB/MNrpLt7D0iWZHxxykh0HQP7qgVTH+IRe8GPMDLwBWRoZYfm6Enpz4cjJBqg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR04MB10522 From: Sandor Yu The i.MX94 Display Control Interface features: * Up to maximum 3 layers of alpha blending: - 1 background layer(Layer 0); - 1 foreground layer(Layer 1); - A programmable constant color behind the background layer; * Each layer supports: - programmable plane size; - programmable background color; - embedded alpha and global alpha; * Data output with CRC checksum for 4 programmable regions; Signed-off-by: Sandor Yu Reviewed-by: Luca Ceresoli # bridge refcounting Signed-off-by: Laurentiu Palcu --- drivers/gpu/drm/imx/Kconfig | 1 + drivers/gpu/drm/imx/Makefile | 1 + drivers/gpu/drm/imx/dcif/Kconfig | 15 + drivers/gpu/drm/imx/dcif/Makefile | 5 + drivers/gpu/drm/imx/dcif/dcif-crc.c | 211 +++++++++++ drivers/gpu/drm/imx/dcif/dcif-crc.h | 52 +++ drivers/gpu/drm/imx/dcif/dcif-crtc.c | 695 ++++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/imx/dcif/dcif-drv.c | 228 +++++++++++ drivers/gpu/drm/imx/dcif/dcif-drv.h | 86 +++++ drivers/gpu/drm/imx/dcif/dcif-kms.c | 100 +++++ drivers/gpu/drm/imx/dcif/dcif-plane.c | 269 +++++++++++++ drivers/gpu/drm/imx/dcif/dcif-reg.h | 267 +++++++++++++ 12 files changed, 1930 insertions(+) diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig index 3e8c6edbc17c2..1b6ced5c60b51 100644 --- a/drivers/gpu/drm/imx/Kconfig +++ b/drivers/gpu/drm/imx/Kconfig @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only =20 source "drivers/gpu/drm/imx/dc/Kconfig" +source "drivers/gpu/drm/imx/dcif/Kconfig" source "drivers/gpu/drm/imx/dcss/Kconfig" source "drivers/gpu/drm/imx/ipuv3/Kconfig" source "drivers/gpu/drm/imx/lcdc/Kconfig" diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile index c7b317640d71d..2b9fd85eefaa3 100644 --- a/drivers/gpu/drm/imx/Makefile +++ b/drivers/gpu/drm/imx/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 =20 obj-$(CONFIG_DRM_IMX8_DC) +=3D dc/ +obj-$(CONFIG_DRM_IMX_DCIF) +=3D dcif/ obj-$(CONFIG_DRM_IMX_DCSS) +=3D dcss/ obj-$(CONFIG_DRM_IMX) +=3D ipuv3/ obj-$(CONFIG_DRM_IMX_LCDC) +=3D lcdc/ diff --git a/drivers/gpu/drm/imx/dcif/Kconfig b/drivers/gpu/drm/imx/dcif/Kc= onfig new file mode 100644 index 0000000000000..c33c662721d36 --- /dev/null +++ b/drivers/gpu/drm/imx/dcif/Kconfig @@ -0,0 +1,15 @@ +config DRM_IMX_DCIF + tristate "DRM support for NXP i.MX94 DCIF" + select DRM_KMS_HELPER + select VIDEOMODE_HELPERS + select DRM_GEM_DMA_HELPER + select DRM_DISPLAY_HELPER + select DRM_BRIDGE_CONNECTOR + select DRM_CLIENT_SELECTION + depends on DRM && OF && ARCH_MXC + depends on COMMON_CLK + help + Enable NXP i.MX94 Display Control Interface(DCIF) support. The DCIF is + a system master that fetches graphics stored in memory and displays + them on a TFT LCD panel or connects to a display interface depending + on the chip configuration. diff --git a/drivers/gpu/drm/imx/dcif/Makefile b/drivers/gpu/drm/imx/dcif/M= akefile new file mode 100644 index 0000000000000..b429572040f0e --- /dev/null +++ b/drivers/gpu/drm/imx/dcif/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + +imx-dcif-drm-objs :=3D dcif-crc.o dcif-crtc.o dcif-drv.o dcif-kms.o dcif-p= lane.o + +obj-$(CONFIG_DRM_IMX_DCIF) +=3D imx-dcif-drm.o diff --git a/drivers/gpu/drm/imx/dcif/dcif-crc.c b/drivers/gpu/drm/imx/dcif= /dcif-crc.c new file mode 100644 index 0000000000000..35743130ccc14 --- /dev/null +++ b/drivers/gpu/drm/imx/dcif/dcif-crc.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2025 NXP + */ + +#include + +#include +#include + +#include "dcif-crc.h" +#include "dcif-reg.h" + +#define MAX_DCIF_CRC_NUM 4 + +static int dcif_crc_config(struct dcif_dev *dcif, struct drm_rect *roi, in= t ncrc) +{ + int pos, size; + + if (ncrc >=3D MAX_DCIF_CRC_NUM) + return -EINVAL; + + pos =3D DCIF_CRC_POS_CRC_HOR_POS(roi->x1) | + DCIF_CRC_POS_CRC_VER_POS(roi->y1); + size =3D DCIF_CRC_SIZE_CRC_HOR_SIZE(roi->x2 - roi->x1) | + DCIF_CRC_SIZE_CRC_VER_SIZE(roi->y2 - roi->y1); + + regmap_write(dcif->regmap, DCIF_CRC_POS_R(ncrc), pos); + regmap_write(dcif->regmap, DCIF_CRC_SIZE_R(ncrc), size); + + regmap_set_bits(dcif->regmap, DCIF_CRC_CTRL, + DCIF_CRC_CTRL_CRC_EN(ncrc) | DCIF_CRC_CTRL_CRC_ERR_CNT_RST); + + return 0; +} + +void dcif_crtc_enable_crc_source(struct dcif_dev *dcif, + enum dcif_crc_source source, + struct drm_rect *roi, + int ncrc) +{ + if (ncrc >=3D MAX_DCIF_CRC_NUM) + return; + + if (source =3D=3D DCIF_CRC_SRC_NONE) + return; + + if (dcif->crc_is_enabled) + return; + + dcif_crc_config(dcif, roi, ncrc); + + regmap_set_bits(dcif->regmap, DCIF_CRC_CTRL, + DCIF_CRC_CTRL_CRC_MODE | DCIF_CRC_CTRL_CRC_SHADOW_LOAD_EN | + DCIF_CRC_CTRL_CRC_TRIG); + + dcif->crc_is_enabled =3D true; +} + +void dcif_crtc_disable_crc_source(struct dcif_dev *dcif, int ncrc) +{ + if (!dcif->crc_is_enabled) + return; + + if (ncrc >=3D MAX_DCIF_CRC_NUM) + return; + + regmap_clear_bits(dcif->regmap, DCIF_CRC_CTRL, DCIF_CRC_CTRL_CRC_EN(ncrc)= ); + + dcif->crc_is_enabled =3D false; +} + +/* + * Supported modes and source names: + * 1) auto mode: + * "auto" should be selected as the source name. + * The evaluation window is the same to the display region as + * indicated by drm_crtc_state->adjusted_mode. + * + * 2) region of interest(ROI) mode: + * "roi:x1,y1,x2,y2" should be selected as the source name. + * The region of interest is defined by the inclusive upper left + * position at (x1, y1) and the exclusive lower right position + * at (x2, y2), see struct drm_rect for the same idea. + * The evaluation window is the region of interest. + */ +static int +dcif_crc_parse_source(const char *source_name, enum dcif_crc_source *s, + struct drm_rect *roi) +{ + static const char roi_prefix[] =3D "roi:"; + + if (!source_name) { + *s =3D DCIF_CRC_SRC_NONE; + } else if (!strcmp(source_name, "auto")) { + *s =3D DCIF_CRC_SRC_FRAME; + } else if (strstarts(source_name, roi_prefix)) { + char *options __free(kfree) =3D NULL, *opt; + int len =3D strlen(roi_prefix); + int params[4]; + int i =3D 0, ret; + + options =3D kstrdup(source_name + len, GFP_KERNEL); + + while ((opt =3D strsep(&options, ",")) !=3D NULL) { + if (i > 3) + return -EINVAL; + + ret =3D kstrtouint(opt, 10, ¶ms[i]); + if (ret < 0) + return ret; + + if (params[i] < 0) + return -EINVAL; + + i++; + } + + if (i !=3D 4) + return -EINVAL; + + roi->x1 =3D params[0]; + roi->y1 =3D params[1]; + roi->x2 =3D params[2]; + roi->y2 =3D params[3]; + + if (!drm_rect_visible(roi)) + return -EINVAL; + + *s =3D DCIF_CRC_SRC_FRAME_ROI; + } else { + return -EINVAL; + } + + return 0; +} + +int dcif_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_= name, + size_t *values_cnt) +{ + struct dcif_dev *dcif =3D crtc_to_dcif_dev(crtc); + enum dcif_crc_source source; + struct drm_rect roi; + + if (dcif_crc_parse_source(source_name, &source, &roi) < 0) { + dev_dbg(dcif->drm.dev, "unknown source %s\n", source_name); + return -EINVAL; + } + + *values_cnt =3D 1; + + return 0; +} + +int dcif_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_nam= e) +{ + struct dcif_dev *dcif =3D crtc_to_dcif_dev(crtc); + struct drm_modeset_acquire_ctx ctx; + struct drm_crtc_state *crtc_state; + struct drm_atomic_state *state; + struct drm_rect roi =3D {0, 0, 0, 0}; + enum dcif_crc_source source; + int ret; + + if (dcif_crc_parse_source(source_name, &source, &roi) < 0) { + dev_dbg(dcif->drm.dev, "unknown source %s\n", source_name); + return -EINVAL; + } + + /* Perform an atomic commit to set the CRC source. */ + drm_modeset_acquire_init(&ctx, 0); + + state =3D drm_atomic_state_alloc(crtc->dev); + if (!state) { + ret =3D -ENOMEM; + goto unlock; + } + + state->acquire_ctx =3D &ctx; + +retry: + crtc_state =3D drm_atomic_get_crtc_state(state, crtc); + if (!IS_ERR(crtc_state)) { + struct dcif_crtc_state *dcif_crtc_state; + + dcif_crtc_state =3D to_dcif_crtc_state(crtc_state); + + dcif_crtc_state->crc.source =3D source; + dcif_copy_roi(&roi, &dcif_crtc_state->crc.roi); + + ret =3D drm_atomic_commit(state); + } else { + ret =3D PTR_ERR(crtc_state); + } + + if (ret =3D=3D -EDEADLK) { + drm_atomic_state_clear(state); + drm_modeset_backoff(&ctx); + goto retry; + } + + drm_atomic_state_put(state); + +unlock: + drm_modeset_drop_locks(&ctx); + drm_modeset_acquire_fini(&ctx); + + return ret; +} + diff --git a/drivers/gpu/drm/imx/dcif/dcif-crc.h b/drivers/gpu/drm/imx/dcif= /dcif-crc.h new file mode 100644 index 0000000000000..a51b44165d564 --- /dev/null +++ b/drivers/gpu/drm/imx/dcif/dcif-crc.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* + * Copyright 2025 NXP + */ + +#ifndef __DCIF_CRC_H__ +#define __DCIF_CRC_H__ + +#include + +#include "dcif-drv.h" + +static inline bool to_enable_dcif_crc(struct dcif_crtc_state *new_dcstate, + struct dcif_crtc_state *old_dcstate) +{ + return old_dcstate->crc.source =3D=3D DCIF_CRC_SRC_NONE && + new_dcstate->crc.source !=3D DCIF_CRC_SRC_NONE; +} + +static inline bool to_disable_dcif_crc(struct dcif_crtc_state *new_dcstate, + struct dcif_crtc_state *old_dcstate) +{ + return old_dcstate->crc.source !=3D DCIF_CRC_SRC_NONE && + new_dcstate->crc.source =3D=3D DCIF_CRC_SRC_NONE; +} + +static inline void dcif_copy_roi(struct drm_rect *from, struct drm_rect *t= o) +{ + to->x1 =3D from->x1; + to->y1 =3D from->y1; + to->x2 =3D from->x2; + to->y2 =3D from->y2; +} + +#ifdef CONFIG_DEBUG_FS +int dcif_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_= name, + size_t *values_cnt); +int dcif_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_nam= e); +void dcif_crtc_enable_crc_source(struct dcif_dev *dcif, + enum dcif_crc_source source, + struct drm_rect *roi, + int ncrc); +void dcif_crtc_disable_crc_source(struct dcif_dev *dcif, int ncrc); +#else +#define dcif_crtc_verify_crc_source NULL +#define dcif_crtc_set_crc_source NULL +#define dcif_crtc_enable_crc_source NULL +#define dcif_crtc_disable_crc_source NULL +#endif + +#endif /* __DCIF_CRC_H__ */ diff --git a/drivers/gpu/drm/imx/dcif/dcif-crtc.c b/drivers/gpu/drm/imx/dci= f/dcif-crtc.c new file mode 100644 index 0000000000000..b509bb57f4e8a --- /dev/null +++ b/drivers/gpu/drm/imx/dcif/dcif-crtc.c @@ -0,0 +1,695 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dcif-crc.h" +#include "dcif-drv.h" +#include "dcif-reg.h" + +#define DCIF_MAX_PIXEL_CLOCK 148500000 + +/* -----------------------------------------------------------------------= ------ + * CRTC + */ + +/* + * For conversion from YCbCr to RGB, the CSC operates as follows: + * + * |R| |A1 A2 A3| |Y + D1| + * |G| =3D |B1 B2 B3| * |Cb + D2| + * |B| |C1 C2 C3| |Cr + D3| + * + * The A, B and C coefficients are expressed as signed Q3.8 fixed point va= lues and + * the D coefficients as signed Q9.0. + */ +static const u32 dcif_yuv2rgb_coeffs[3][2][6] =3D { + [DRM_COLOR_YCBCR_BT601] =3D { + [DRM_COLOR_YCBCR_LIMITED_RANGE] =3D { + /* + * BT.601 limited range: + * + * |R| |1.1644 0.0000 1.5960| |Y - 16 | + * |G| =3D |1.1644 -0.3917 -0.8129| * |Cb - 128| + * |B| |1.1644 2.0172 0.0000| |Cr - 128| + */ + DCIF_CSC_COEF0_L0_A1(0x12a) | DCIF_CSC_COEF0_L0_A2(0x000), + DCIF_CSC_COEF1_L0_A3(0x199) | DCIF_CSC_COEF1_L0_B1(0x12a), + DCIF_CSC_COEF2_L0_B2(0x79c) | DCIF_CSC_COEF2_L0_B3(0x730), + DCIF_CSC_COEF3_L0_C1(0x12a) | DCIF_CSC_COEF3_L0_C2(0x204), + DCIF_CSC_COEF4_L0_C3(0x000) | DCIF_CSC_COEF4_L0_D1(0x1f0), + DCIF_CSC_COEF5_L0_D2(0x180) | DCIF_CSC_COEF5_L0_D3(0x180), + }, + [DRM_COLOR_YCBCR_FULL_RANGE] =3D { + /* + * BT.601 full range: + * + * |R| |1.0000 0.0000 1.4020| |Y - 0 | + * |G| =3D |1.0000 -0.3441 -0.7141| * |Cb - 128| + * |B| |1.0000 1.7720 0.0000| |Cr - 128| + */ + DCIF_CSC_COEF0_L0_A1(0x100) | DCIF_CSC_COEF0_L0_A2(0x000), + DCIF_CSC_COEF1_L0_A3(0x167) | DCIF_CSC_COEF1_L0_B1(0x100), + DCIF_CSC_COEF2_L0_B2(0x7a8) | DCIF_CSC_COEF2_L0_B3(0x749), + DCIF_CSC_COEF3_L0_C1(0x100) | DCIF_CSC_COEF3_L0_C2(0x1c6), + DCIF_CSC_COEF4_L0_C3(0x000) | DCIF_CSC_COEF4_L0_D1(0x000), + DCIF_CSC_COEF5_L0_D2(0x180) | DCIF_CSC_COEF5_L0_D3(0x180), + }, + }, + [DRM_COLOR_YCBCR_BT709] =3D { + [DRM_COLOR_YCBCR_LIMITED_RANGE] =3D { + /* + * Rec.709 limited range: + * + * |R| |1.1644 0.0000 1.7927| |Y - 16 | + * |G| =3D |1.1644 -0.2132 -0.5329| * |Cb - 128| + * |B| |1.1644 2.1124 0.0000| |Cr - 128| + */ + DCIF_CSC_COEF0_L0_A1(0x12a) | DCIF_CSC_COEF0_L0_A2(0x000), + DCIF_CSC_COEF1_L0_A3(0x1cb) | DCIF_CSC_COEF1_L0_B1(0x12a), + DCIF_CSC_COEF2_L0_B2(0x7c9) | DCIF_CSC_COEF2_L0_B3(0x778), + DCIF_CSC_COEF3_L0_C1(0x12a) | DCIF_CSC_COEF3_L0_C2(0x21d), + DCIF_CSC_COEF4_L0_C3(0x000) | DCIF_CSC_COEF4_L0_D1(0x1f0), + DCIF_CSC_COEF5_L0_D2(0x180) | DCIF_CSC_COEF5_L0_D3(0x180), + }, + [DRM_COLOR_YCBCR_FULL_RANGE] =3D { + /* + * Rec.709 full range: + * + * |R| |1.0000 0.0000 1.5748| |Y - 0 | + * |G| =3D |1.0000 -0.1873 -0.4681| * |Cb - 128| + * |B| |1.0000 1.8556 0.0000| |Cr - 128| + */ + DCIF_CSC_COEF0_L0_A1(0x100) | DCIF_CSC_COEF0_L0_A2(0x000), + DCIF_CSC_COEF1_L0_A3(0x193) | DCIF_CSC_COEF1_L0_B1(0x100), + DCIF_CSC_COEF2_L0_B2(0x7d0) | DCIF_CSC_COEF2_L0_B3(0x788), + DCIF_CSC_COEF3_L0_C1(0x100) | DCIF_CSC_COEF3_L0_C2(0x1db), + DCIF_CSC_COEF4_L0_C3(0x000) | DCIF_CSC_COEF4_L0_D1(0x000), + DCIF_CSC_COEF5_L0_D2(0x180) | DCIF_CSC_COEF5_L0_D3(0x180), + }, + }, + [DRM_COLOR_YCBCR_BT2020] =3D { + [DRM_COLOR_YCBCR_LIMITED_RANGE] =3D { + /* + * BT.2020 limited range: + * + * |R| |1.1644 0.0000 1.6787| |Y - 16 | + * |G| =3D |1.1644 -0.1874 -0.6505| * |Cb - 128| + * |B| |1.1644 2.1418 0.0000| |Cr - 128| + */ + DCIF_CSC_COEF0_L0_A1(0x12a) | DCIF_CSC_COEF0_L0_A2(0x000), + DCIF_CSC_COEF1_L0_A3(0x1ae) | DCIF_CSC_COEF1_L0_B1(0x12a), + DCIF_CSC_COEF2_L0_B2(0x7d0) | DCIF_CSC_COEF2_L0_B3(0x759), + DCIF_CSC_COEF3_L0_C1(0x12a) | DCIF_CSC_COEF3_L0_C2(0x224), + DCIF_CSC_COEF4_L0_C3(0x000) | DCIF_CSC_COEF4_L0_D1(0x1f0), + DCIF_CSC_COEF5_L0_D2(0x180) | DCIF_CSC_COEF5_L0_D3(0x180), + }, + [DRM_COLOR_YCBCR_FULL_RANGE] =3D { + /* + * BT.2020 full range: + * + * |R| |1.0000 0.0000 1.4746| |Y - 0 | + * |G| =3D |1.0000 -0.1646 -0.5714| * |Cb - 128| + * |B| |1.0000 1.8814 0.0000| |Cr - 128| + */ + DCIF_CSC_COEF0_L0_A1(0x100) | DCIF_CSC_COEF0_L0_A2(0x000), + DCIF_CSC_COEF1_L0_A3(0x179) | DCIF_CSC_COEF1_L0_B1(0x100), + DCIF_CSC_COEF2_L0_B2(0x7d6) | DCIF_CSC_COEF2_L0_B3(0x76e), + DCIF_CSC_COEF3_L0_C1(0x100) | DCIF_CSC_COEF3_L0_C2(0x1e2), + DCIF_CSC_COEF4_L0_C3(0x000) | DCIF_CSC_COEF4_L0_D1(0x000), + DCIF_CSC_COEF5_L0_D2(0x180) | DCIF_CSC_COEF5_L0_D3(0x180), + }, + }, +}; + +static enum drm_mode_status dcif_crtc_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) +{ + if (mode->crtc_clock > DCIF_MAX_PIXEL_CLOCK) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static void dcif_set_formats(struct dcif_dev *dcif, struct drm_plane_state= *plane_state, + const u32 bus_format) +{ + const u32 format =3D plane_state->fb->format->format; + struct drm_device *drm =3D &dcif->drm; + bool in_yuv =3D false; + u32 reg =3D 0; + + switch (bus_format) { + case MEDIA_BUS_FMT_RGB565_1X16: + reg |=3D DCIF_DPI_CTRL_DATA_PATTERN(PATTERN_RGB565); + break; + case MEDIA_BUS_FMT_RGB888_1X24: + reg |=3D DCIF_DPI_CTRL_DATA_PATTERN(PATTERN_RGB888); + break; + case MEDIA_BUS_FMT_RBG888_1X24: + reg |=3D DCIF_DPI_CTRL_DATA_PATTERN(PATTERN_RBG888); + break; + case MEDIA_BUS_FMT_BGR888_1X24: + reg |=3D DCIF_DPI_CTRL_DATA_PATTERN(PATTERN_BGR888); + break; + case MEDIA_BUS_FMT_GBR888_1X24: + reg |=3D DCIF_DPI_CTRL_DATA_PATTERN(PATTERN_GBR888); + break; + default: + dev_err(drm->dev, "Unknown media bus format 0x%x\n", bus_format); + break; + } + + regmap_update_bits(dcif->regmap, DCIF_DPI_CTRL, DCIF_DPI_CTRL_DATA_PATTER= N_MASK, reg); + + reg =3D 0; + switch (format) { + /* RGB Formats */ + case DRM_FORMAT_RGB565: + reg |=3D DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_RGB565); + break; + case DRM_FORMAT_RGB888: + reg |=3D DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_RGB888); + break; + case DRM_FORMAT_XRGB1555: + reg |=3D DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_ARGB1555); + break; + case DRM_FORMAT_XRGB4444: + reg |=3D DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_ARGB4444); + break; + case DRM_FORMAT_XBGR8888: + reg |=3D DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_ABGR8888); + break; + case DRM_FORMAT_XRGB8888: + reg |=3D DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_ARGB8888); + break; + + /* YUV Formats */ + case DRM_FORMAT_YUYV: + reg |=3D DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_YCBCR422) | + DCIF_CTRLDESC0_YUV_FORMAT(CTRLDESCL0_YUV_FORMAT_VY2UY1); + in_yuv =3D true; + break; + case DRM_FORMAT_YVYU: + reg |=3D DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_YCBCR422) | + DCIF_CTRLDESC0_YUV_FORMAT(CTRLDESCL0_YUV_FORMAT_UY2VY1); + in_yuv =3D true; + break; + case DRM_FORMAT_UYVY: + reg |=3D DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_YCBCR422) | + DCIF_CTRLDESC0_YUV_FORMAT(CTRLDESCL0_YUV_FORMAT_Y2VY1U); + in_yuv =3D true; + break; + case DRM_FORMAT_VYUY: + reg |=3D DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_YCBCR422) | + DCIF_CTRLDESC0_YUV_FORMAT(CTRLDESCL0_YUV_FORMAT_Y2UY1V); + in_yuv =3D true; + break; + + default: + dev_err(drm->dev, "Unknown pixel format 0x%x\n", format); + break; + } + + regmap_update_bits(dcif->regmap, DCIF_CTRLDESC0(0), + DCIF_CTRLDESC0_FORMAT_MASK | DCIF_CTRLDESC0_YUV_FORMAT_MASK, + reg); + + if (in_yuv) { + /* Enable CSC YCbCr -> RGB */ + const u32 *coeffs =3D + dcif_yuv2rgb_coeffs[plane_state->color_encoding][plane_state->color_ran= ge]; + + regmap_bulk_write(dcif->regmap, DCIF_CSC_COEF0_L0, coeffs, 6); + + regmap_write(dcif->regmap, DCIF_CSC_CTRL_L0, + DCIF_CSC_CTRL_L0_CSC_EN | + DCIF_CSC_CTRL_L0_CSC_MODE_YCBCR2RGB); + } else { + regmap_write(dcif->regmap, DCIF_CSC_CTRL_L0, 0); + } +} + +static void dcif_set_mode(struct dcif_dev *dcif, u32 bus_flags) +{ + struct drm_display_mode *m =3D &dcif->crtc.state->adjusted_mode; + u32 reg =3D 0; + + if (m->flags & DRM_MODE_FLAG_NHSYNC) + reg |=3D DCIF_DPI_CTRL_HSYNC_POL_LOW; + if (m->flags & DRM_MODE_FLAG_NVSYNC) + reg |=3D DCIF_DPI_CTRL_VSYNC_POL_LOW; + if (bus_flags & DRM_BUS_FLAG_DE_LOW) + reg |=3D DCIF_DPI_CTRL_DE_POL_LOW; + if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) + reg |=3D DCIF_DPI_CTRL_PCLK_EDGE_FALLING; + + regmap_update_bits(dcif->regmap, DCIF_DPI_CTRL, DCIF_DPI_CTRL_POL_MASK, r= eg); + + /* config display timings */ + reg =3D DCIF_DISP_SIZE_DISP_WIDTH(m->hdisplay) | + DCIF_DISP_SIZE_DISP_HEIGHT(m->vdisplay); + regmap_write(dcif->regmap, DCIF_DISP_SIZE, reg); + + reg =3D DCIF_DPI_HSYN_PAR_BP_H(m->htotal - m->hsync_end) | + DCIF_DPI_HSYN_PAR_FP_H(m->hsync_start - m->hdisplay); + regmap_write(dcif->regmap, DCIF_DPI_HSYN_PAR, reg); + + reg =3D DCIF_DPI_VSYN_PAR_BP_V(m->vtotal - m->vsync_end) | + DCIF_DPI_VSYN_PAR_FP_V(m->vsync_start - m->vdisplay); + regmap_write(dcif->regmap, DCIF_DPI_VSYN_PAR, reg); + + reg =3D DCIF_DPI_VSYN_HSYN_WIDTH_PW_V(m->vsync_end - m->vsync_start) | + DCIF_DPI_VSYN_HSYN_WIDTH_PW_H(m->hsync_end - m->hsync_start); + regmap_write(dcif->regmap, DCIF_DPI_VSYN_HSYN_WIDTH, reg); + + /* Layer 0 frame size */ + reg =3D DCIF_CTRLDESC2_HEIGHT(m->vdisplay) | + DCIF_CTRLDESC2_WIDTH(m->hdisplay); + regmap_write(dcif->regmap, DCIF_CTRLDESC2(0), reg); + + /* + * Configure P_SIZE, T_SIZE and pitch + * 1. P_SIZE and T_SIZE should never be less than AXI bus width. + * 2. P_SIZE should never be less than T_SIZE. + */ + reg =3D DCIF_CTRLDESC3_P_SIZE(2) | DCIF_CTRLDESC3_T_SIZE(2) | + DCIF_CTRLDESC3_PITCH(dcif->crtc.primary->state->fb->pitches[0]); + regmap_write(dcif->regmap, DCIF_CTRLDESC3(0), reg); +} + +static void dcif_enable_plane_panic(struct dcif_dev *dcif) +{ + u32 reg; + + /* Set FIFO Panic watermarks, low 1/3, high 2/3. */ + reg =3D DCIF_PANIC_THRES_LOW(1 * PANIC0_THRES_MAX / 3) | + DCIF_PANIC_THRES_HIGH(2 * PANIC0_THRES_MAX / 3) | + DCIF_PANIC_THRES_REQ_EN; + regmap_write(dcif->regmap, DCIF_PANIC_THRES(0), reg); + regmap_write(dcif->regmap, DCIF_PANIC_THRES(1), reg); + + regmap_set_bits(dcif->regmap, DCIF_IE1(dcif->cpu_domain), + DCIF_INT1_FIFO_PANIC0 | DCIF_INT1_FIFO_PANIC1); +} + +static void dcif_disable_plane_panic(struct dcif_dev *dcif) +{ + regmap_clear_bits(dcif->regmap, DCIF_IE1(dcif->cpu_domain), + DCIF_INT1_FIFO_PANIC0 | DCIF_INT1_FIFO_PANIC1); + regmap_clear_bits(dcif->regmap, DCIF_PANIC_THRES(0), DCIF_PANIC_THRES_REQ= _EN); + regmap_clear_bits(dcif->regmap, DCIF_PANIC_THRES(1), DCIF_PANIC_THRES_REQ= _EN); +} + +static void dcif_enable_controller(struct dcif_dev *dcif) +{ + /* Enable Display */ + regmap_set_bits(dcif->regmap, DCIF_DISP_CTRL, DCIF_DISP_CTRL_DISP_ON); + + /* Enable layer 0 */ + regmap_set_bits(dcif->regmap, DCIF_CTRLDESC0(0), DCIF_CTRLDESC0_EN); +} + +static void dcif_disable_controller(struct dcif_dev *dcif) +{ + u32 reg; + int ret; + + /* Disable layer 0 */ + regmap_clear_bits(dcif->regmap, DCIF_CTRLDESC0(0), DCIF_CTRLDESC0_EN); + + ret =3D regmap_read_poll_timeout(dcif->regmap, DCIF_CTRLDESC0(0), reg, + !(reg & DCIF_CTRLDESC0_EN), 0, + 36000); /* Wait ~2 frame times max */ + if (ret) + drm_err(&dcif->drm, "Failed to disable controller!\n"); + + /* Disable Display */ + regmap_clear_bits(dcif->regmap, DCIF_DISP_CTRL, DCIF_DISP_CTRL_DISP_ON); +} + +static void dcif_shadow_load_enable(struct dcif_dev *dcif) +{ + regmap_write_bits(dcif->regmap, DCIF_CTRLDESC0(0), DCIF_CTRLDESC0_SHADOW_= LOAD_EN, + DCIF_CTRLDESC0_SHADOW_LOAD_EN); +} + +static void dcif_reset_block(struct dcif_dev *dcif) +{ + regmap_set_bits(dcif->regmap, DCIF_DISP_CTRL, DCIF_DISP_CTRL_SW_RST); + + regmap_clear_bits(dcif->regmap, DCIF_DISP_CTRL, DCIF_DISP_CTRL_SW_RST); +} + +static void dcif_crtc_atomic_destroy_state(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + __drm_atomic_helper_crtc_destroy_state(state); + kfree(to_dcif_crtc_state(state)); +} + +static void dcif_crtc_reset(struct drm_crtc *crtc) +{ + struct dcif_crtc_state *state; + + if (crtc->state) + dcif_crtc_atomic_destroy_state(crtc, crtc->state); + + crtc->state =3D NULL; + + state =3D kzalloc_obj(*state, GFP_KERNEL); + if (state) + __drm_atomic_helper_crtc_reset(crtc, &state->base); +} + +static struct drm_crtc_state *dcif_crtc_atomic_duplicate_state(struct drm_= crtc *crtc) +{ + struct dcif_crtc_state *old =3D to_dcif_crtc_state(crtc->state); + struct dcif_crtc_state *new; + + if (WARN_ON(!crtc->state)) + return NULL; + + new =3D kzalloc_obj(*new, GFP_KERNEL); + if (!new) + return NULL; + + __drm_atomic_helper_crtc_duplicate_state(crtc, &new->base); + + new->bus_format =3D old->bus_format; + new->bus_flags =3D old->bus_flags; + new->crc.source =3D old->crc.source; + dcif_copy_roi(&old->crc.roi, &new->crc.roi); + + return &new->base; +} + +static void dcif_crtc_mode_set_nofb(struct drm_crtc_state *crtc_state, + struct drm_plane_state *plane_state) +{ + struct dcif_crtc_state *dcif_crtc_state =3D to_dcif_crtc_state(crtc_state= ); + struct drm_device *drm =3D crtc_state->crtc->dev; + struct dcif_dev *dcif =3D crtc_to_dcif_dev(crtc_state->crtc); + struct drm_display_mode *m =3D &crtc_state->adjusted_mode; + + dev_dbg(drm->dev, "Pixel clock: %dkHz\n", m->crtc_clock); + dev_dbg(drm->dev, "Bridge bus_flags: 0x%08X\n", dcif_crtc_state->bus_flag= s); + dev_dbg(drm->dev, "Mode flags: 0x%08X\n", m->flags); + + dcif_reset_block(dcif); + + dcif_set_formats(dcif, plane_state, dcif_crtc_state->bus_format); + + dcif_set_mode(dcif, dcif_crtc_state->bus_flags); +} + +static void dcif_crtc_queue_state_event(struct drm_crtc *crtc) +{ + struct dcif_dev *dcif =3D crtc_to_dcif_dev(crtc); + + scoped_guard(spinlock, &crtc->dev->event_lock) { + if (crtc->state->event) { + WARN_ON(drm_crtc_vblank_get(crtc)); + WARN_ON(dcif->event); + dcif->event =3D crtc->state->event; + crtc->state->event =3D NULL; + } + } +} + +static struct drm_bridge *dcif_crtc_get_bridge(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state) +{ + struct drm_connector_state *conn_state; + struct drm_encoder *encoder; + struct drm_connector *conn; + struct drm_bridge *bridge; + int i; + + for_each_new_connector_in_state(crtc_state->state, conn, conn_state, i) { + if (crtc !=3D conn_state->crtc) + continue; + + encoder =3D conn_state->best_encoder; + + bridge =3D drm_bridge_chain_get_first_bridge(encoder); + if (bridge) + return bridge; + } + + return NULL; +} + +static void dcif_crtc_query_output_bus_format(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state) +{ + struct dcif_crtc_state *dcif_state =3D to_dcif_crtc_state(crtc_state); + struct drm_bridge *bridge __free(drm_bridge_put) =3D NULL; + struct drm_bridge_state *bridge_state; + + dcif_state->bus_format =3D MEDIA_BUS_FMT_RGB888_1X24; + dcif_state->bus_flags =3D 0; + + bridge =3D dcif_crtc_get_bridge(crtc, crtc_state); + if (!bridge) + return; + + bridge_state =3D drm_atomic_get_new_bridge_state(crtc_state->state, bridg= e); + if (!bridge_state) + return; + + dcif_state->bus_format =3D bridge_state->input_bus_cfg.format; + dcif_state->bus_flags =3D bridge_state->input_bus_cfg.flags; +} + +static int dcif_crtc_atomic_check(struct drm_crtc *crtc, struct drm_atomic= _state *state) +{ + struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(state= , crtc); + bool enable_primary =3D crtc_state->plane_mask & drm_plane_mask(crtc->pri= mary); + int ret; + + if (crtc_state->active && !enable_primary) + return -EINVAL; + + dcif_crtc_query_output_bus_format(crtc, crtc_state); + + if (crtc_state->active_changed && crtc_state->active) { + if (!crtc_state->mode_changed) { + crtc_state->mode_changed =3D true; + ret =3D drm_atomic_helper_check_modeset(crtc->dev, state); + if (ret) + return ret; + } + } + + return 0; +} + +static void dcif_crtc_atomic_flush(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct drm_crtc_state *old_crtc_state =3D drm_atomic_get_old_crtc_state(s= tate, crtc); + struct dcif_crtc_state *old_dcif_crtc_state =3D to_dcif_crtc_state(old_cr= tc_state); + struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(state= , crtc); + struct dcif_crtc_state *dcif_crtc_state =3D to_dcif_crtc_state(crtc_state= ); + bool need_modeset =3D drm_atomic_crtc_needs_modeset(crtc->state); + struct dcif_dev *dcif =3D crtc_to_dcif_dev(crtc); + + dcif_shadow_load_enable(dcif); + + if (!crtc->state->active && !old_crtc_state->active) + return; + + if (!need_modeset && to_disable_dcif_crc(dcif_crtc_state, old_dcif_crtc_s= tate)) + dcif_crtc_disable_crc_source(dcif, 0); + + if (!need_modeset) + dcif_crtc_queue_state_event(crtc); + + if (!need_modeset && to_enable_dcif_crc(dcif_crtc_state, old_dcif_crtc_st= ate)) + dcif_crtc_enable_crc_source(dcif, dcif_crtc_state->crc.source, + &dcif_crtc_state->crc.roi, 0); +} + +static void dcif_crtc_atomic_enable(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(state= , crtc); + struct drm_plane_state *plane_state =3D drm_atomic_get_new_plane_state(st= ate, crtc->primary); + struct dcif_crtc_state *dcif_crtc_state =3D to_dcif_crtc_state(crtc_state= ); + struct drm_display_mode *adj =3D &crtc_state->adjusted_mode; + struct dcif_dev *dcif =3D crtc_to_dcif_dev(crtc); + struct drm_device *drm =3D crtc->dev; + dma_addr_t baseaddr; + int ret; + + dev_dbg(drm->dev, "mode " DRM_MODE_FMT "\n", DRM_MODE_ARG(adj)); + + /* enable power when we start to set mode for CRTC */ + ret =3D pm_runtime_resume_and_get(drm->dev); + if (ret < 0) + drm_err(drm, "failed to resume DCIF, ret =3D %d\n", ret); + + drm_crtc_vblank_on(crtc); + + dcif_crtc_mode_set_nofb(crtc_state, plane_state); + + baseaddr =3D drm_fb_dma_get_gem_addr(plane_state->fb, plane_state, 0); + if (baseaddr) + regmap_write(dcif->regmap, DCIF_CTRLDESC4(0), baseaddr); + + dcif_enable_plane_panic(dcif); + dcif_enable_controller(dcif); + + dcif_crtc_queue_state_event(crtc); + + if (dcif->has_crc && dcif_crtc_state->crc.source !=3D DCIF_CRC_SRC_NONE) + dcif_crtc_enable_crc_source(dcif, dcif_crtc_state->crc.source, + &dcif_crtc_state->crc.roi, 0); +} + +static void dcif_crtc_atomic_disable(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(state= , crtc); + struct dcif_crtc_state *dcif_crtc_state =3D to_dcif_crtc_state(crtc_state= ); + struct dcif_dev *dcif =3D crtc_to_dcif_dev(crtc); + struct drm_device *drm =3D crtc->dev; + + if (dcif->has_crc && dcif_crtc_state->crc.source !=3D DCIF_CRC_SRC_NONE) + dcif_crtc_disable_crc_source(dcif, 0); + + dcif_disable_controller(dcif); + dcif_disable_plane_panic(dcif); + + drm_crtc_vblank_off(crtc); + + pm_runtime_put_sync(drm->dev); + + scoped_guard(spinlock, &crtc->dev->event_lock) { + if (crtc->state->event && !crtc->state->active) { + drm_crtc_send_vblank_event(crtc, crtc->state->event); + crtc->state->event =3D NULL; + } + } +} + +static const struct drm_crtc_helper_funcs dcif_crtc_helper_funcs =3D { + .mode_valid =3D dcif_crtc_mode_valid, + .atomic_check =3D dcif_crtc_atomic_check, + .atomic_flush =3D dcif_crtc_atomic_flush, + .atomic_enable =3D dcif_crtc_atomic_enable, + .atomic_disable =3D dcif_crtc_atomic_disable, +}; + +static int dcif_crtc_enable_vblank(struct drm_crtc *crtc) +{ + struct dcif_dev *dcif =3D crtc_to_dcif_dev(crtc); + int domain =3D dcif->cpu_domain; + + /* Clear and enable VS_BLANK IRQ */ + regmap_set_bits(dcif->regmap, DCIF_IS0(domain), DCIF_INT0_VS_BLANK); + regmap_set_bits(dcif->regmap, DCIF_IE0(domain), DCIF_INT0_VS_BLANK); + + return 0; +} + +static void dcif_crtc_disable_vblank(struct drm_crtc *crtc) +{ + struct dcif_dev *dcif =3D crtc_to_dcif_dev(crtc); + int domain =3D dcif->cpu_domain; + + /* Disable and clear VS_BLANK IRQ */ + regmap_clear_bits(dcif->regmap, DCIF_IE0(domain), DCIF_INT0_VS_BLANK); + regmap_clear_bits(dcif->regmap, DCIF_IS0(domain), DCIF_INT0_VS_BLANK); +} + +static const struct drm_crtc_funcs dcif_crtc_funcs =3D { + .reset =3D dcif_crtc_reset, + .destroy =3D drm_crtc_cleanup, + .set_config =3D drm_atomic_helper_set_config, + .page_flip =3D drm_atomic_helper_page_flip, + .atomic_duplicate_state =3D dcif_crtc_atomic_duplicate_state, + .atomic_destroy_state =3D dcif_crtc_atomic_destroy_state, + .enable_vblank =3D dcif_crtc_enable_vblank, + .disable_vblank =3D dcif_crtc_disable_vblank, + .set_crc_source =3D dcif_crtc_set_crc_source, + .verify_crc_source =3D dcif_crtc_verify_crc_source, +}; + +irqreturn_t dcif_irq_handler(int irq, void *data) +{ + struct drm_device *drm =3D data; + struct dcif_dev *dcif =3D to_dcif_dev(drm); + int domain =3D dcif->cpu_domain; + u32 stat0, stat1, crc; + + regmap_read(dcif->regmap, DCIF_IS0(domain), &stat0); + regmap_read(dcif->regmap, DCIF_IS1(domain), &stat1); + regmap_write(dcif->regmap, DCIF_IS0(domain), stat0); + regmap_write(dcif->regmap, DCIF_IS1(domain), stat1); + + if (stat0 & DCIF_INT0_VS_BLANK) { + drm_crtc_handle_vblank(&dcif->crtc); + + scoped_guard(spinlock_irqsave, &drm->event_lock) { + if (dcif->event) { + drm_crtc_send_vblank_event(&dcif->crtc, dcif->event); + dcif->event =3D NULL; + drm_crtc_vblank_put(&dcif->crtc); + } + if (dcif->crc_is_enabled) { + regmap_read(dcif->regmap, DCIF_CRC_VAL_R(0), &crc); + drm_crtc_add_crc_entry(&dcif->crtc, false, 0, &crc); + dev_dbg(drm->dev, "crc=3D0x%x\n", crc); + } + } + } + + if (stat1 & (DCIF_INT1_FIFO_PANIC0 | DCIF_INT1_FIFO_PANIC1)) { + u32 panic =3D stat1 & (DCIF_INT1_FIFO_PANIC0 | DCIF_INT1_FIFO_PANIC1); + + dev_dbg_ratelimited(drm->dev, "FIFO panic on %s\n", + panic =3D=3D (DCIF_INT1_FIFO_PANIC0 | DCIF_INT1_FIFO_PANIC1) ? + "layers 0 & 1" : panic =3D=3D DCIF_INT1_FIFO_PANIC0 ? "layer 0" : + "layer 1"); + } + + return IRQ_HANDLED; +} + +int dcif_crtc_init(struct dcif_dev *dcif) +{ + int ret; + + ret =3D dcif_plane_init(dcif); + if (ret) + return ret; + + drm_crtc_helper_add(&dcif->crtc, &dcif_crtc_helper_funcs); + ret =3D drm_crtc_init_with_planes(&dcif->drm, &dcif->crtc, &dcif->planes.= primary, NULL, + &dcif_crtc_funcs, NULL); + if (ret) { + drm_err(&dcif->drm, "failed to initialize CRTC: %d\n", ret); + return ret; + } + + return 0; +} diff --git a/drivers/gpu/drm/imx/dcif/dcif-drv.c b/drivers/gpu/drm/imx/dcif= /dcif-drv.c new file mode 100644 index 0000000000000..9e3d19d0a4aa6 --- /dev/null +++ b/drivers/gpu/drm/imx/dcif/dcif-drv.c @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "dcif-drv.h" +#include "dcif-reg.h" + +#define DCIF_CPU_DOMAIN 0 + +DEFINE_DRM_GEM_DMA_FOPS(dcif_driver_fops); + +static struct drm_driver dcif_driver =3D { + .driver_features =3D DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, + DRM_GEM_DMA_DRIVER_OPS, + DRM_FBDEV_DMA_DRIVER_OPS, + .fops =3D &dcif_driver_fops, + .name =3D "imx-dcif", + .desc =3D "i.MX DCIF DRM graphics", + .major =3D 1, + .minor =3D 0, + .patchlevel =3D 0, +}; + +static void dcif_read_chip_info(struct dcif_dev *dcif) +{ + struct drm_device *drm =3D &dcif->drm; + u32 val, vmin, vmaj; + + pm_runtime_get_sync(drm->dev); + + regmap_read(dcif->regmap, DCIF_VER, &val); + + dcif->has_crc =3D val & DCIF_FEATURE_CRC; + + vmin =3D DCIF_VER_GET_MINOR(val); + vmaj =3D DCIF_VER_GET_MAJOR(val); + DRM_DEV_DEBUG(drm->dev, "DCIF version is %d.%d\n", vmaj, vmin); + + pm_runtime_put_sync(drm->dev); +} + +static const struct regmap_config dcif_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .fast_io =3D true, + .max_register =3D 0x20250, + .cache_type =3D REGCACHE_NONE, + .disable_locking =3D true, +}; + +static int dcif_probe(struct platform_device *pdev) +{ + struct dcif_dev *dcif; + struct drm_device *drm; + int ret; + int i; + + dcif =3D devm_drm_dev_alloc(&pdev->dev, &dcif_driver, struct dcif_dev, dr= m); + if (IS_ERR(dcif)) + return PTR_ERR(dcif); + + /* CPU 0 domain for interrupt control */ + dcif->cpu_domain =3D DCIF_CPU_DOMAIN; + + drm =3D &dcif->drm; + dev_set_drvdata(&pdev->dev, dcif); + + dcif->reg_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dcif->reg_base)) + return dev_err_probe(drm->dev, PTR_ERR(dcif->reg_base), + "failed to get reg base\n"); + + for (i =3D 0; i < 3; i++) { + dcif->irq[i] =3D platform_get_irq(pdev, i); + if (dcif->irq[i] < 0) + return dev_err_probe(drm->dev, dcif->irq[i], + "failed to get domain%d irq\n", i); + } + + dcif->regmap =3D devm_regmap_init_mmio(drm->dev, dcif->reg_base, &dcif_re= gmap_config); + if (IS_ERR(dcif->regmap)) + return dev_err_probe(drm->dev, PTR_ERR(dcif->regmap), + "failed to init DCIF regmap\n"); + + dcif->num_clks =3D devm_clk_bulk_get_all(drm->dev, &dcif->clks); + if (dcif->num_clks < 0) + return dev_err_probe(drm->dev, dcif->num_clks, + "cannot get required clocks\n"); + + dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); + + devm_pm_runtime_enable(drm->dev); + + ret =3D devm_request_irq(drm->dev, dcif->irq[dcif->cpu_domain], + dcif_irq_handler, 0, drm->driver->name, drm); + if (ret < 0) + return dev_err_probe(drm->dev, ret, "failed to install IRQ handler\n"); + + dcif_read_chip_info(dcif); + + ret =3D dcif_kms_prepare(dcif); + if (ret) + return ret; + + ret =3D drm_dev_register(drm, 0); + if (ret) + return dev_err_probe(drm->dev, ret, "failed to register drm device\n"); + + drm_client_setup(drm, NULL); + + return 0; +} + +static void dcif_remove(struct platform_device *pdev) +{ + struct dcif_dev *dcif =3D dev_get_drvdata(&pdev->dev); + struct drm_device *drm =3D &dcif->drm; + + drm_dev_unregister(drm); + + drm_atomic_helper_shutdown(drm); +} + +static void dcif_shutdown(struct platform_device *pdev) +{ + struct dcif_dev *dcif =3D dev_get_drvdata(&pdev->dev); + struct drm_device *drm =3D &dcif->drm; + + drm_atomic_helper_shutdown(drm); +} + +static int dcif_runtime_suspend(struct device *dev) +{ + struct dcif_dev *dcif =3D dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(dcif->num_clks, dcif->clks); + + return 0; +} + +static int dcif_runtime_resume(struct device *dev) +{ + struct dcif_dev *dcif =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_bulk_prepare_enable(dcif->num_clks, dcif->clks); + if (ret) { + dev_err(dev, "failed to enable clocks: %d\n", ret); + return ret; + } + + return 0; +} + +static int dcif_suspend(struct device *dev) +{ + struct dcif_dev *dcif =3D dev_get_drvdata(dev); + int ret; + + ret =3D drm_mode_config_helper_suspend(&dcif->drm); + if (ret < 0) + return ret; + + if (pm_runtime_suspended(dev)) + return 0; + + return dcif_runtime_suspend(dev); +} + +static int dcif_resume(struct device *dev) +{ + struct dcif_dev *dcif =3D dev_get_drvdata(dev); + int ret; + + if (!pm_runtime_suspended(dev)) { + ret =3D dcif_runtime_resume(dev); + if (ret < 0) + return ret; + } + + return drm_mode_config_helper_resume(&dcif->drm); +} + +static const struct dev_pm_ops dcif_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(dcif_suspend, dcif_resume) + SET_RUNTIME_PM_OPS(dcif_runtime_suspend, dcif_runtime_resume, NULL) +}; + +static const struct of_device_id dcif_dt_ids[] =3D { + { .compatible =3D "nxp,imx94-dcif", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, dcif_dt_ids); + +static struct platform_driver dcif_platform_driver =3D { + .probe =3D dcif_probe, + .remove =3D dcif_remove, + .shutdown =3D dcif_shutdown, + .driver =3D { + .name =3D "imx-dcif-drm", + .of_match_table =3D dcif_dt_ids, + .pm =3D pm_ptr(&dcif_pm_ops), + }, +}; +module_platform_driver(dcif_platform_driver); + +MODULE_AUTHOR("NXP Semiconductor"); +MODULE_DESCRIPTION("i.MX94 DCIF DRM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/imx/dcif/dcif-drv.h b/drivers/gpu/drm/imx/dcif= /dcif-drv.h new file mode 100644 index 0000000000000..9ba4f9b97ab40 --- /dev/null +++ b/drivers/gpu/drm/imx/dcif/dcif-drv.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* + * Copyright 2025 NXP + */ + +#ifndef __DCIF_DRV_H__ +#define __DCIF_DRV_H__ + +#include +#include + +#include +#include +#include +#include +#include + +#define DCIF_CPU_DOMAINS 3 + +struct dcif_dev { + struct drm_device drm; + void __iomem *reg_base; + + struct regmap *regmap; + int irq[DCIF_CPU_DOMAINS]; + + int num_clks; + struct clk_bulk_data *clks; + + struct drm_crtc crtc; + struct { + struct drm_plane primary; + struct drm_plane overlay; + } planes; + struct drm_encoder encoder; + + struct drm_pending_vblank_event *event; + + /* Implement crc */ + bool has_crc; + bool crc_is_enabled; + + /* CPU domain for interrupt control */ + int cpu_domain; +}; + +enum dcif_crc_source { + DCIF_CRC_SRC_NONE, + DCIF_CRC_SRC_FRAME, + DCIF_CRC_SRC_FRAME_ROI, +}; + +struct dcif_crc { + enum dcif_crc_source source; + struct drm_rect roi; +}; + +struct dcif_crtc_state { + struct drm_crtc_state base; + struct dcif_crc crc; + u32 bus_format; + u32 bus_flags; +}; + +static inline struct dcif_dev *to_dcif_dev(struct drm_device *drm_dev) +{ + return container_of(drm_dev, struct dcif_dev, drm); +} + +static inline struct dcif_dev *crtc_to_dcif_dev(struct drm_crtc *crtc) +{ + return to_dcif_dev(crtc->dev); +} + +static inline struct dcif_crtc_state *to_dcif_crtc_state(struct drm_crtc_s= tate *s) +{ + return container_of(s, struct dcif_crtc_state, base); +} + +irqreturn_t dcif_irq_handler(int irq, void *data); +int dcif_crtc_init(struct dcif_dev *dcif); +int dcif_plane_init(struct dcif_dev *dcif); +int dcif_kms_prepare(struct dcif_dev *dcif); + +#endif diff --git a/drivers/gpu/drm/imx/dcif/dcif-kms.c b/drivers/gpu/drm/imx/dcif= /dcif-kms.c new file mode 100644 index 0000000000000..69d999d178b0b --- /dev/null +++ b/drivers/gpu/drm/imx/dcif/dcif-kms.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "dcif-drv.h" + +static int dcif_kms_init(struct dcif_dev *dcif) +{ + struct drm_device *drm =3D &dcif->drm; + struct device_node *np =3D drm->dev->of_node; + struct drm_connector *connector; + struct drm_bridge *bridge; + int ret; + + ret =3D dcif_crtc_init(dcif); + if (ret) + return ret; + + bridge =3D devm_drm_of_get_bridge(drm->dev, np, 0, 0); + if (IS_ERR(bridge)) + return dev_err_probe(drm->dev, PTR_ERR(bridge), "Failed to find bridge\n= "); + + dcif->encoder.possible_crtcs =3D drm_crtc_mask(&dcif->crtc); + ret =3D drm_simple_encoder_init(drm, &dcif->encoder, DRM_MODE_ENCODER_NON= E); + if (ret) { + drm_err(drm, "failed to initialize encoder: %d\n", ret); + return ret; + } + + ret =3D drm_bridge_attach(&dcif->encoder, bridge, NULL, DRM_BRIDGE_ATTACH= _NO_CONNECTOR); + if (ret) { + drm_err(drm, "failed to attach bridge to encoder: %d\n", ret); + return ret; + } + + connector =3D drm_bridge_connector_init(drm, &dcif->encoder); + if (IS_ERR(connector)) { + drm_err(drm, "failed to initialize bridge connector: %d\n", ret); + return PTR_ERR(connector); + } + + ret =3D drm_connector_attach_encoder(connector, &dcif->encoder); + if (ret) + drm_err(drm, "failed to attach encoder to connector: %d\n", ret); + + return ret; +} + +static const struct drm_mode_config_funcs dcif_mode_config_funcs =3D { + .fb_create =3D drm_gem_fb_create, + .atomic_check =3D drm_atomic_helper_check, + .atomic_commit =3D drm_atomic_helper_commit, +}; + +static const struct drm_mode_config_helper_funcs dcif_mode_config_helpers = =3D { + .atomic_commit_tail =3D drm_atomic_helper_commit_tail_rpm, +}; + +int dcif_kms_prepare(struct dcif_dev *dcif) +{ + struct drm_device *drm =3D &dcif->drm; + int ret; + + ret =3D drmm_mode_config_init(drm); + if (ret) + return ret; + + ret =3D dcif_kms_init(dcif); + if (ret) + return ret; + + drm->mode_config.min_width =3D 1; + drm->mode_config.min_height =3D 1; + drm->mode_config.max_width =3D 1920; + drm->mode_config.max_height =3D 1920; + drm->mode_config.funcs =3D &dcif_mode_config_funcs; + drm->mode_config.helper_private =3D &dcif_mode_config_helpers; + + ret =3D drm_vblank_init(drm, 1); + if (ret < 0) { + drm_err(drm, "failed to initialize vblank: %d\n", ret); + return ret; + } + + drm_mode_config_reset(drm); + + drmm_kms_helper_poll_init(drm); + + return 0; +} diff --git a/drivers/gpu/drm/imx/dcif/dcif-plane.c b/drivers/gpu/drm/imx/dc= if/dcif-plane.c new file mode 100644 index 0000000000000..54ab8edd11e0c --- /dev/null +++ b/drivers/gpu/drm/imx/dcif/dcif-plane.c @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2025 NXP + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dcif-drv.h" +#include "dcif-reg.h" + +static const u32 dcif_primary_plane_formats[] =3D { + /* RGB */ + DRM_FORMAT_RGB565, + DRM_FORMAT_RGB888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_XRGB1555, + DRM_FORMAT_XRGB4444, + DRM_FORMAT_XRGB8888, + + /* Packed YCbCr */ + DRM_FORMAT_YUYV, + DRM_FORMAT_YVYU, + DRM_FORMAT_UYVY, + DRM_FORMAT_VYUY, +}; + +static const u32 dcif_overlay_plane_formats[] =3D { + /* RGB */ + DRM_FORMAT_RGB565, + DRM_FORMAT_RGB888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_XRGB1555, + DRM_FORMAT_XRGB4444, + DRM_FORMAT_XRGB8888, +}; + +static inline struct dcif_dev *plane_to_dcif_dev(struct drm_plane *plane) +{ + return to_dcif_dev(plane->dev); +} + +static inline dma_addr_t drm_plane_state_to_baseaddr(struct drm_plane_stat= e *state) +{ + struct drm_framebuffer *fb =3D state->fb; + struct drm_gem_dma_object *dma_obj; + unsigned int x =3D state->src.x1 >> 16; + unsigned int y =3D state->src.y1 >> 16; + + dma_obj =3D drm_fb_dma_get_gem_obj(fb, 0); + + return dma_obj->dma_addr + fb->offsets[0] + fb->pitches[0] * y + fb->form= at->cpp[0] * x; +} + +static int dcif_plane_get_layer_id(struct drm_plane *plane) +{ + return (plane->type =3D=3D DRM_PLANE_TYPE_PRIMARY) ? 0 : 1; +} + +static int dcif_plane_atomic_check(struct drm_plane *plane, struct drm_ato= mic_state *state) +{ + struct drm_plane_state *new_plane_state =3D drm_atomic_get_new_plane_stat= e(state, plane); + struct drm_plane_state *old_plane_state =3D drm_atomic_get_old_plane_stat= e(state, plane); + struct dcif_dev *dcif =3D plane_to_dcif_dev(plane); + struct drm_framebuffer *fb =3D new_plane_state->fb; + struct drm_framebuffer *old_fb =3D old_plane_state->fb; + struct drm_crtc_state *crtc_state; + + if (!fb) + return 0; + + crtc_state =3D drm_atomic_get_new_crtc_state(state, &dcif->crtc); + if (WARN_ON(!crtc_state)) + return -EINVAL; + + /* + * Force CRTC mode change if framebuffer stride or pixel format have chan= ged. + */ + if (plane->type =3D=3D DRM_PLANE_TYPE_PRIMARY && old_fb && + (fb->pitches[0] !=3D old_fb->pitches[0] || fb->format->format !=3D ol= d_fb->format->format)) + crtc_state->mode_changed =3D true; + + return drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, + DRM_PLANE_NO_SCALING, DRM_PLANE_NO_SCALING, true, + true); +} + +static void dcif_plane_atomic_update(struct drm_plane *plane, struct drm_a= tomic_state *state) +{ + struct drm_plane_state *new_state =3D drm_atomic_get_new_plane_state(stat= e, plane); + struct dcif_dev *dcif =3D plane_to_dcif_dev(plane); + int layer_id =3D dcif_plane_get_layer_id(plane); + struct drm_framebuffer *fb =3D new_state->fb; + u32 crtc_x, crtc_y, crtc_h, crtc_w; + u32 layer_fmt =3D 0, yuv_fmt =3D 0; + dma_addr_t baseaddr; + u32 reg; + + if (!fb) + return; + + crtc_x =3D new_state->crtc_x; + crtc_y =3D new_state->crtc_y; + crtc_h =3D new_state->crtc_h; + crtc_w =3D new_state->crtc_w; + + /* visible portion of plane on crtc */ + regmap_write(dcif->regmap, DCIF_CTRLDESC1(layer_id), + DCIF_CTRLDESC1_POSX(crtc_x) | DCIF_CTRLDESC1_POSY(crtc_y)); + regmap_write(dcif->regmap, DCIF_CTRLDESC2(layer_id), + DCIF_CTRLDESC2_WIDTH(crtc_w) | DCIF_CTRLDESC2_HEIGHT(crtc_h)); + + /* pitch size */ + reg =3D DCIF_CTRLDESC3_P_SIZE(2) | DCIF_CTRLDESC3_T_SIZE(2) | + DCIF_CTRLDESC3_PITCH(fb->pitches[0]); + regmap_write(dcif->regmap, DCIF_CTRLDESC3(layer_id), reg); + + /* address */ + baseaddr =3D drm_fb_dma_get_gem_addr(new_state->fb, new_state, 0); + + drm_dbg_kms(plane->dev, "[PLANE:%d:%s] fb address %pad, pitch 0x%08x\n", + plane->base.id, plane->name, &baseaddr, fb->pitches[0]); + + regmap_write(dcif->regmap, DCIF_CTRLDESC4(layer_id), baseaddr); + + /* Format */ + switch (fb->format->format) { + /* RGB Formats */ + case DRM_FORMAT_RGB565: + layer_fmt =3D CTRLDESCL0_FORMAT_RGB565; + break; + case DRM_FORMAT_RGB888: + layer_fmt =3D CTRLDESCL0_FORMAT_RGB888; + break; + case DRM_FORMAT_XRGB1555: + layer_fmt =3D CTRLDESCL0_FORMAT_ARGB1555; + break; + case DRM_FORMAT_XRGB4444: + layer_fmt =3D CTRLDESCL0_FORMAT_ARGB4444; + break; + case DRM_FORMAT_XBGR8888: + layer_fmt =3D CTRLDESCL0_FORMAT_ABGR8888; + break; + case DRM_FORMAT_XRGB8888: + layer_fmt =3D CTRLDESCL0_FORMAT_ARGB8888; + break; + + /* YUV Formats */ + case DRM_FORMAT_YUYV: + layer_fmt =3D CTRLDESCL0_FORMAT_YCBCR422; + yuv_fmt =3D CTRLDESCL0_YUV_FORMAT_VY2UY1; + break; + case DRM_FORMAT_YVYU: + layer_fmt =3D CTRLDESCL0_FORMAT_YCBCR422; + yuv_fmt =3D CTRLDESCL0_YUV_FORMAT_UY2VY1; + break; + case DRM_FORMAT_UYVY: + layer_fmt =3D CTRLDESCL0_FORMAT_YCBCR422; + yuv_fmt =3D CTRLDESCL0_YUV_FORMAT_Y2VY1U; + break; + case DRM_FORMAT_VYUY: + layer_fmt =3D CTRLDESCL0_FORMAT_YCBCR422; + yuv_fmt =3D CTRLDESCL0_YUV_FORMAT_Y2UY1V; + break; + + default: + dev_err(dcif->drm.dev, "Unknown pixel format 0x%x\n", fb->format->format= ); + break; + } + + if (plane->type =3D=3D DRM_PLANE_TYPE_OVERLAY && yuv_fmt =3D=3D CTRLDESCL= 0_YUV_FORMAT_Y2UY1V) { + dev_err(dcif->drm.dev, "Overlay plane could not support YUV format\n"); + return; + } + + reg =3D DCIF_CTRLDESC0_EN | DCIF_CTRLDESC0_SHADOW_LOAD_EN | + DCIF_CTRLDESC0_FORMAT(layer_fmt) | DCIF_CTRLDESC0_YUV_FORMAT(yuv_fm= t); + + /* Alpha */ + reg |=3D DCIF_CTRLDESC0_GLOBAL_ALPHA(new_state->alpha >> 8) | ALPHA_GLOBA= L; + + regmap_write(dcif->regmap, DCIF_CTRLDESC0(layer_id), reg); +} + +static void dcif_overlay_plane_atomic_disable(struct drm_plane *plane, + struct drm_atomic_state *state) +{ + struct dcif_dev *dcif =3D plane_to_dcif_dev(plane); + + regmap_update_bits(dcif->regmap, DCIF_CTRLDESC0(1), + DCIF_CTRLDESC0_EN | DCIF_CTRLDESC0_SHADOW_LOAD_EN, + DCIF_CTRLDESC0_SHADOW_LOAD_EN); +} + +static const struct drm_plane_helper_funcs dcif_primary_plane_helper_funcs= =3D { + .prepare_fb =3D drm_gem_plane_helper_prepare_fb, + .atomic_check =3D dcif_plane_atomic_check, + .atomic_update =3D dcif_plane_atomic_update, +}; + +static const struct drm_plane_helper_funcs dcif_overlay_plane_helper_funcs= =3D { + .atomic_check =3D dcif_plane_atomic_check, + .atomic_update =3D dcif_plane_atomic_update, + .atomic_disable =3D dcif_overlay_plane_atomic_disable, +}; + +static const struct drm_plane_funcs dcif_plane_funcs =3D { + .update_plane =3D drm_atomic_helper_update_plane, + .disable_plane =3D drm_atomic_helper_disable_plane, + .destroy =3D drm_plane_cleanup, + .reset =3D drm_atomic_helper_plane_reset, + .atomic_duplicate_state =3D drm_atomic_helper_plane_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_plane_destroy_state, +}; + +int dcif_plane_init(struct dcif_dev *dcif) +{ + const u32 supported_encodings =3D BIT(DRM_COLOR_YCBCR_BT601) | + BIT(DRM_COLOR_YCBCR_BT709) | + BIT(DRM_COLOR_YCBCR_BT2020); + const u32 supported_ranges =3D BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | + BIT(DRM_COLOR_YCBCR_FULL_RANGE); + int ret; + + /* primary plane */ + drm_plane_helper_add(&dcif->planes.primary, &dcif_primary_plane_helper_fu= ncs); + ret =3D drm_universal_plane_init(&dcif->drm, &dcif->planes.primary, 1, &d= cif_plane_funcs, + dcif_primary_plane_formats, + ARRAY_SIZE(dcif_primary_plane_formats), NULL, + DRM_PLANE_TYPE_PRIMARY, NULL); + if (ret) { + drm_err(&dcif->drm, "failed to initialize primary plane: %d\n", ret); + return ret; + } + + ret =3D drm_plane_create_color_properties(&dcif->planes.primary, supporte= d_encodings, + supported_ranges, DRM_COLOR_YCBCR_BT601, + DRM_COLOR_YCBCR_LIMITED_RANGE); + if (ret) + return ret; + + ret =3D drm_plane_create_alpha_property(&dcif->planes.primary); + if (ret) + return ret; + + /* overlay plane */ + drm_plane_helper_add(&dcif->planes.overlay, &dcif_overlay_plane_helper_fu= ncs); + ret =3D drm_universal_plane_init(&dcif->drm, &dcif->planes.overlay, 1, &d= cif_plane_funcs, + dcif_overlay_plane_formats, + ARRAY_SIZE(dcif_overlay_plane_formats), NULL, + DRM_PLANE_TYPE_OVERLAY, NULL); + if (ret) { + drm_err(&dcif->drm, "failed to initialize overlay plane: %d\n", ret); + return ret; + } + + return drm_plane_create_alpha_property(&dcif->planes.overlay); +} diff --git a/drivers/gpu/drm/imx/dcif/dcif-reg.h b/drivers/gpu/drm/imx/dcif= /dcif-reg.h new file mode 100644 index 0000000000000..acf9e3071aa52 --- /dev/null +++ b/drivers/gpu/drm/imx/dcif/dcif-reg.h @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* + * Copyright 2025 NXP + */ +#ifndef __DCIF_REG_H__ +#define __DCIF_REG_H__ + +#include + +/* Version ID Register */ +#define DCIF_VER 0x0 +#define DCIF_VER_GET_FEATURE(x) FIELD_GET(GENMASK(15, 0), x) +#define DCIF_VER_GET_MINOR(x) FIELD_GET(GENMASK(23, 16), x) +#define DCIF_VER_GET_MAJOR(x) FIELD_GET(GENMASK(31, 24), x) +#define DCIF_FEATURE_CRC BIT(1) + +/* Parameter Registers */ +#define DCIF_PAR_0 0x4 +#define DCIF_PAR_0_LAYER_NUM(x) FIELD_PREP(GENMASK(3, 0), x) +#define DCIF_PAR_0_DOMAIN_NUM(x) FIELD_PREP(GENMASK(5, 4), x) +#define DCIF_PAR_0_AXI_DATA_WIDTH(x) FIELD_PREP(GENMASK(7, 6), x) +#define DCIF_PAR_0_CLUT_RAM_NUM(x) FIELD_PREP(GENMASK(11, 8), x) +#define DCIF_PAR_0_CSC_NUM(x) FIELD_PREP(GENMASK(13, 12), x) +#define DCIF_PAR_0_CRC_REGION_NUM(x) FIELD_PREP(GENMASK(18, 16), x) +#define DCIF_PAR_0_BACKUP(x) FIELD_PREP(GENMASK(31, 28), x) + +#define DCIF_PAR_1 0x8 +#define DCIF_PAR_1_LAYER0_FIFO_SIZE(x) FIELD_PREP(GENMASK(3, 0), x) +#define DCIF_PAR_1_LAYER1_FIFO_SIZE(x) FIELD_PREP(GENMASK(7, 4), x) + +/* Display Control and Parameter Registers */ +#define DCIF_DISP_CTRL 0x10 +#define DCIF_DISP_CTRL_DISP_ON BIT(0) +#define DCIF_DISP_CTRL_AXI_RD_HOLD BIT(30) +#define DCIF_DISP_CTRL_SW_RST BIT(31) +#define DCIF_DISP_PAR 0x14 +#define DCIF_DISP_PAR_BGND_B(x) FIELD_PREP(GENMASK(7, 0), x) +#define DCIF_DISP_PAR_BGND_G(x) FIELD_PREP(GENMASK(15, 8), x) +#define DCIF_DISP_PAR_BGND_R(x) FIELD_PREP(GENMASK(23, 16), x) +#define DCIF_DISP_SIZE 0x18 +#define DCIF_DISP_SIZE_DISP_WIDTH(x) FIELD_PREP(GENMASK(11, 0), x) +#define DCIF_DISP_SIZE_DISP_HEIGHT(x) FIELD_PREP(GENMASK(27, 16), x) + +/* Display Status Registers */ +#define DCIF_DISP_SR0 0x1C +#define DCIF_DISP_SR0_AXI_RD_PEND(x) FIELD_PREP(GENMASK(4, 0), x) +#define DCIF_DISP_SR0_DPI_BUSY(x) FIELD_PREP(GENMASK(14, 14), x) +#define DCIF_DISP_SR0_AXI_RD_BUSY(x) FIELD_PREP(GENMASK(15, 15), x) +#define DCIF_DISP_SR0_TXFIFO_CNT(x) FIELD_PREP(GENMASK(23, 16), x) + +#define DCIF_DISP_SR1 0x20 +#define DCIF_DISP_SR1_H_CNT(x) FIELD_PREP(GENMASK(11, 0), x) +#define DCIF_DISP_SR1_V_CNT(x) FIELD_PREP(GENMASK(27, 16), x) + +/* Interrupt Enable and Status Registers, n=3D0-2*/ +#define DCIF_IE0(n) (0x24 + (n) * 0x10000) +#define DCIF_IS0(n) (0x28 + (n) * 0x10000) +#define DCIF_INT0_VSYNC BIT(0) +#define DCIF_INT0_UNDERRUN BIT(1) +#define DCIF_INT0_VS_BLANK BIT(2) +#define DCIF_INT0_HIST_DONE BIT(5) +#define DCIF_INT0_CRC_ERR BIT(6) +#define DCIF_INT0_CRC_ERR_SAT BIT(7) + +#define DCIF_IE1(n) (0x2C + (n) * 0x10000) +#define DCIF_IS1(n) (0x30 + (n) * 0x10000) +#define DCIF_INT1_FIFO_PANIC0 BIT(0) +#define DCIF_INT1_FIFO_PANIC1 BIT(1) +#define DCIF_INT1_DMA_ERR0 BIT(8) +#define DCIF_INT1_DMA_ERR1 BIT(9) +#define DCIF_INT1_DMA_DONE0 BIT(16) +#define DCIF_INT1_DMA_DONE1 BIT(17) +#define DCIF_INT1_FIFO_EMPTY0 BIT(24) +#define DCIF_INT1_FIFO_EMPTY1 BIT(25) + +/* DPI Control and Sync Parameter Registers */ +#define DCIF_DPI_CTRL 0x40 +#define DCIF_DPI_CTRL_HSYNC_POL_LOW BIT(0) +#define DCIF_DPI_CTRL_VSYNC_POL_LOW BIT(1) +#define DCIF_DPI_CTRL_DE_POL_LOW BIT(2) +#define DCIF_DPI_CTRL_PCLK_EDGE_FALLING BIT(3) +#define DCIF_DPI_CTRL_POL_MASK GENMASK(3, 0) +#define DCIF_DPI_CTRL_DATA_INV(x) FIELD_PREP(GENMASK(4, 4), x) +#define DCIF_DPI_CTRL_DEF_BGND_EN(x) FIELD_PREP(GENMASK(5, 5), x) +#define DCIF_DPI_CTRL_FETCH_OPT(x) FIELD_PREP(GENMASK(9, 8), x) +#define DCIF_DPI_CTRL_DISP_MODE(x) FIELD_PREP(GENMASK(13, 12), x) +#define DCIF_DPI_CTRL_DATA_PATTERN_MASK GENMASK(18, 16) +#define DCIF_DPI_CTRL_DATA_PATTERN(x) FIELD_PREP(GENMASK(18, 16), x) +#define PATTERN_RGB888 0 +#define PATTERN_RBG888 1 +#define PATTERN_GBR888 2 +#define PATTERN_GRB888 3 +#define PATTERN_BRG888 4 +#define PATTERN_BGR888 5 +#define PATTERN_RGB555 6 +#define PATTERN_RGB565 7 + +#define DCIF_DPI_HSYN_PAR 0x44 +#define DCIF_DPI_HSYN_PAR_FP_H(x) FIELD_PREP(GENMASK(11, 0), x) +#define DCIF_DPI_HSYN_PAR_BP_H(x) FIELD_PREP(GENMASK(27, 16), x) + +#define DCIF_DPI_VSYN_PAR 0x48 +#define DCIF_DPI_VSYN_PAR_FP_V(x) FIELD_PREP(GENMASK(11, 0), x) +#define DCIF_DPI_VSYN_PAR_BP_V(x) FIELD_PREP(GENMASK(27, 16), x) + +#define DCIF_DPI_VSYN_HSYN_WIDTH 0x4C +#define DCIF_DPI_VSYN_HSYN_WIDTH_PW_H(x) FIELD_PREP(GENMASK(11, 0), x) +#define DCIF_DPI_VSYN_HSYN_WIDTH_PW_V(x) FIELD_PREP(GENMASK(27, 16), x) + +/* Control Descriptor Registers, n=3D0-1*/ +#define DCIF_CTRLDESC0(n) (0x10000 + (n) * 0x10000) +#define DCIF_CTRLDESC0_AB_MODE(x) FIELD_PREP(GENMASK(1, 0), x) +#define ALPHA_EMBEDDED 0 +#define ALPHA_GLOBAL 1 +#define DCIF_CTRLDESC0_YUV_FORMAT_MASK GENMASK(15, 14) +#define DCIF_CTRLDESC0_YUV_FORMAT(x) FIELD_PREP(GENMASK(15, 14), x) +#define CTRLDESCL0_YUV_FORMAT_Y2VY1U 0x0 +#define CTRLDESCL0_YUV_FORMAT_Y2UY1V 0x1 +#define CTRLDESCL0_YUV_FORMAT_VY2UY1 0x2 +#define CTRLDESCL0_YUV_FORMAT_UY2VY1 0x3 +#define DCIF_CTRLDESC0_GLOBAL_ALPHA(x) FIELD_PREP(GENMASK(23, 16), x) +#define DCIF_CTRLDESC0_FORMAT_MASK GENMASK(27, 24) +#define DCIF_CTRLDESC0_FORMAT(x) FIELD_PREP(GENMASK(27, 24), x) +#define CTRLDESCL0_FORMAT_RGB565 0x4 +#define CTRLDESCL0_FORMAT_ARGB1555 0x5 +#define CTRLDESCL0_FORMAT_ARGB4444 0x6 +#define CTRLDESCL0_FORMAT_YCBCR422 0x7 +#define CTRLDESCL0_FORMAT_RGB888 0x8 +#define CTRLDESCL0_FORMAT_ARGB8888 0x9 +#define CTRLDESCL0_FORMAT_ABGR8888 0xa +#define DCIF_CTRLDESC0_SHADOW_LOAD_EN BIT(30) +#define DCIF_CTRLDESC0_EN BIT(31) + +#define DCIF_CTRLDESC1(n) (0x10004 + (n) * 0x10000) +#define DCIF_CTRLDESC1_POSX(x) FIELD_PREP(GENMASK(11, 0), x) +#define DCIF_CTRLDESC1_POSY(x) FIELD_PREP(GENMASK(27, 16), x) + +#define DCIF_CTRLDESC2(n) (0x10008 + (n) * 0x10000) +#define DCIF_CTRLDESC2_WIDTH(x) FIELD_PREP(GENMASK(11, 0), x) +#define DCIF_CTRLDESC2_HEIGHT(x) FIELD_PREP(GENMASK(27, 16), x) + +#define DCIF_CTRLDESC3(n) (0x1000C + (n) * 0x10000) +#define DCIF_CTRLDESC3_PITCH(x) FIELD_PREP(GENMASK(15, 0), x) +#define DCIF_CTRLDESC3_T_SIZE(x) FIELD_PREP(GENMASK(17, 16), x) +#define DCIF_CTRLDESC3_P_SIZE(x) FIELD_PREP(GENMASK(22, 20), x) + +#define DCIF_CTRLDESC4(n) (0x10010 + (n) * 0x10000) +#define DCIF_CTRLDESC4_ADDR(x) FIELD_PREP(GENMASK(31, 0), x) + +#define DCIF_CTRLDESC5(n) (0x10014 + (n) * 0x10000) +#define DCIF_CTRLDESC6(n) (0x10018 + (n) * 0x10000) +#define DCIF_CTRLDESC6_BCLR_B(x) FIELD_PREP(GENMASK(7, 0), x) +#define DCIF_CTRLDESC6_BCLR_G(x) FIELD_PREP(GENMASK(15, 8), x) +#define DCIF_CTRLDESC6_BCLR_R(x) FIELD_PREP(GENMASK(23, 16), x) +#define DCIF_CTRLDESC6_BCLR_A(x) FIELD_PREP(GENMASK(31, 24), x) + +/* CLUT control Register */ +#define DCIF_CLUT_CTRL 0x1003C +#define DCIF_CLUT_CTRL_CLUT0_SEL(x) FIELD_PREP(GENMASK(0, 0), x) +#define DCIF_CLUT_CTRL_CLUT1_SEL(x) FIELD_PREP(GENMASK(3, 3), x) +#define DCIF_CLUT_CTRL_CLUT_MUX(x) FIELD_PREP(GENMASK(29, 28), x) +#define DCIF_CLUT_CTRL_CLUT_SHADOW_LOAD_EN(x) FIELD_PREP(GENMASK(31, 31)= , x) + +/* FIFO Panic Threshold Register, n=3D0-1 */ +#define DCIF_PANIC_THRES(n) (0x10040 + (n) * 0x10000) +#define DCIF_PANIC_THRES_LOW_MASK GENMASK(11, 0) +#define DCIF_PANIC_THRES_LOW(x) FIELD_PREP(GENMASK(11, 00), x) +#define DCIF_PANIC_THRES_HIGH_MASK GENMASK(27, 16) +#define DCIF_PANIC_THRES_HIGH(x) FIELD_PREP(GENMASK(27, 16), x) +#define DCIF_PANIC_THRES_REQ_EN BIT(31) +#define PANIC0_THRES_MAX 511 + +/* Layer Status Register 0, n=3D0-1 */ +#define DCIF_LAYER_SR0(n) (0x10044 + (n) * 0x10000) +#define DCIF_LAYER_SR0_L0_FIFO_CNT_MASK GENMASK(9, 0) +#define DCIF_LAYER_SR0_L0_FIFO_CNT(x) FIELD_PREP(GENMASK(9, 0), x) + +/* Color Space Conversion Control and Coefficient Registers for Layer 0 */ +#define DCIF_CSC_CTRL_L0 0x10050 +#define DCIF_CSC_CTRL_L0_CSC_EN BIT(0) +#define DCIF_CSC_CTRL_L0_CSC_MODE_YCBCR2RGB BIT(1) + +#define DCIF_CSC_COEF0_L0 0x10054 +#define DCIF_CSC_COEF0_L0_A1(x) FIELD_PREP_CONST(GENMASK(10, 0), x) +#define DCIF_CSC_COEF0_L0_A2(x) FIELD_PREP_CONST(GENMASK(26, 16), x) + +#define DCIF_CSC_COEF1_L0 0x10058 +#define DCIF_CSC_COEF1_L0_A3(x) FIELD_PREP_CONST(GENMASK(10, 0), x) +#define DCIF_CSC_COEF1_L0_B1(x) FIELD_PREP_CONST(GENMASK(26, 16), x) + +#define DCIF_CSC_COEF2_L0 0x1005C +#define DCIF_CSC_COEF2_L0_B2(x) FIELD_PREP_CONST(GENMASK(10, 0), x) +#define DCIF_CSC_COEF2_L0_B3(x) FIELD_PREP_CONST(GENMASK(26, 16), x) + +#define DCIF_CSC_COEF3_L0 0x10060 +#define DCIF_CSC_COEF3_L0_C1(x) FIELD_PREP_CONST(GENMASK(10, 0), x) +#define DCIF_CSC_COEF3_L0_C2(x) FIELD_PREP_CONST(GENMASK(26, 16), x) + +#define DCIF_CSC_COEF4_L0 0x10064 +#define DCIF_CSC_COEF4_L0_C3(x) FIELD_PREP_CONST(GENMASK(10, 0), x) +#define DCIF_CSC_COEF4_L0_D1(x) FIELD_PREP_CONST(GENMASK(24, 16), x) + +#define DCIF_CSC_COEF5_L0 0x10068 +#define DCIF_CSC_COEF5_L0_D2(x) FIELD_PREP_CONST(GENMASK(8, 0), x) +#define DCIF_CSC_COEF5_L0_D3(x) FIELD_PREP_CONST(GENMASK(24, 16), x) + +/* CRC Control, Threshold, and Histogram Coefficient Registers */ +#define DCIF_CRC_CTRL 0x20100 +#define DCIF_CRC_CTRL_CRC_EN(x) (1 << (x)) +#define DCIF_CRC_CTRL_HIST_REGION_SEL(x) FIELD_PREP(GENMASK(17, 16), x) +#define DCIF_CRC_CTRL_HIST_MODE BIT(21) +#define DCIF_CRC_CTRL_HIST_TRIG BIT(22) +#define DCIF_CRC_CTRL_HIST_EN BIT(23) +#define DCIF_CRC_CTRL_CRC_MODE BIT(28) +#define DCIF_CRC_CTRL_CRC_TRIG BIT(29) +#define DCIF_CRC_CTRL_CRC_ERR_CNT_RST BIT(30) +#define DCIF_CRC_CTRL_CRC_SHADOW_LOAD_EN BIT(31) + +#define DCIF_CRC_THRES 0x20104 +#define DCIF_CRC_THRES_CRC_THRESHOLD_MASK GENMASK(31, 0) +#define DCIF_CRC_THRES_CRC_THRESHOLD(x) FIELD_PREP(GENMASK(31, 0), x) + +#define DCIF_CRC_HIST_COEF 0x20108 +#define DCIF_CRC_HIST_COEF_HIST_WB_MASK GENMASK(7, 0) +#define DCIF_CRC_HIST_COEF_HIST_WB(x) FIELD_PREP(GENMASK(7, 0), x) +#define DCIF_CRC_HIST_COEF_HIST_WG_MASK GENMASK(15, 8) +#define DCIF_CRC_HIST_COEF_HIST_WG(x) FIELD_PREP(GENMASK(15, 8), x) +#define DCIF_CRC_HIST_COEF_HIST_WR_MASK GENMASK(23, 16) +#define DCIF_CRC_HIST_COEF_HIST_WR(x) FIELD_PREP(GENMASK(23, 16), x) + +#define DCIF_CRC_ERR_CNT 0x2010C +#define DCIF_CRC_ERR_CNT_CRC_ERR_CNT_MASK GENMASK(31, 0) +#define DCIF_CRC_ERR_CNT_CRC_ERR_CNT(x) FIELD_PREP(GENMASK(31, 0), x) + +#define DCIF_CRC_SR 0x20110 +#define DCIF_CRC_SR_HIST_CNT_SAT_MASK BIT(13) +#define DCIF_CRC_SR_HIST_CNT_SAT(x) FIELD_PREP(GENMASK(13, 13), x) +#define DCIF_CRC_SR_HIST_SAT_MASK BIT(14) +#define DCIF_CRC_SR_HIST_SAT(x) FIELD_PREP(GENMASK(14, 14), x) +#define DCIF_CRC_SR_HIST_BUSY_MASK BIT(15) +#define DCIF_CRC_SR_HIST_BUSY(x) FIELD_PREP(GENMASK(15, 15), x) +#define DCIF_CRC_SR_CRC_STATUS_MASK BIT(31) +#define DCIF_CRC_SR_CRC_STATUS(x) FIELD_PREP(GENMASK(31, 31), x) + +#define DCIF_CRC_HIST_CNT_B(n) (0x20114 + (n) * 4) +#define DCIF_B_BIN_CNT_MASK GENMASK(20, 0) +#define DCIF_B_BIN_CNT(x) FIELD_PREP(GENMASK(20, 0), x) + +/* CRC Region Position, Size, Value, and Expected Value Registers, n=3D0-3= */ +#define DCIF_CRC_POS_R(n) (0x20214 + (n) * 0x10) +#define DCIF_CRC_POS_CRC_HOR_POS(x) FIELD_PREP(GENMASK(11, 0), x) +#define DCIF_CRC_POS_CRC_VER_POS(x) FIELD_PREP(GENMASK(27, 16), x) + +#define DCIF_CRC_SIZE_R(n) (0x20218 + (n) * 0x10) +#define DCIF_CRC_SIZE_CRC_HOR_SIZE(x) FIELD_PREP(GENMASK(11, 0), x) +#define DCIF_CRC_SIZE_CRC_VER_SIZE(x) FIELD_PREP(GENMASK(27, 16), x) + +#define DCIF_CRC_VAL_R(n) (0x2021C + (n) * 0x10) +#define DCIF_CRC_VAL_CRC_VAL_MASK GENMASK(31, 0) +#define DCIF_CRC_VAL_CRC_VAL(x) FIELD_PREP(GENMASK(31, 0), x) + +#define DCIF_CRC_EXP_VAL_R(n) (0x20220 + (n) * 0x10) +#define DCIF_CRC_EXP_VAL_CRC_EXP_VAL_MASK GENMASK(31, 0) +#define DCIF_CRC_EXP_VAL_CRC_EXP_VAL(x) FIELD_PREP(GENMASK(31, 0), x) + +#endif /* __DCIF_REG_H__ */ --=20 2.51.0 From nobody Thu Apr 2 12:13:32 2026 Received: from DB3PR0202CU003.outbound.protection.outlook.com (mail-northeuropeazon11010027.outbound.protection.outlook.com [52.101.84.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C34361D5160; Wed, 4 Mar 2026 11:35:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.84.27 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624111; cv=fail; b=bgCjBrp0SkJNsHXtq5mubwv0nKu9H78Dq4B3NnNIGLIhryN5NQCrBnF1tt890suCCoAhWEflKOb0Q4G4z4w0dX+Ia0F1x8ErUQtssn6KZeilFzKuW5HjpgQ04d89b8APuM9NgbQJWA3zG9ps9OgBOGv+XN65IbaUKuwTscj9h8w= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624111; c=relaxed/simple; bh=MhOx0hDhbrkEGtzeY9OBn8nnaTYqJHLoRJdmhORwt+c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=NxNEBP6DcpzxcwUNGFbALup1+6lQBXxSdoWd7dPA3D4qBJgKS8yNBCDaQbHw9dvSOcr58S7ccCLVDDgPK49IgGg0oXgSz4sXZ6n6nQdfnBO2wT1fT8ST5S9j1IGu2stSIrrt1oOCLv09yKACpco67H/AQ34+PLC0uSdIbBZR2hE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=RodNgIWT; arc=fail smtp.client-ip=52.101.84.27 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="RodNgIWT" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=m+YyPOehFa116k2mhmbqPDFxpZxbDhSxGJDPasH4OX/wkpzdKTh/FfolLhghSx2ihx4C3EXpXkA71FiKd6HclCcieAJXY7YiauwF5/Cg/CC4YFlBfyFskDoeYX+uxiP3VWYGqKTKq8Le163wM5mIcZbfa7UwzUHxqUlwVZ2E+A6UhRcrk3dBx7FYJXhENHd+nXjbU6Li4mKRfYgKnicLudpzb5RyHq0haJnKcJ7VN+xz7r8NqLwDvm3wID8R2K/uloSqTDi5nOIoQrjOAIF7DNBo/k/5G6nUhyIz/HkAA+56nelBwSlOH9RuzCk1J6yL7dHqibZK5WTYiJ4CF38I1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uDC1H0m+9mkhYatIZ7i7+LeDmjpEtDu+YDWXYIYAttg=; b=u0n32+kzPzUVWwwJ5M7SQWaKDUX0pf8qON0VICjzKl3XQlZ/DCs72YAwmFsrT0fUmvzJetSqA3g6UwbHotGVWSUohc+bmOwuR0yAh/LiHNqJA/RUTF1amrWid4IuLM5cPugAvXN+vTi9LJCg7eI3+PqMQPrwd4+zzStXwc80KHG7kkxzZKcPt/1o5MWpdK/B7y7tZfjb0qKRReFUQaAtWtfBmWHSO+agogl5NjxfUtTCipxhNXe4n1jQ1tDH5glxFJw4YwhKbiuSOxDmaGrnEK2VFe4qjAUIuw0o/khVnwSjnA3FITOkeoTrDxvEL8XNeYW/gHALNSJAxiyQuEQdmA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uDC1H0m+9mkhYatIZ7i7+LeDmjpEtDu+YDWXYIYAttg=; b=RodNgIWTEDxdGezl/yJBiJ0Ngcc6UVIuIVTygvEjzcv5mHLBj7zmMjCf/klQwrig+KukDOVl22bvfO2Og4dHXrxp/fVeSYbcbYZgExlgY7yBmkuZudxdlK1rbpw6At58y69qpAMZy0zYt41c4sXC+UtktrNd7FfmaoleLY9X1RIeeXgPTCT9RWnpqKqZvBAQi3m44NpGGXiDA5Bi915BCw74qqzUlEKDyn4LGUqo3K9Kq1im7/PnWB8b6CMFYiU90I3xr2Dz73MOkbUxHd1tlFQQd9b5oHmEWksH4Lad3x2xjaEoESrbwLEg4cTkuUPweWqLZYOPZeAuK+NZqL8+DA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) by GV1PR04MB10522.eurprd04.prod.outlook.com (2603:10a6:150:1ce::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9678.17; Wed, 4 Mar 2026 11:35:03 +0000 Received: from GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2]) by GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2%5]) with mapi id 15.20.9654.022; Wed, 4 Mar 2026 11:35:03 +0000 From: Laurentiu Palcu To: imx@lists.linux.dev, Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: dri-devel@lists.freedesktop.org, Ying Liu , Laurentiu Palcu , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 6/9] dt-bindings: clock: nxp,imx95-blk-ctl: Add ldb child node Date: Wed, 4 Mar 2026 11:34:15 +0000 Message-ID: <20260304-dcif-upstreaming-v8-6-bec5c047edd4@oss.nxp.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> References: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AM8P251CA0007.EURP251.PROD.OUTLOOK.COM (2603:10a6:20b:21b::12) To GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV1PR04MB9135:EE_|GV1PR04MB10522:EE_ X-MS-Office365-Filtering-Correlation-Id: e5065cc8-cc66-4237-a463-08de79e213ca X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|19092799006|376014|366016|921020; X-Microsoft-Antispam-Message-Info: MnZ8FgguxVipBFj7ZKk0ur6LCVPjI76EuiBX7brEv+IlEE3EoqucsaBr9EeTDSC4uhIbtyn9eULBupb8oMNXIBuGv4UcZeI5PQCcfvDfFyItoUbgeF+0Y9btDC6FotOzCTqKxGvTnDP4Vg7d5iNsEZDWp2Ci/Vm8ilU86XkOerWzXdnX27r/HdkA0x1AYKbgaoL+AfIwSsahvc+vEuQcEfWiUdW7PY+0WvFan+AIo08SauVlOhRADMD10xL3USR0haXNlt0l4V9c4X13NTIAYyRenXtDHeKPv4/rqBHnbgWR1aAijzJoA8sV1w0ENIVTVonR/u+H8bub2uQVWjMUiDxJdo5YowSlsTUub5R/gulviom4rU+KMKEc4upoQFA8yuTJvaCiylJmSayFWJlxTZCIOnIq+RVsn6VyhSjk2aSLs5m1mdiOmi8naOHysuOcXxqBV+Q/QAvYubSa+qftioaHIrGQfiOGbDyhvXZbuaLGKSOoumzcQ/jFv72vvCpnjcPjyGyapq9GVabxCzMFMOD1PbKpZtdJaHX4c520mjs5i81TszYYO2gPhScwVkOsSyL102F3C8r3aPH9KHU41aK9B/xLQ/V3aSCbPdwTaeaorUQny4wnL5M1j65tTLtp7FPFINCh+/8qRZlnW/CU2Zbea+AZ+YihesNJJ+Q7Q+OdMs3agNP49o/hpXoVHbFzlFFfAqRcWOxocFCWpdqGmXrkVAnLzWZfTzhz9/PyesWFTg+3BWyCJs33gIUYHNJbpjbNvNYBI74tBT85jMqC2A== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:GV1PR04MB9135.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(19092799006)(376014)(366016)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?ak5oMkQyQWtRYktoM0JxeHNPVUx0dXlHN2NhbjF1QmFXd0YrUWhIeW5RS3lU?= =?utf-8?B?Z1ZDTThOY2dvMEZyMDVxZ1RqNVNUTkl5N3JCcENwY0h1bUdPNm9SRmJsZnlL?= =?utf-8?B?TjZxUjlCYUVFU2l1NVhTclRDRmVQSGlvM1I0eTVnVE9JbGZCV2RIbUNmbzA5?= =?utf-8?B?VEZaNnZBU3dOS1c1aGFBUlEvREY5c0VCQjZXNGtzUkNHVm1XQ0pBaU5YUnNn?= =?utf-8?B?a3lvOGdyNitFRDJhMHJaSDlvU04wN3BDNkloUEZLM3JIQkl6K1ZFMHBCMmJF?= =?utf-8?B?Zm0rZUNZWElzclZPMUtFK0N0MVgwV3VVOVhsVDcrVWhOeE1kU0dJSXJqZ2l1?= =?utf-8?B?Nk5ieloxY0tUNXFta0FGS2pWaDVmdDllbHFkYkc2ZWh5WFM5RXpmSE5mR29U?= =?utf-8?B?a2xUeFdITzFFSGNJTitoL2lmZ25CTzhHL3ZqaC9xY1NhdlVoK2NXK0VqS3hj?= =?utf-8?B?clJCWVFJOHliNDlObU93VTU0bmdidmp6VjRjYWxMVXRmUVZZNVY5OUF5anc3?= =?utf-8?B?aDEzMnF0Z1dub2ZLaExIWGUvQi9ycjAzRExTbUJaaG93VXhzdDdjNXpZdmor?= =?utf-8?B?eG10cS8ybmJkUU1yMUdzdFhKTjhQZmtzNGlCSVMyRWhiL1ExZkdJTmhBL3Ni?= =?utf-8?B?UWpCN3VzWDJpa3V1cm1Fc2RsWGN1U0NCNGNlbXNMSzFwcTFYd2MzRlFTR1pZ?= =?utf-8?B?N3pDTDBNbVNJUFRZN1BOU2c5YlI4VHgvc2w3ZVgvUHR2Y1QrUThSRDBUWlh1?= =?utf-8?B?ZG82SysweWtrS1lIUG9kQS9EY2x1dE5iaElGWk1FMC9zVUNFRGh6QnBUREdk?= =?utf-8?B?dU9VdjdNQmF2amlUTWxCYTgwcGg4c3lBOUpYTFBDUGorb1EzQ2k0NlQwVEkx?= =?utf-8?B?SXQ3eXFvNTRHRy9UY2VwRkVSbmY3UWJWZWVSV2pSRitucVJCRkR4NzdJZlF5?= =?utf-8?B?emdWSHUzSUdWa3ErTXIzZVJzZTdhSUpiaWVHeHlEOXVOZENSWUZFY2lVQzVq?= =?utf-8?B?Y2xaeFVJZStKWGNHR1A0QjBaaWd1Wjd4RTBkc0RGemVZSXM3YnNVRUtwOFQr?= =?utf-8?B?blg0blgwTlV5SnkxQ2FoSHVUdmNadE5idzYrUmd3TzA5MmlmQzNtdUswcHZN?= =?utf-8?B?WG1pZWxsRWFBcjFwdE1MUmVaSXkrMDhiaTV2QkhuZGx4TFhSc3dIVWFseWcr?= =?utf-8?B?Z2Y3WDZzRkdhWHlLWmxiU01BMWhYVzdzVEVXMXNmZENGOVhPckk2enlkeXJq?= =?utf-8?B?bDVPUlRsb2xOK1RYdFNDTkxLWjU1WjlzYk9iMzF0bjFJSlJEWFFKN2tFaXV0?= =?utf-8?B?MjRFQytMUmNPaG9WRUhQcDNNR0duWWlqeHR6WnNtcXNHOWpGVmVFc1BKNTZj?= =?utf-8?B?T29uYmcxdXo3MUptOG9PZ1pRc1BEaFg4U3dRcENPRlZpUDc3ekV1MTBTQ3gy?= =?utf-8?B?aWFBa1EyMDlPRjdtMHpyL0VnUDdYbXhKQVp5YWEvUklBNTFPWnloMHVoM3Bk?= =?utf-8?B?VU5JdE5Ia3FURUZYYUkzNXJ4ejRNWVJhV2p6MzhDeFgwbU1UNVZ5WWY3SmI1?= =?utf-8?B?YzF4VWxGcE5RT1dIN213dFNqS0grbUdnY1ZuZ0MxZUlYNFVkaUZtbHpCQ1R0?= =?utf-8?B?Yy8zWXcxdndQblZnQWpBQUZPbjNnY1hsbGxwK2wyOEw2VDV3U2ptYmZBUkZs?= =?utf-8?B?cUs0U1R4QWc1ZTRFNU9RQ3JIOFkvZWhHa3ZqZ0FKWWdpdHZHdUdhUzFudGl4?= =?utf-8?B?YjZUVjBSSnVjMlljUW8zMjN2V0ZydFZiRjZFMWgrSTAveXZVNjN0TGJ0ck1Z?= =?utf-8?B?Q0NlMHpBNi9BZGNNYnEzcmRGQUwxQzR4OXNrZlVGblZLREJVa2NPcHQwaWZj?= =?utf-8?B?VDNYK3hZekF2ei9iNU8xNS9WOW1peUoyRWFSWWN3NGFhOVp6YU91STQzdGRG?= =?utf-8?B?MlRHUXozT29nNnYzOVRTWU5qdGVHdWFxY05FQzV0M3ZpdFdjZjV5eEdNSFow?= =?utf-8?B?ZjhRUG5KbTUyT244dWVXeFlFYlRpWUJuQm9kSTA0Yzh1WDN0Y2hHT251cXhr?= =?utf-8?B?ODNmNklPMUNoMHF3QXJINWdGOThtS3lvU0taUnBsNElZS0VxbU1Ld1J2S2tN?= =?utf-8?B?S2lWSWpGWTh5c0RGcTAxZ1RNTGRuenRiZTh6QnFhb1NvOFVvam5nSXhGRlRF?= =?utf-8?B?bWJpRHJuVHVXTDkza0J0MFlIYkZZaEJwdGI3c3daR3d4WVZuNk5LSW9LbGRU?= =?utf-8?B?TENweC8veEhVclgrL2ZPOVd1Z1YrZWFVNE50aVNtS1ovU2xmRXBhNmgveGZk?= =?utf-8?B?eVhTWUFoUEtNSEZzbS9GRWQ0ek5QckFuMExhZ1drcDdlTUVPQkhiZGxGOHV3?= =?utf-8?Q?u82YJqx/m+4Pr77s=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: e5065cc8-cc66-4237-a463-08de79e213ca X-MS-Exchange-CrossTenant-AuthSource: GV1PR04MB9135.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2026 11:35:03.6805 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9NXNWUUR20hONyDOn8ezsYr17PUYLVtd3Y7oPjC7mtBUV9c2YCUnGeuoqKvZekq2TUGj6+ETRF3GNxnXyueZnA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR04MB10522 Since the BLK CTL registers, like the LVDS CSR, can be used to control the LVDS Display Bridge controllers, add 'ldb' child node to handle these use cases. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Laurentiu Palcu --- .../bindings/clock/nxp,imx95-blk-ctl.yaml | 26 ++++++++++++++++++= ++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml= b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml index 27403b4c52d62..85d64c4daf4c9 100644 --- a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml @@ -26,6 +26,12 @@ properties: reg: maxItems: 1 =20 + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + power-domains: maxItems: 1 =20 @@ -39,6 +45,11 @@ properties: ID in its "clocks" phandle cell. See include/dt-bindings/clock/nxp,imx95-clock.h =20 +patternProperties: + "^ldb@[0-9a-f]+$": + type: object + $ref: /schemas/display/bridge/fsl,ldb.yaml# + required: - compatible - reg @@ -46,6 +57,21 @@ required: - power-domains - clocks =20 +allOf: + - if: + not: + properties: + compatible: + contains: + const: nxp,imx94-lvds-csr + then: + patternProperties: + "^ldb@[0-9a-f]+$": false + else: + required: + - '#address-cells' + - '#size-cells' + additionalProperties: false =20 examples: --=20 2.51.0 From nobody Thu Apr 2 12:13:32 2026 Received: from DB3PR0202CU003.outbound.protection.outlook.com (mail-northeuropeazon11010027.outbound.protection.outlook.com [52.101.84.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 599EB36607C; Wed, 4 Mar 2026 11:35:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.84.27 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624113; cv=fail; b=BHJX6hsmBRjt+GJjtqKYXs1qJ2JD4crTDoO9hGjFVk1iZ7HlrJvuuB0xgUwUoM1GdSMAUv0mYuyteqkzejjAYmj4aPlbnkA3NM3A/CsOvyizflrrvf37y/mHEaN/AmvKgYUEjQ+kFR4y7+YZ/4xImL1o1D+sGlNIe4FhaslBWx8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624113; c=relaxed/simple; bh=WE/TcJkUffHrBm+4gVgKzQ4oHKOLam7o674S0I+Y4Uc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=nARW4pYmfXWKXqaScpMBmz0iWamq4H51VGBGByz6I9+PvcgUhCqxzkQEJlfIQ9E5fgJiBLJ0Wdqo8gvqEJ9rm/PrHCMz58t686HXSpn+dYgax3BDT0KZE64SPNOLRpzGQT0YwxoC5o4SVwjByqbJUZYcG6Mos4Xk2iyIRSelP34= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=unycttIo; arc=fail smtp.client-ip=52.101.84.27 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="unycttIo" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=xddmkU+/8a8gmrNkXd5h3i8gjkR0/v8gtTqDyIushd/IOUWxtf9IsjOjz432LRoFi+QqB1/Gz/3ecrbs3ZjrUybyUPs5xW17lRzN4skWwPyqXc8VnfjAIuACFwH7IZ4vgMIWpW4B6lKq0mF3pU2hAbCfiPNUP+YsmcOu0g+Rq4uh0ogu5B5rlJqvdOwigUiDIhyDK70wwBE+RdsTZW4N/XraoV1SgBCfGvGjBrBtlHh3DmqLyTnj2S2D2idnZoMBQsbVn9oVM4DqfbyyoG0W+ZW/nWLrTzDQraVV/Sxap3CamXDgKrEE5Mf+i3E+K8UowAQo2Ebv4G6NehvnZkMH1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=aHA5qcqXcY29B6gE1YPwSeWdQVOITwiLJNnmSiuQZjY=; b=bDwAT2u5un+C9EuGjtqxZzJ5tpe/kloS3/SGUhH0saxJIRqOlCIhTrFNESY6ti2yLcqL6JprgEKnBXJ6RxSovid6XzLSDvzoFLg+d+TBVyluF1yUbAuv1Pvpfr6irtKfXupLaqg6SBnCSl8EO1RR4Asiv12ikK4+zoVUsMAwf/I0F+vgIJDQWkzOQe0ak0cpHeSq1l+VhZzukgIn4IFctU1F2HklvQ/nKUPZZwYWTElXx1CQkbX8jLAg270cV8QdxgGK9TZjkZjaXGDJVlN8kaEQsVVWirHCIJvqERNHxKhPnueHMbjBx1kI9taypPtYaBBuYylPvepW6WfSAOKe2g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=aHA5qcqXcY29B6gE1YPwSeWdQVOITwiLJNnmSiuQZjY=; b=unycttIoYCB/2FBQc+d9saqPn+fu2Xo0D6Pd1YyXYV2ARVpUt1DzvVqB7Waox3XwWMM3Lr0icgDyap4dLpkP3A5yQ5ZOqdQlXQKrOltnKXfznTC4/PgOVI3yd8BXTkn9jEw/aw0clU9Cq9tSd705lTWS/z+FVjoyn0YpeUscNTeqbRkWq1tVvT+hW2AhV6l3/aW3WMTpZaMjLejKWmMLL64CtbhGg4SXrLD5+Z7SiN0LEbrPR3T1GRkq2g50xZYVcc4ttEvko3oZu4LU08rWjeRxhft/A4vqRcBJ2OI5iexWudWougTM1xEeuQ7q4yB0Q4mVQ7jBtLvRgeX1uM5LOA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) by GV1PR04MB10522.eurprd04.prod.outlook.com (2603:10a6:150:1ce::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9678.17; Wed, 4 Mar 2026 11:35:06 +0000 Received: from GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2]) by GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2%5]) with mapi id 15.20.9654.022; Wed, 4 Mar 2026 11:35:06 +0000 From: Laurentiu Palcu To: imx@lists.linux.dev, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: dri-devel@lists.freedesktop.org, Ying Liu , Laurentiu Palcu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 7/9] arm64: dts: imx943: Add display pipeline nodes Date: Wed, 4 Mar 2026 11:34:16 +0000 Message-ID: <20260304-dcif-upstreaming-v8-7-bec5c047edd4@oss.nxp.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> References: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AM8P251CA0017.EURP251.PROD.OUTLOOK.COM (2603:10a6:20b:21b::22) To GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV1PR04MB9135:EE_|GV1PR04MB10522:EE_ X-MS-Office365-Filtering-Correlation-Id: e0c3bf73-6709-4ddb-5959-08de79e21556 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|19092799006|376014|366016; X-Microsoft-Antispam-Message-Info: xCGf5tP5R6Qa9bqvXGdg/O6aF1reNcptEE5cbpOQ5A5vtmVhKl5evvWw9vrbBjk7Bnq17QklIFQuNwEDT927fzKE1IiA49yrmD7dU+2PbcphWEUVZdEjBHoUFRi5OvyrbaxUvKdEbXZ7DUvYP1pfSe/W/ZAju77F9IQp7VEXwNB2401ofH9oHp8C4M4AcviEg3PyO1ucBMvSuQRaz6Ly8Sev1naIP63BYYUeTezYlTC9DTrPULnbUiiJbFcBKeBC8LSjw/aaaXFk1P2qCGWZxsa2DghOtEu6n28xH41hJMncD3C/MVmzIt0/eXCgB1eRy7qQEHmkN4tgaue9OVfGHt9DK8LnMhTA5t6y3QTet9DzdHWNBEu4ig55MH26OJMwJis4xmuLeZLH/U6V1rRZFubuCYVwP8djHL4a0Xz3tPp93rSrnQY0uvsIgn7I8MwLFr++Pg9b3BaWID5DHbOpUoKELuMrZGt7WtWgBeKVtLVRGtnEIo1dADh1R1O66Pm1rc0MfvzymtNw0CdMuXQH2oguUG9A5ZR80itFukE9QhJgIUZrbITj3nN/x9oKn0PTQvtYqgFU7ebeXqFIqb+3rmy5OJEts5gQWDA1NvszbO7i9gz5uFy/2DhnqVdfFQ8N0vJTUmpJcWt0qF5DLAWAHgfLab9LgYUsQMDQiblEl4L2T56hTp2N0S71AunjRnSRmAF9xON9MmtY7qGnzhUEMcHGOSCAvnK1NNbouKQWjxA= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:GV1PR04MB9135.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(19092799006)(376014)(366016);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?WkVMT3U2d3N1MnJFWmNyQ3YxK3NhUFBwR2xKUU9YS1NaY1ZESDkvV3VDaCt6?= =?utf-8?B?eFFxTjhIWVhjai9NV0hOcm15VXFab1ErZlpmTHI4d1djZUdvY2JORTBjbk9Y?= =?utf-8?B?VGNnRlhjMktZZGRJWUJxMEVhM2JVYm0weXZRR2xxVVgvSFFtN0ROOXoxOCty?= =?utf-8?B?Q3pNc2tETklxS3lwWWJ0dDRTUzd3VTVXcWFKak1pVzArU0l3RFdabUhZUFN1?= =?utf-8?B?OVBGSGF4L3dvQ3JwbGJtYndLSkVUaFJDKzNJMUx3U1NuM1BpUGFMaU9OVnpR?= =?utf-8?B?YnQyMzE0cjl2WnBPb1RFOGQ0M2gwZUZKWGFzM1Nqa0cyT01xdnFzblNldlhZ?= =?utf-8?B?by9oM1QybEtrVFJZKzZvRVVNbjdWTnVUQTI4aWJkTTF1ODhLUDlLaTh6MnpS?= =?utf-8?B?MWdCZlJaem1xS0JkTDg4ZWR6bml5cnZ4MHJpTThuNWNlOHorYzdGYURsQzM4?= =?utf-8?B?SC9HRFIvaDhkbjhaczduWmVlRXlmNnFMcWFJeWxRdFNpcEhDUVBoSzFsRkpG?= =?utf-8?B?Y1padm44K2pRTDFIM082bVBFWnFBSWF6NlJ1Y0JNaG9RaWliRjRYVzRsMTZO?= =?utf-8?B?RWlxWVgvYzFjWis0NWtheTlBZ1U2UW9EdnNkM0JFSUZJdzRWeWN4OXNhQWh5?= =?utf-8?B?RGUyQUUweENiRTUwZHBLbzZjM2JOcC84YlZGWFJseTlZalJ2b1d5SllxQTNV?= =?utf-8?B?VjE3NEl4RzhMYlYxMStPUS90NzhnR2dUYnNnQnpmaUkwSUoyOG5WSUtVNU42?= =?utf-8?B?ZTd6QWdrdU02bWlXTFlGV2ZMMHhNODgrdFNxTHRIZUtMa2JKTE1DNkt0TU1j?= =?utf-8?B?dmtpUmlkZlNWTGRwYmdGYlhaRXRLdmZQSk9yRzZheERPcmJhMFdhcW1SV2Ns?= =?utf-8?B?Z1dOM0lWSGl2VEVkU0JGZzlUTkVWMENlZWNBNWNWdHZhaFpudWtuUWJZd3NF?= =?utf-8?B?UFQxOHV3RmdKZVlNT1A1enovNko2SG5TazljWGFvTnlXeSs4cktjTCtWRTlU?= =?utf-8?B?SDJkSXZIQjFrSDJxS1FOL3NPNGZENjQ2S1BPcFp6NEFTV3dFcytYaHp1bDN3?= =?utf-8?B?MGFjZUF2VzBBSkNNVUtVR3A5enkvYWNnYmNSSUFiMWdROW1qcThtam5HbkZp?= =?utf-8?B?WWlad0JIcXA4S3p1UE5wWFR5MnJrNStDQ0tIME1zaHBCY0xBSjc4cGszTHhI?= =?utf-8?B?UXVxSVJOb2g3NGZnMVFjRmdrVWFDbiswSElveHRPRUxaY2c5NHNJYjBuNG5v?= =?utf-8?B?Q0pmRmdxZVljU2t3L2FRWDhsbmlKT2R0UlUzTitlTks3cHd0Q0tPMDZvM1E1?= =?utf-8?B?aHJBR3ArbmFoTXdkTzR6aEZEWUNObUVCZTNyLy9vdXdNb1ZnLzlGeUNuZ3pr?= =?utf-8?B?TDlWMVFYN3lLMUtKQ1B6YnBqTDhtR25jZFhhS1dzVTJwamE2Z1JyNmtUTG0w?= =?utf-8?B?cXdUelB6NlpiL0s5VWRxcS9QYktlaVAwU0F0UjhsZllMeEVKaXBabzhLZENB?= =?utf-8?B?b1NMWDdzNEtlWW1sSkJnU3QvemczTjlnd0RnMnNhOGtlZ1J2cld0NmxRN3Av?= =?utf-8?B?Y1Mwc0I5dXRPc0EzS1BPOHl0NWFYZ1Q5VFQrTWNLaXY0TXdmaDlTbjN5NzRI?= =?utf-8?B?U05JNzFwS29rUm4yZm5kV0lHRGFWMUJkVWM0UUc4OUVydnBUTnU3NlRUQi8y?= =?utf-8?B?TmYrcnZhMDY0RFB3dTc3QjNUdXlGclgrYzRYWVlvWVhLZDBQNjFCeHhESjBm?= =?utf-8?B?R0g4TWRwbmNGNFZEcXorV3M1aW5MU1BCL3ZQTUo5RENnQ3ZzSVQ1L0VTbzFq?= =?utf-8?B?OE5SR3NITnlUdTFuNXRxZ1FIQXk5RElDSlV4L3g3THhwTU4ydnNPemZhandJ?= =?utf-8?B?QXJRMXhrQXMyd0hvZW5lRUZRWjR5enNvMFdrQXllQjBydGJXbENMY0w0Um10?= =?utf-8?B?ZDZlcElnQXVUWVdLTHRJVDZjMithNzQ4WHFwZW83elZVUnIvcGpBcXY4czFI?= =?utf-8?B?VDRDcVlWcHVsaTFUcTFwZWhzSEFKL09mMTZ4UEZvQW5NOFZ1T296OUUxZkVK?= =?utf-8?B?VVJYWDdoWWtrRjc5MlBuQW12Z3pPQWVRVUhzMFdpZFZtWkRESmNNc2ozVDl5?= =?utf-8?B?aWQ1VjZjUWtlek9Ed2VYVm14ekV3SDhnUzNzanlVemM0TE04QWlkUkJGYWdo?= =?utf-8?B?WUJ1WWNkb3B0SXBqMjZPTTIwOFUyMEU2V1daOWhUVkRsZ2dnUjlVVkVuYWVX?= =?utf-8?B?MkJrR3hZYmJZMjRjM1BvVWlxVUxMRFI2aFhKUytRd2lWWUFKdkRoeWlaenRh?= =?utf-8?B?STFYTVhadGtBWGNvbXA5RlZuQ2FueFhlWjUzekdGckJ3cThkKzdzQjVuUFQw?= =?utf-8?Q?OPlY9Kv95CwIHzOY=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: e0c3bf73-6709-4ddb-5959-08de79e21556 X-MS-Exchange-CrossTenant-AuthSource: GV1PR04MB9135.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2026 11:35:06.2922 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +EZ0g5irlcO4bH0erxdQKoM6BwZ4lXrBL6/cVubjfJNyKZ8MTWYbG/aPeuVC4Vw7DXuPmiV2qtJuEUVY4fFvgA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR04MB10522 Add display controller and LDB support in imx943. Signed-off-by: Laurentiu Palcu --- arch/arm64/boot/dts/freescale/imx943.dtsi | 53 +++++++++++++++++++++++++++= +++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dt= s/freescale/imx943.dtsi index 657c81b6016f2..9a91beef54e86 100644 --- a/arch/arm64/boot/dts/freescale/imx943.dtsi +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi @@ -148,7 +148,7 @@ l3_cache: l3-cache { }; }; =20 - clock-ldb-pll-div7 { + clock_ldb_pll_div7: clock-ldb-pll-div7 { compatible =3D "fixed-factor-clock"; #clock-cells =3D <0>; clocks =3D <&scmi_clk IMX94_CLK_LDBPLL>; @@ -174,9 +174,60 @@ dispmix_csr: syscon@4b010000 { lvds_csr: syscon@4b0c0000 { compatible =3D "nxp,imx94-lvds-csr", "syscon"; reg =3D <0x0 0x4b0c0000 0x0 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; clocks =3D <&scmi_clk IMX94_CLK_DISPAPB>; #clock-cells =3D <1>; power-domains =3D <&scmi_devpd IMX94_PD_DISPLAY>; + + ldb: ldb@4 { + compatible =3D "fsl,imx94-ldb"; + reg =3D <0x4 0x4>, <0x8 0x4>; + reg-names =3D "ldb", "lvds"; + clocks =3D <&lvds_csr IMX94_CLK_DISPMIX_LVDS_CLK_GATE>; + clock-names =3D "ldb"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + lvds_in: endpoint { + remote-endpoint =3D <&dcif_out>; + }; + }; + + port@1 { + reg =3D <1>; + }; + }; + }; + }; + + dcif: display-controller@4b120000 { + compatible =3D "nxp,imx94-dcif"; + reg =3D <0x0 0x4b120000 0x0 0x300000>; + interrupts =3D , + , + ; + interrupt-names =3D "common", "bg_layer", "fg_layer"; + clocks =3D <&scmi_clk IMX94_CLK_DISPAPB>, + <&scmi_clk IMX94_CLK_DISPAXI>, + <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>; + clock-names =3D "apb", "axi", "pix"; + assigned-clocks =3D <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>; + assigned-clock-parents =3D <&clock_ldb_pll_div7>; + power-domains =3D <&scmi_devpd IMX94_PD_DISPLAY>; + status =3D "disabled"; + + port { + dcif_out: endpoint { + remote-endpoint =3D <&lvds_in>; + }; + }; }; }; }; --=20 2.51.0 From nobody Thu Apr 2 12:13:32 2026 Received: from DB3PR0202CU003.outbound.protection.outlook.com (mail-northeuropeazon11010027.outbound.protection.outlook.com [52.101.84.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E7EB372B5F; Wed, 4 Mar 2026 11:35:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.84.27 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624115; cv=fail; b=r3+NAN1OTE/cjar11UEKGGVQiF9ucctE1+yhidlMfbyzrwwf1tntyaBdm29rt+V6wfICG3W3tqH2zdSbzyHPhTlOnCype8TY7jwQ4vToZGhmAX/F53+mr49NkZbZFt4ny5vqNoaWumAv5SgOuoH26JFst+fVEo6RZ7L+1LV2/Ow= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624115; c=relaxed/simple; bh=JCscwsYC2UZYi2J/CD2JLSrv7eRuVeX7ssfCTmsbLqQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=B1QuWjIe9c5w4nTHcyTdLK7An4Bjh41jABQ7QiijDdnNlkX7Oid0lEIrK8Kh12iuxR0T5flgg5pzUcSPQLqZsaL8Hlt6nvN/y4eiMGnXqjPX+YrywkVKI/WZheCuax3UezzQGxE9Du5T31ICnb20Z3Ea6AuLrPqq10jyc1Tlrao= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=Ae1Om627; arc=fail smtp.client-ip=52.101.84.27 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="Ae1Om627" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DvCGg1cwNTuTw8XvWZpc/PSEUrsI1vKrPw19leTLCQq31PNezkKzyCRih1H7W+cLSXDapa/75lhYOqfZcwz99yxALWCqTBGhTofLurkOUggj0rHNunoxtZ5A2sJ4rDTqT48BaVqxFCQAeAQBVBbvZqnX+KdOaXKjSmwznpGT/rYO/0nXxnbxRC67j7rZSCUzE5mf+L1q5Gi+V8HevzrBjixya4+FKeeNds9k+mW1UMQ/oHtdnbgP/Da35FxBoUYMylmhjRDLWlXqxNclCAT0e5/euj8/GH9qUmtVbtcr24YDNOeTBUJRqnHdr0fDiyE6oYAz6feLTVEYo4lf3V1O9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rxmC7REIwkDLDNsvhDHypg0S1aF/Jcbc7I0TMIizkpg=; b=WaOmJhJ6YyGkPRfqATdentihOaOPWphvenqVYfQUQVJjDv4zFGSxfMPxeUme/gUmwesFqpgwR97UUSBRaDG6NG5SgxeeZeSDMRZgKpdHpKWUeh+5xYOoAzBtxGfO6WAlVpj249aCNQxX32x9d14HcAt/0Eo/QDdHJpc7vr3HPLv9dqHkQzt7x24eEXR6KhOqdVrYjIDdya5rgO6iOmtbcOJm5hsBhfmIHNUD9An9lvBDzMvaa8GPd/cXTNBiBOzV3wyH0v39/5G+9p6kkO3LQVoCpzfG0P72Zn135Orn5C8PR1Eef6CvHVi95rUcMwW4kyTtlKZVN2XCgxJ4BqXDMA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rxmC7REIwkDLDNsvhDHypg0S1aF/Jcbc7I0TMIizkpg=; b=Ae1Om627PSc3fVKIcpA8O5h6op/Fc5SK7jbnIRD6olV38A8ggBE3ouY3WlpFYwz6Aklkm06nCxPTi02FYZpgnamQeVvk9SccbpSXLx6yQpw3FRbLea+z/KokSrK9ZaGNsYFo/tsYd4xAiPqOQhmhvQT9NI4FKo/LEiZZ38cobKVwutXaWAKlcuJb7avS2Kkrnthxm5UYukvZBOkMmkRlxrrX1aO6SOvwx+j2Hg2nen7P8VUMwnCDiMOO5SGB7QrDCFhEbso9zHq0kj87g8n/dduFuVwRIlcZGwml265K9pLo0hsD4XxbZJK6lPkvjmcXa1IPfDbdDabmjYX3zREXkQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) by GV1PR04MB10522.eurprd04.prod.outlook.com (2603:10a6:150:1ce::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9678.17; Wed, 4 Mar 2026 11:35:08 +0000 Received: from GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2]) by GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2%5]) with mapi id 15.20.9654.022; Wed, 4 Mar 2026 11:35:08 +0000 From: Laurentiu Palcu To: imx@lists.linux.dev, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: dri-devel@lists.freedesktop.org, Ying Liu , Laurentiu Palcu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 8/9] arm64: dts: imx943-evk: Add display support using IT6263 Date: Wed, 4 Mar 2026 11:34:17 +0000 Message-ID: <20260304-dcif-upstreaming-v8-8-bec5c047edd4@oss.nxp.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> References: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AS4PR10CA0021.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:5d8::9) To GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV1PR04MB9135:EE_|GV1PR04MB10522:EE_ X-MS-Office365-Filtering-Correlation-Id: 40fe36ea-142c-4923-f655-08de79e216ee X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|19092799006|376014|366016; X-Microsoft-Antispam-Message-Info: zaRe6JIhxfyoe88+ozGFIwPEceYQvZ7BzKu0UFsCnL8YJjJPtDMQZuwQDAeuWpQFdfyfsECBTrjK5ApA/FHHPqfdXfxFK3HlfDy2Qn3oQ3/zZLleaWvQq+PXDGxDYyMw6Fa9Ew1GKJzfoktapqry+aMuprnhTrBFtYZjm2YEAS88Kd/SWexmLuLTnfbbXSQOuVu9vHYUlsMo6dAJ7dcePD7KgXELbptc0iKOgwSboBTv3B/QHwgYsNfDIjKMaajS1KdOdNwNVmhi7skUkviNXQqM0yCokVW+JYRLomyDU7zpmVrqAUHcQ47yBq42B3F7CK8z+a8zkP6wgln/7l2VK3rw2g23ntGlgas4N42JMwNULCAkbVAVHCfD8Aytj9zvgyhw3lSiBfPfQ8UejYezPMcT7xmvqH+ZRJfy9hFJOW9pvzX5fIAEBitN+lmmGdNSSIuHIw87JJS5bG3u/c7mv81Pxzapb5n/WLeeqnnUZWg3ykMClT5vrowDIl+3hvnA1ZmscjHdrQqwid61tG5dDzigRItb7YVIr84hJpaYD67OnuovjT6X3DPS1JnmEcTLbAggxoCTstsEkgfxXnSO5v9MbhEqdhq3C5fpFij/C67q2arZhrAI81foFVmV3ihtWgK6Aeork86p9YnJ3eWboFQ4src5SLICeP8pmd8sROgRhml8yzYt3LvEUFzFZovXb+x99MZBiIqPEyQizqqjAECCs610op1pIFtv3dwoNb4= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:GV1PR04MB9135.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(19092799006)(376014)(366016);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?azVrUUZuSEJ6MlgranBPbHprSGtVYUNOVXZKQkdZZDlQT0Rqd1UzOFlTQW54?= =?utf-8?B?Z1BjWXdhSEVoMGd2aU5XS3dSWGJsVS9SbUc2UXJXeVJFNFY1dkxrdEpxcHhL?= =?utf-8?B?U2kvNi9sS1hZNW1yU1RRMitvaDdlUUhDVmgrQi9pbWcxellFVmhjRzdCaTBa?= =?utf-8?B?SDBsNDJheHFNTUswUGVlN2RRcmVJOHRVYTJoQ0NkTVl5L3BSYkNQOGF0Z0FZ?= =?utf-8?B?REF1RTJ6OGRaYjVIbnBIUFF6UFF6dk1NWFBDRzlOVFJEVkdIbmpZOTFQaE5Y?= =?utf-8?B?QlN4OUQzRW4zcTR4OEYrUnNNTVJZU1poQjdpanY2VmlXQmYwV2NObzFxcnlT?= =?utf-8?B?cklZV294Szd5WWoxeU14SlJ3Z1dpbUdhM1M1VHBkSjM2eVBRbCtyMi8zV29v?= =?utf-8?B?R2FpMUY5Y0pRTWs2aS9ONlAxM0txWXBRVTB0SkRQRG92UTJpb1VzLzVSZmNx?= =?utf-8?B?ejE4T1l0bWVtdThUNGhoenR3S1IwRjczNG1sdk5wUkp2TU1XeDBDODFPVkRE?= =?utf-8?B?bG5qamhUdmdTZGhvVFl3aSswM1dPQ0tQcjlCTUVmNFBTenVwS2d3RTY3anhZ?= =?utf-8?B?cVhoQlFpNHdNb2tDVjNpUmEwN21lYWo5RUZFQmQ3aXNZcDBHREp2Tml5TjBa?= =?utf-8?B?bzQxTUlWcStpdkN1cFVlZUNYTHJJbjdYTE1ZdU83SFVGRk8xbVgxeEJnRytT?= =?utf-8?B?L0crM0hINDYyL04zTFJvZ3RzbW9ZazBlRDNsS2xvQUNxa0ZtdXJLc216bGl4?= =?utf-8?B?andDQkhaUUdxL0JmbGtFWExPeVZramY4WFdFaCtWK2oxbmx4Zm9Ubk1lQSsy?= =?utf-8?B?UUlSTFFpWUFYOHZUWUw5QkpJUjFiUlFaelRiQmMrR25DRXE3cDdlUVRBSGNQ?= =?utf-8?B?MEFVTzNiNEJTNjl0Y0JZT2d6ZTlGSWJnOHdiSWZ4S1UrM3ZROUF0d3FNQlJM?= =?utf-8?B?OFJaR3h3T21BZkFKQWFKK2lsdmd2d3grbEV5WUZFR1RhVnRKanVBdnBRN0k3?= =?utf-8?B?d1NBS0FxV2ZTV3VESmViQmRxRHloVlhXTlN1Q3M0SkhMR3ZxL0QvWFZlWkI2?= =?utf-8?B?bnNUWER6UytxTi9zMVBFR29SOGxiTFZWSkNqeUpkWm9EOWNwaFZnNjJvVFJZ?= =?utf-8?B?bDVRTlg5a2pLR2NOSXNabjdON2lpcDlxLzBrRUQ0Qm1ZcnBlQTJKNlpsa3JW?= =?utf-8?B?TFR0SGQ2Z3B4end1K01FcVgva24yVENabmxmczB4VUtQZVp5N3BlUDdsUy9K?= =?utf-8?B?dEtiUXlIOERYUE5YSnZrN0ZmcWM0dVB1QWNVNStQUTBlcFBxaTdDRk1Xdkg3?= =?utf-8?B?eXQybUFObG9CTEQydGFacjRKZzNQNEFBMm50YVNzZlBmcHdEazlpRDdMdG1V?= =?utf-8?B?Zmt2MEhTeGNWK25aV0hCbmhHcGJTd283Q05xVGkvSkNWQkRRQTM4cnlFdnRF?= =?utf-8?B?cVdWaXhTa2lxUHlNT2FPdmt4SUVuTUl5T3k1ZFcxcWY4YjNKcGpFc0YwejJP?= =?utf-8?B?ZjQ1VWwrQk44Z2NXNnVUUndXQXZTVGlBVDFMbXJnTWgvYU9sUzdwM2Z5b0ZP?= =?utf-8?B?ZDAyaExCQkxkOHlRQk45T1Z4L28vUU9hc1NUM1R5djdkdzhxa0xPa1dMM3BB?= =?utf-8?B?WFRuZXRJQTJTbHBXMUFISC94VUhpczllcUwvOEpjMWpZdlBCVyttWVhXcVJx?= =?utf-8?B?VUFTZ3YyeWIrRDA2dkhvK0gzV1VCS0ZNNVFMVXgrOGUzdWxiU0ZvZkU3NzZT?= =?utf-8?B?eXZHRktncThIN2QreXE4Qk9VRGQ3N3pHcWdmSlNZNVRic213U2pkR1gxWWZE?= =?utf-8?B?cmZpSVByRmZwR1ZPT0hGU1F6Q0ZJME5aZkFFSjE1bVJCN3NoM2NUblhpK0JR?= =?utf-8?B?MEp4U3loZzVNTGZSQTFjdndWZk5QUGFyQm82QkM5Rmx4dEtvOUtaWGpxeGNL?= =?utf-8?B?TkhSdldXSGZjQ3VEUlJoUG9wTGpRQmwzZUVINWF2ZmprdVpiRDVuajJOMzRK?= =?utf-8?B?Qm1MUWVQc1N5T3liRC9KN0x1anhQVEIrSEpEcERkZi8rTDVZZU1xTmRaQzRU?= =?utf-8?B?YUQ3RnFMSHJHRENTMU5aSXJhNkRNU1FqSmlNUW9zbHZ6MzRtdldINERlL2or?= =?utf-8?B?OGVhUlRSaW9SZm9XS1dtZjhqUVd6ZjEvOHUrdnpvM0NndW9ESjVMM09DUFNX?= =?utf-8?B?azE0d2JoMmdwVytFZlZ5emdPdmNVZi9jYmRyOWV0b1dMRG4wVGpweHhjdm1x?= =?utf-8?B?RXVmdUNKVzEwME9hYk1QenArYXJaZFlscGx4RSs0MDFKOWhFMEM4RnNMK3lE?= =?utf-8?B?dFBBNUhLQ0RwUURRYTV4OXhXcFA5b3E3VWVGL2tadlcvY0xEMWVtWUhkTmRP?= =?utf-8?Q?feUBii6WRp6WKnTE=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 40fe36ea-142c-4923-f655-08de79e216ee X-MS-Exchange-CrossTenant-AuthSource: GV1PR04MB9135.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2026 11:35:08.8688 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nBu+3dbktYNQE6DXkMbGj0HWA5AK5olQUjyIVn2WUKH/qJVrJ69HAQTs4OTPOZtl5cAbBMOJ9wz6weR9GT00vw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR04MB10522 The ITE IT6263 based NXP LVDS to HDMI converter can be attached to the i.MX943 EVK board LVDS port using the mini-SAS connector. Since this is the default configuration for the EVK, add support for it here. Signed-off-by: Laurentiu Palcu --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 86 ++++++++++++++++++++++++= ++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot= /dts/freescale/imx943-evk.dts index c8ceabe3d9239..0b69450566159 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -55,6 +55,36 @@ dmic: dmic { #sound-dai-cells =3D <0>; }; =20 + hdmi-connector { + compatible =3D "hdmi-connector"; + label =3D "hdmi"; + type =3D "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint =3D <&it6263_out>; + }; + }; + }; + + reg_1v8_ext: regulator-1v8-ext { + compatible =3D "regulator-fixed"; + regulator-name =3D "1V8_EXT"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3v3_ext: regulator-3v3-ext { + compatible =3D "regulator-fixed"; + regulator-name =3D "3V3_EXT"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + reg_m2_pwr: regulator-m2-pwr { compatible =3D "regulator-fixed"; regulator-name =3D "M.2-power"; @@ -179,6 +209,10 @@ memory@80000000 { }; }; =20 +&dcif { + status =3D "okay"; +}; + &enetc1 { clocks =3D <&scmi_clk IMX94_CLK_MAC4>; clock-names =3D "ref"; @@ -217,6 +251,21 @@ &flexcan4 { status =3D "okay"; }; =20 +&ldb { + assigned-clocks =3D <&scmi_clk IMX94_CLK_LDBPLL_VCO>, + <&scmi_clk IMX94_CLK_LDBPLL>; + assigned-clock-rates =3D <4158000000>, <1039500000>; + status =3D "okay"; + + ports { + port@1 { + lvds_out: endpoint { + remote-endpoint =3D <&it6263_in>; + }; + }; + }; +}; + &lpi2c3 { clock-frequency =3D <400000>; pinctrl-0 =3D <&pinctrl_lpi2c3>; @@ -258,6 +307,43 @@ i2c@3 { reg =3D <3>; #address-cells =3D <1>; #size-cells =3D <0>; + + lvds-to-hdmi-bridge@4c { + compatible =3D "ite,it6263"; + reg =3D <0x4c>; + data-mapping =3D "jeida-24"; + reset-gpios =3D <&pcal6416_i2c3_u171 8 GPIO_ACTIVE_HIGH>; + ivdd-supply =3D <®_1v8_ext>; + ovdd-supply =3D <®_3v3_ext>; + txavcc18-supply =3D <®_1v8_ext>; + txavcc33-supply =3D <®_3v3_ext>; + pvcc1-supply =3D <®_1v8_ext>; + pvcc2-supply =3D <®_1v8_ext>; + avcc-supply =3D <®_3v3_ext>; + anvdd-supply =3D <®_1v8_ext>; + apvdd-supply =3D <®_1v8_ext>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + it6263_in: endpoint { + remote-endpoint =3D <&lvds_out>; + }; + }; + + port@2 { + reg =3D <2>; + + it6263_out: endpoint { + remote-endpoint =3D <&hdmi_connector_in>; + }; + }; + }; + }; }; =20 i2c@4 { --=20 2.51.0 From nobody Thu Apr 2 12:13:32 2026 Received: from DB3PR0202CU003.outbound.protection.outlook.com (mail-northeuropeazon11010027.outbound.protection.outlook.com [52.101.84.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25E4C34C816 for ; Wed, 4 Mar 2026 11:35:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.84.27 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624117; cv=fail; b=cuVcQwqazbgzhy318Q9dB9q2J6XTnHGyoPM6VKFWuXW7y2sC+Q4F9XKLOJXkT+pI0iQ+9vG+Fu3bAHQYsaDXbCD3tG6IS5aLclMQNaCJK6e20nEW/iBwWG89uq7HyNSyRWOLXkrn0kznYCJmfuk0RUnX2c9K+pWJh9wxjcad4AY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772624117; c=relaxed/simple; bh=PaQGUOci15BA710vz09ShrghvFE80wn/qfffFtaKkzI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=UBb5zbyw8c0a7xVIJTDCaI8jNhslKMfD6hVhllZzcgQ1SY1exox9xg2IyNns12bLVjxI4xuFUaK1ptzQn9AK9GxlCe38PaJlQhFe+wd/F0qFxqk+ohN1k1kV0/oemMplDfkFKSHlP4N8/BEZNvLlPOUS1DxGyD1HCACSDVAydP4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com; spf=pass smtp.mailfrom=oss.nxp.com; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b=fRiHstob; arc=fail smtp.client-ip=52.101.84.27 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com header.b="fRiHstob" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=tau1vEG3+a/A8Yq71O5YbQmGwp/wNjoE+t2whLXfNVCPQesMZZkzequQFrrioBY44gHbrdCwa44RyXn8SCKdkqDx1yzLrRMYWGIWsNGaPXTekRMnF5e4WPTkDdx9F8iVaJV45cG58v0kx2Bm24WyvsGpuL/n6EO4/pIrtBOVtQJoj/PNW1tOfk4G2kfnVNJV0wJxBMyAOngYhe69GW7qnH8LUYDTf/nWn9g0XZFrh2qX3/3FJ1rumPzET4AseDy9PsA9hNT7TGtAHoO+WgnhH4/jUNSVFngUdBOmjk2ZtQLtk3/gta16h6N+s4ybsPnoi3mj+ezxykficnpumA5Czg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IhGDEx9o9rS2Au9SfGJRzMNdjhwZX8RTiMlAGU49gZM=; b=rT3T8CnVNFrjf/XkO3mkg1gj6+sBzzX0U4qJN5My1d8G3wo14pvuSwxtVshOEBNF0caIrBxDjykkTnxvfb0eSoudEcDNgRCGkB07z8evJrfUTBBudLLJABwVYMKLyeVr3NQDxi1qSE799sWGEQrckSOjFGcuB6sUDtf68tqLs1xQpt9rSfv/KZnKAESgfEc77DHVlghsw3Lt3jsF/4OYxYjpHXnN3QwACj/6gRUL62G8VrZBUvqhU5A4UhoHiUqxAXmanOeJ9VtAMCjMlondwff4UEVc7JQ9Q9vJsbxZM6lt31tyiwKDzLdi5qdYtqh1juh43mFrOS4oTyureRbykQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector1-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IhGDEx9o9rS2Au9SfGJRzMNdjhwZX8RTiMlAGU49gZM=; b=fRiHstobs340ZSMIaDiu7iaa0sE92wHoSvZyoqkaUfFxlzT5We8CFyR2nK/cPYKcZE2/lBDjiabVsuTSY39vV5V6d71tKwsIlC+6k99YxNLFwnDMK/p3GhCpB2FIB1uUy9v6d+YIgRcY61qhEAlLAbAW3ZQhpxSZrVy6dH8PDd8w1oZSz4/cOGQwUw5RFI288o2FBeu3vDOhu6sP0L3bgRsbSJOD47OrfIPtpilVunciLER5KAw8kkuJaeX/0e2MdGQsoQEizCrBTIwxnX4hsWdi9K7sCZ2rU4h1oHtyCxU/l126bmgb3tWbhVqjedaW4Z8pixLGBo1bnhIf2BE7kA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) by GV1PR04MB10522.eurprd04.prod.outlook.com (2603:10a6:150:1ce::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9678.17; Wed, 4 Mar 2026 11:35:11 +0000 Received: from GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2]) by GV1PR04MB9135.eurprd04.prod.outlook.com ([fe80::3826:2706:1e81:c9e2%5]) with mapi id 15.20.9654.022; Wed, 4 Mar 2026 11:35:11 +0000 From: Laurentiu Palcu To: imx@lists.linux.dev Cc: dri-devel@lists.freedesktop.org, Frank Li , Ying Liu , Laurentiu Palcu , linux-kernel@vger.kernel.org Subject: [PATCH v8 9/9] MAINTAINERS: Add entry for i.MX94 DCIF driver Date: Wed, 4 Mar 2026 11:34:18 +0000 Message-ID: <20260304-dcif-upstreaming-v8-9-bec5c047edd4@oss.nxp.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> References: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AS4PR10CA0020.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:5d8::10) To GV1PR04MB9135.eurprd04.prod.outlook.com (2603:10a6:150:26::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV1PR04MB9135:EE_|GV1PR04MB10522:EE_ X-MS-Office365-Filtering-Correlation-Id: 95c0d9cb-67ea-435e-94f2-08de79e21870 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|19092799006|376014|366016|7053199007; X-Microsoft-Antispam-Message-Info: dqQlm6bvaXN9DqSyA04MNJGMsqMKL3ijkMlWhSGaiG4uo0w5o0xaxDYQzXC3xTsvH1b/yFgaZPEOFAfe3u3sqboByatLlzYvzJH8XVsgSpsPQxCKgaub0EwOS3f6FrX1lZL3c+KacKfVincg3dZPE2nXd3p08uIukbnx1/U5y431kiRYfm0NQnBBhkLu3aMzM5fKhtd+ePlASj9lObBHqPrQ5aMdtSAmWvVqpOGPjloHvXDQEefs+JE9XK42usVaDnTOHXeZTpmRoX7x2y7WGS9pzRsaFy0g38CorHjM6kX+lKG++MqOCADL0oRCc29UlzgKf6I17Td7Wou9X137omnU31M41wfOGmDrH2pCoW3QE9lSHMj7SSooWZ+L392l36r9cwc/FWIRgRUI024blSEl1Q9KoBFj3/N/x51x5YfQxLWtMZ0l22wKVfrPLLcPBwTuKJkZDoUSWja+p6lVtXCzXvcn5+ewBtK/5FzzEpfznpXTQzHo0LrVq/OdEZocfpsyaQ4G+1Cw/5LCLoov6F3lHM35SPxx3gqcUQ1Oew1RnlQ18WrSRit8xfkflb9MxyQ6Aftyc+E5WCq4nQrKUn2ERu5vJsveNGxd2AIeqveTjy13etZ8z2bggSCw4vn/3HCwNl1lyyHGY2kfCLCM3di81WLKO+mD7ZO2DsOHLCSQl0HebRzkDpOOnyLjoMco X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:GV1PR04MB9135.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(19092799006)(376014)(366016)(7053199007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?QkFGWHBDbUw3aXV4QjFvNzR3RHlxb0ZZVkFqQ01FMVZwSjlUVERPQlR2UUE0?= =?utf-8?B?NFlONDd4RmJ6NUNUR1hhQlVlbjdkSExRVEFsanNWR0UrV01MVTRYRTZZeGY5?= =?utf-8?B?cXp6WCtFbWVRVFVuWjhjMlBvSzVST2hwdzJJY2sxRitOMHZ2OEl2ckpHWXpu?= =?utf-8?B?ZTZDMC94QTlKdUdxMEV2dC9LMXZ6NCsxcVpKMkNKdHpLTDV2R0tnQ1lQOTQy?= =?utf-8?B?QlhnT240S240TDdjSUhHbDBWcm1pTkFvS0ZiNzBsT2dPaEtJTEEzUGxmSUY5?= =?utf-8?B?dGZ3Z2tPNmFGcnhGenlzNVo0eEU5YTVjSnFXRStJUkIxbHhKdlVySmlkYVVE?= =?utf-8?B?NWIwQ0pUOWFsZDU4clFid21wRUhuM3VTWUFDYzlRRGpwSnZVUVNqNklOcmNE?= =?utf-8?B?RFZUYkoxVGxURHBFNjFKVVV4N1JjTy9LM1B0ZTJKU3FMODJpWkt4enljbCtU?= =?utf-8?B?UlFGSW1qMnU1MTlhSzRTY2kxU2J6OEpPYU8vYmJCZWVOUW1tTWZKS1hjZmZx?= =?utf-8?B?bFZxTHo3c2NzdVJnLzRaMFNQR1hOL2sxZXg0aEwxaDQweE1qdTlyUEFyMkUr?= =?utf-8?B?bjk5KytESUYyZ0ljWGRMbXpWVGo4WHpxSzlCaHdkMUFuQVBMSzIwUEdQWS9F?= =?utf-8?B?b25UYWRLKzRMaW1yOEIyaUlZZEkvNDFPWm81QkJJL085ZW1IM05nZ2NsbllL?= =?utf-8?B?Y29TWnU4RkJNTG1aVkFDN0U4TzJKdXQxRi9sa2J1OXI4QllqT2FsWklKQWR5?= =?utf-8?B?Qm43R2Q0RTVjQkl1RmFKSEcramVmOHZsc3lGRjB1bzlXUGltOTZlWFFFWTZE?= =?utf-8?B?VC9RdWUwY3BrS2J0STBwR0xxeHYzUzZuUkpubkVtdUdvZ3RwUmlyQ2lMMVVi?= =?utf-8?B?VkFKTDllbzU3VE5RY1c0N2ZqS0F2cmVtQStLTWZvaWo0M3orL1dYTnAvS1gz?= =?utf-8?B?TksweDMvOFZSSWgvM28wZk5HNDlNUHMyTUNhZDR3N0N5Yit5ZkEwWmZIZnds?= =?utf-8?B?bDQ4SmFldUZYTVh4TGdIYWlHWVdDYW9PZ2pLLzBBTFlqZytMaWYzbzBKUFU0?= =?utf-8?B?aFpWalZuVU9VVXVXbUxSai9CVEFPRzFSTGJlS3FRNTJNUGg5Z2ZBOTE3N0h3?= =?utf-8?B?d0tvMnNlU2FpM013MWQrUXdZTkFWYVJOdDR6M2Z0U2Ivdjd1YXhiNFZWbnVp?= =?utf-8?B?TUtyYnFyS3lZcmFXUi91KzFvMzlKUFRKWVIwai9zV3dSdys2bVJEakhMUllQ?= =?utf-8?B?TTU0UGlLRGg5QU5mT1ZxZ3NrZTdBRGJ0OGxNelpRdkVkdUt0dUJWMWMxSU5Y?= =?utf-8?B?RGhhOEVwRnNxYWxvN0JVemN0MERXZXIxTnhxVEtvVktpWmxVRzdtSCt2NWlS?= =?utf-8?B?N05LTWFGRU9QUG9rUWRsQ2ZEcGtzYWtaRklublloZUt5b0I2ejgvOEc0Q2d3?= =?utf-8?B?M0FyVEo0eWt2OXlkSGlRSWg2ZnFGb2tCWVJFNG90Y2pHT2JjenozQldRSUU5?= =?utf-8?B?VXU0WFZycHJlM0tBU1o0M2pHZzE0MzdwMFF1WDJIaFh5U01nWXQ4aGRQL2hq?= =?utf-8?B?SEZGL28ramR5STE0Mi94N2cvclBjRmlwY1FlUi9IK1lVdkE4aDlEaWQzdWo0?= =?utf-8?B?NDF3dDFuSmVERWtFZkh0L2d0dHBEcWluNnNLSTl3UDNkb0RnV2Q2WVlIallG?= =?utf-8?B?QTNvUzhpbDN3Ymtvako5SWp3c3l6cldvUmZhZ1ptUVlBcEQ3YTUwOGRrWG1q?= =?utf-8?B?NmtsWGdweERPUWVodVdtSWZSWWhrZXZSb0I3Mnlsdnc1eDkyQytPMlcwZWVq?= =?utf-8?B?cGt4aXlNWVBrYlVTUHR5eU5ERUp6NUxGNHFrLzh4dlFEa1hNZWdoYVhTOUZS?= =?utf-8?B?YXBBUUt6dDAzR0RJVDVoTklEbXNOWU5VcWpHYzJINjIzeHFUSDY5cjh5VHFx?= =?utf-8?B?UXhNUGZCblZBcDU5NitHcDZEeWN2VjluNDhOQUZYT1dtU2M0ajgvc1pIK2ZH?= =?utf-8?B?eWY4ZFdiQ2c3TjA5TkRQd0kxNG1md2dHaS8vcWh6R2dtTm5TWFNCdDF6WDVY?= =?utf-8?B?bHZmRGNaY3BMbDg1SFk2THNOMUNEUStKUkxoVjN3UUJyMm4rMVUwS1o5K1lw?= =?utf-8?B?bHJWYnJOZUd0T3dXRHVMdWc3dm5sMjBJUEZlQWZjcmlMRzdQdWNPWkxveHdZ?= =?utf-8?B?ZlBnUlgzTlAvSjlVOFdMMkxna0xOZHUxa0NydVlON1pjRnd5SXA1WXFmMzNI?= =?utf-8?B?UGREOEtZU1lMRDNHSnlieDlGTHJXZVoyL0tRTFdQVEtlSGY0RFI5V1JoWExY?= =?utf-8?B?a3Zja0NFeWU2OGQxalFhS29aakp1cDlTb3diaWp6N2dlY3MxQTM3bXdDRno5?= =?utf-8?Q?Cbjwc8aBRWkLwilg=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 95c0d9cb-67ea-435e-94f2-08de79e21870 X-MS-Exchange-CrossTenant-AuthSource: GV1PR04MB9135.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2026 11:35:11.3943 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ApS9QisiDce3HllU6SJNS055wfAVZeEy3ZK52Ko3hYMQS1CqPqFBz0WI9GmBA8E4iooSBwhJJiq9RvizrO4hog== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR04MB10522 The driver is part of DRM subsystem and is located in drivers/gpu/drm/imx/dcif. Signed-off-by: Laurentiu Palcu Reviewed-by: Frank Li --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 364f0bec87489..306e04d6885ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19117,6 +19117,15 @@ S: Maintained F: Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml F: drivers/media/platform/nxp/imx-jpeg =20 +NXP i.MX 94 DCIF DRIVER +M: Laurentiu Palcu +L: dri-devel@lists.freedesktop.org +L: imx@lists.linux.dev +S: Maintained +T: git https://gitlab.freedesktop.org/drm/misc/kernel.git +F: Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml +F: drivers/gpu/drm/imx/dcif/ + NXP i.MX CLOCK DRIVERS M: Abel Vesa R: Peng Fan --=20 2.51.0