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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Nikunj Kela Signed-off-by: Deepti Jaggi Reviewed-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index d48c625d3fc4..f9a04769e20b 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -891,6 +891,11 @@ properties: - qcom,sa8155p-adp - const: qcom,sa8155p =20 + - items: + - enum: + - qcom,sa8255p-ride + - const: qcom,sa8255p + - items: - enum: - qcom,sa8295p-adp --=20 2.43.0 From nobody Tue Apr 7 14:05:30 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D29D248861 for ; Thu, 5 Mar 2026 04:28:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1279cbd1993sm11164942c88.2.2026.03.04.20.28.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 20:28:53 -0800 (PST) From: Deepti Jaggi Date: Wed, 04 Mar 2026 20:28:29 -0800 Subject: [PATCH v5 2/3] arm64: dts: qcom: Introduce sa8255p SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260304-b4-scmi-upstream-v5-2-f8fc763d8da0@oss.qualcomm.com> References: <20260304-b4-scmi-upstream-v5-0-f8fc763d8da0@oss.qualcomm.com> In-Reply-To: <20260304-b4-scmi-upstream-v5-0-f8fc763d8da0@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prasad Sodagudi , Nikunj Kela , Shazad Hussain , Deepti Jaggi X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772684930; l=111287; i=deepti.jaggi@oss.qualcomm.com; s=20250501; h=from:subject:message-id; bh=Bu0OvzjBya/KjcQ4x+W9dIYk8kL9s+fow3YJ5i/usQI=; b=RrbDWAF0YXj9Chxi5GYI+tmlsnaBIkDmKBfmZswGD8fQ7iCkRo0L9qQK+KTk3nNlCfVk7Byj5 1fJkRFdL2ZvAYtaKXb6H1U1qEf4YZMTqvWMzUOUJ+FpwNVaan96/iiD X-Developer-Key: i=deepti.jaggi@oss.qualcomm.com; a=ed25519; pk=+b3H5UC/u0pUK5+btJ+35nW+6vKwJV1CfjJ1CJWuOZw= X-Authority-Analysis: v=2.4 cv=e6wLiKp/ c=1 sm=1 tr=0 ts=69a90689 cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=TEjjMiGAkk3_VdAh1egA:9 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: phVi4j0N_nm6hEjxkg21ktddIMQuKqct X-Proofpoint-GUID: phVi4j0N_nm6hEjxkg21ktddIMQuKqct X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDAzMSBTYWx0ZWRfXxYfsRtvfOm4H pgcIbTlHXl65qHXUEtm2O6BnwIorDVWmbcFTIioLqT1GCmzazzlXDgqPARNJVcYeXVWFFfuM4Fz SsZaVJKrkEmAZTon5cLzNwwboqklMWiBBCk6hv4pWVLdbuAaufo6LGUAEsUQk++RcENzooayERg OSCHQH2MjSDRi3M3Xm5zPTVhi/qFAGwxi5HFk4ZYazkHg7YqQozshYieJujRqMQ/0Cgm0y5J4lE iQMxjm8HqvmZD4wcc/yczd89HVMfUZ0VNdsscAHhCttxe2fz0GESCMTZA/Yi6+PBrdlaWsjfbHO NFFSB0CHJpJx4ToGg4KFCmHcSrzh58a5mcaYSteiLfyeg/zDVB01VU3jBNJDwQp0Tk+WPMSpdjC W/wt5vUGC6NoFzBtU2LR0qVJbZ1K9KOjzEfTu/G1IPq5ORk+rdRnu4xKO3SXMqbP6BmpNSEq5d3 qW3a9IL/7GuwOCF6TiA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-04_09,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603050031 From: Nikunj Kela Introduce base device tree support for sa8255p Qualcomm's automotive infotainment SoC. The base dt file describes core SoC components- CPUs, CPU map, ipcc, QUP, geni UART, interrupt controller, TLMM, reserved memory, SMMU, firmware scm, scmi, watchdog, SRAM, PSCI, ufs, pcie, pmu nodes and enable booting to shell with ramdisk. The Qualcomm automotive sa8255p SoC utilizes firmware to configure platform resources such as clocks, interconnects, and TLMM. Device drivers request these resources through the SCMI power,reset and performance protocols. Assign each device driver a dedicated SCMI channel and Tx/Rx doorbells to support parallel resource requests and aggregation in the SCMI platform server. Operate the SCMI server stack in an SMP-enabled VM, using the Qualcomm SMC/HVC transport driver for communication. Group resource operations to improve abstraction and reduce the number of SCMI requests. Follow the SCMI-based resource management approach demonstrated by Qualcomm at LinaroConnect 2024.[1] Limit initial support to basic platform resources, serial console, ufs and pcie.Defer enabling USB, and Ethernet to subsequent updates. [1]: https://resources.linaro.org/en/resource/wfnfEwBhRjLV1PEAJoDDte Co-developed-by: Shazad Hussain Signed-off-by: Shazad Hussain Signed-off-by: Nikunj Kela Co-developed-by: Deepti Jaggi Signed-off-by: Deepti Jaggi Reviewed-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sa8255p.dtsi | 4861 +++++++++++++++++++++++++++++= ++++ 1 file changed, 4861 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8255p.dtsi b/arch/arm64/boot/dts/qc= om/sa8255p.dtsi new file mode 100644 index 000000000000..4f8529db70f6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8255p.dtsi @@ -0,0 +1,4861 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_board_clk>; + clock-mult =3D <1>; + clock-div =3D <2>; + #clock-cells =3D <0>; + }; + + gpll0_board_clk: gpll0-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + xo_board_clk: xo-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + next-level-cache =3D <&l2_1>; + l2_1: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + next-level-cache =3D <&l2_2>; + l2_2: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + next-level-cache =3D <&l2_3>; + l2_3: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu4: cpu@10000 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x10000>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + next-level-cache =3D <&l2_4>; + l2_4: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_1>; + l3_1: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + + }; + }; + + cpu5: cpu@10100 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x10100>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + next-level-cache =3D <&l2_5>; + l2_5: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; + }; + + cpu6: cpu@10200 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x10200>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + next-level-cache =3D <&l2_6>; + l2_6: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; + }; + + cpu7: cpu@10300 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x10300>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + next-level-cache =3D <&l2_7>; + l2_7: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + }; + + firmware: firmware { + scm { + compatible =3D "qcom,scm-sa8255p", "qcom,scm"; + memory-region =3D <&tz_ffi_mem>; + qcom,dload-mode =3D <&tcsr 0x13000>; + }; + + scmi0: scmi-0 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem0>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi0_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi0_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi0_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi1: scmi-1 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem1>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi1_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi1_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi1_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi2: scmi-2 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem2>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi2_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi2_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi2_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi3: scmi-3 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem3>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi3_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi3_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi3_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi4: scmi-4 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem4>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi4_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi4_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi4_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi5: scmi-5 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem5>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi5_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi5_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi5_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi6: scmi-6 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem6>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi6_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi6_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi6_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi7: scmi-7 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem7>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi7_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi7_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi7_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi8: scmi-8 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem8>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi8_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi8_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi8_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi9: scmi-9 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem9>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi9_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi9_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi9_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi10: scmi-10 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem10>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi10_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi10_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi10_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi11: scmi-11 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem11>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi11_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi11_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi11_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi12: scmi-12 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem12>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi12_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi12_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi12_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi13: scmi-13 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem13>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi13_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi13_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi13_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi14: scmi-14 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem14>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi14_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi14_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi14_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi15: scmi-15 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem15>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi15_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi15_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi15_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi16: scmi-16 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem16>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi16_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi16_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi16_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi17: scmi-17 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem17>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi17_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi17_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi17_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi18: scmi-18 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem18>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi18_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi18_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi18_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi19: scmi-19 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem19>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi19_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi19_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi19_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi20: scmi-20 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem20>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi20_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi20_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi20_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi21: scmi-21 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem21>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi21_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi21_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi21_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi22: scmi-22 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem22>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi22_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi22_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi22_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi23: scmi-23 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem23>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi23_sensor: protocol@15 { + reg =3D <0x15>; + #thermal-sensor-cells =3D <1>; + }; + }; + + scmi24: scmi-24 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem24>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi24_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi24_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi24_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi25: scmi-25 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem25>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi25_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi25_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi25_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi26: scmi-26 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem26>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi26_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi26_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi26_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi27: scmi-27 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem27>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi27_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi27_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi27_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi28: scmi-28 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem28>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi28_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi28_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi28_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi29: scmi-29 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem29>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi29_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi29_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi29_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi30: scmi-30 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem30>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi30_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi30_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi30_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi31: scmi-31 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem31>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi31_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi31_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi31_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi32: scmi-32 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem32>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi32_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi32_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi32_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi33: scmi-33 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem33>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi33_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi33_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi33_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi34: scmi-34 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem34>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi34_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi34_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi34_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi35: scmi-35 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem35>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi35_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi35_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi35_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi36: scmi-36 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem36>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi36_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi36_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi36_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi37: scmi-37 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem37>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi37_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi37_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi37_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi38: scmi-38 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem38>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi38_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi38_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi38_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi39: scmi-39 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem39>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi39_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi39_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi39_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi40: scmi-40 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem40>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi40_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi40_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi40_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi41: scmi-41 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem41>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi41_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi41_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi41_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi42: scmi-42 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem42>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi42_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi42_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi42_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi43: scmi-43 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem43>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi43_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi43_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi43_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi44: scmi-44 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem44>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi44_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi44_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi44_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi45: scmi-45 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem45>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi45_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi45_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi45_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi46: scmi-46 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem46>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi46_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi46_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi46_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi47: scmi-47 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem47>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi47_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi47_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi47_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi48: scmi-48 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem48>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi48_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi48_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi48_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi49: scmi-49 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem49>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi49_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi49_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi49_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi50: scmi-50 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem50>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi50_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi50_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi50_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi51: scmi-51 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem51>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi51_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi51_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi51_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi52: scmi-52 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem52>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi52_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi52_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi52_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi53: scmi-53 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem53>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi53_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi53_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi53_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi54: scmi-54 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem54>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi54_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi54_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi54_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi55: scmi-55 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem55>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi55_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi55_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi55_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi56: scmi-56 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem56>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi56_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi56_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi56_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi57: scmi-57 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem57>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi57_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi57_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi57_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi58: scmi-58 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem58>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi58_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi58_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi58_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi59: scmi-59 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem59>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi59_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi59_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi59_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi60: scmi-60 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem60>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi60_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi60_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi60_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi61: scmi-61 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem61>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi61_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi61_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi61_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi62: scmi-62 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem62>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi62_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi62_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi62_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi63: scmi-63 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem63>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi63_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi63_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi63_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + sail_ss_mem: sail-ss@80000000 { + reg =3D <0x0 0x80000000 0x0 0x10000000>; + no-map; + }; + + hyp_mem: hyp@90000000 { + reg =3D <0x0 0x90000000 0x0 0x600000>; + no-map; + }; + + xbl_boot_mem: xbl-boot@90700000 { + reg =3D <0x0 0x90700000 0x0 0x100000>; + no-map; + }; + + aop_image_mem: aop-image@90800000 { + reg =3D <0x0 0x90800000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@90860000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x90860000 0x0 0x20000>; + no-map; + }; + + uefi_log: uefi-log@908b0000 { + reg =3D <0x0 0x908b0000 0x0 0x10000>; + no-map; + }; + + ddr_training_checksum: ddr-training-checksum@908c0000 { + reg =3D <0x0 0x908c0000 0x0 0x1000>; + no-map; + }; + + reserved_mem: reserved@908f0000 { + reg =3D <0x0 0x908f0000 0x0 0xe000>; + no-map; + }; + + secdata_apss_mem: secdata-apss@908fe000 { + reg =3D <0x0 0x908fe000 0x0 0x2000>; + no-map; + }; + + smem_mem: smem@90900000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x90900000 0x0 0x200000>; + no-map; + hwlocks =3D <&tcsr_mutex 3>; + }; + + tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { + reg =3D <0x0 0x90c00000 0x0 0x100000>; + no-map; + }; + + sail_mailbox_mem: sail-ss@90d00000 { + reg =3D <0x0 0x90d00000 0x0 0x100000>; + no-map; + }; + + sail_ota_mem: sail-ss@90e00000 { + reg =3D <0x0 0x90e00000 0x0 0x300000>; + no-map; + }; + + hyp_md_mem: hyp-md@91a80000 { + no-map; + reg =3D <0x0 0x91a80000 0x0 0x80000>; + }; + + aoss_backup_mem: aoss-backup@91b00000 { + reg =3D <0x0 0x91b00000 0x0 0x40000>; + no-map; + }; + + cpucp_backup_mem: cpucp-backup@91b40000 { + reg =3D <0x0 0x91b40000 0x0 0x40000>; + no-map; + }; + + tz_config_backup_mem: tz-config-backup@91b80000 { + reg =3D <0x0 0x91b80000 0x0 0x10000>; + no-map; + }; + + ddr_training_data_mem: ddr-training-data@91b90000 { + reg =3D <0x0 0x91b90000 0x0 0x10000>; + no-map; + }; + + cdt_data_backup_mem: cdt-data-backup@91ba0000 { + reg =3D <0x0 0x91ba0000 0x0 0x1000>; + no-map; + }; + + tz_ffi_mem: tz-ffi@91c00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x91c00000 0x0 0x1400000>; + no-map; + }; + + lpass_machine_learning_mem: lpass-machine-learning@93b00000 { + reg =3D <0x0 0x93b00000 0x0 0xf00000>; + no-map; + }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { + reg =3D <0x0 0x94a00000 0x0 0x800000>; + no-map; + }; + + pil_camera_mem: pil-camera@95200000 { + reg =3D <0x0 0x95200000 0x0 0x500000>; + no-map; + }; + + pil_adsp_mem: pil-adsp@95c00000 { + reg =3D <0x0 0x95c00000 0x0 0x1e00000>; + no-map; + }; + + pil_adsp_dtb_mem: q6-adsp-dtb@97a00000 { + no-map; + reg =3D <0x0 0x97a00000 0x0 0x80000>; + }; + + pil_gdsp0_dtb_mem: pil-gdsp0-dtb@97a80000 { + no-map; + reg =3D <0x0 0x97a80000 0x0 0x80000>; + }; + + pil_gdsp0_mem: pil-gdsp0@97b00000 { + reg =3D <0x0 0x97b00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_mem: pil-gdsp1@99900000 { + reg =3D <0x0 0x99900000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_dtb_mem: pil-gdsp1-dtb@9b700000 { + no-map; + reg =3D <0x0 0x9b700000 0x0 0x80000>; + }; + + pil_cdsp0_dtb_mem: pil-cdsp0-dtb@9b780000 { + no-map; + reg =3D <0x0 0x9b780000 0x0 0x80000>; + }; + + pil_cdsp0_mem: pil-cdsp0@9b800000 { + reg =3D <0x0 0x9b800000 0x0 0x1e00000>; + no-map; + }; + + pil_gpu_mem: pil-gpu@9d600000 { + reg =3D <0x0 0x9d600000 0x0 0x2000>; + no-map; + }; + + pil_cdsp1_dtb_mem: pil-cdsp1-dtb@9d680000 { + no-map; + reg =3D <0x0 0x9d680000 0x0 0x80000>; + }; + + pil_cdsp1_mem: pil-cdsp1@9d700000 { + reg =3D <0x0 0x9d700000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f500000 { + reg =3D <0x0 0x9f500000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9fc00000 { + reg =3D <0x0 0x9fc00000 0x0 0x700000>; + no-map; + }; + + audio_config_mem: audio-config-region@ac600000 { + no-map; + reg =3D <0x0 0xac600000 0x0 0xa00000>; + }; + + audio_mdf_mem: audio-mdf-region@ad000000 { + reg =3D <0x0 0xad000000 0x0 0x2000000>; + no-map; + }; + + firmware_mem: firmware-region@b0000000 { + reg =3D <0x0 0xb0000000 0x0 0x800000>; + no-map; + }; + + hyptz_reserved_mem: hyptz-reserved@beb00000 { + reg =3D <0x0 0xbeb00000 0x0 0x11500000>; + no-map; + }; + + shmem0: scmi-mem@d0000000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0000000 0x0 0x1000>; + no-map; + }; + + shmem1: scmi-mem@d0001000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0001000 0x0 0x1000>; + no-map; + }; + + shmem2: scmi-mem@d0002000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0002000 0x0 0x1000>; + no-map; + }; + + shmem3: scmi-mem@d0003000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0003000 0x0 0x1000>; + no-map; + }; + + shmem4: scmi-mem@d0004000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0004000 0x0 0x1000>; + no-map; + }; + + shmem5: scmi-mem@d0005000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0005000 0x0 0x1000>; + no-map; + }; + + shmem6: scmi-mem@d0006000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0006000 0x0 0x1000>; + no-map; + }; + + shmem7: scmi-mem@d0007000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0007000 0x0 0x1000>; + no-map; + }; + + shmem8: scmi-mem@d0008000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0008000 0x0 0x1000>; + no-map; + }; + + shmem9: scmi-mem@d0009000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0009000 0x0 0x1000>; + no-map; + }; + + shmem10: scmi-mem@d000a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd000a000 0x0 0x1000>; + no-map; + }; + + shmem11: scmi-mem@d000b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd000b000 0x0 0x1000>; + no-map; + }; + + shmem12: scmi-mem@d000c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd000c000 0x0 0x1000>; + no-map; + }; + + shmem13: scmi-mem@d000d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd000d000 0x0 0x1000>; + no-map; + }; + + shmem14: scmi-mem@d000e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd000e000 0x0 0x1000>; + no-map; + }; + + shmem15: scmi-mem@d000f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd000f000 0x0 0x1000>; + no-map; + }; + + shmem16: scmi-mem@d0010000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0010000 0x0 0x1000>; + no-map; + }; + + shmem17: scmi-mem@d0011000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0011000 0x0 0x1000>; + no-map; + }; + + shmem18: scmi-mem@d0012000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0012000 0x0 0x1000>; + no-map; + }; + + shmem19: scmi-mem@d0013000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0013000 0x0 0x1000>; + no-map; + }; + + shmem20: scmi-mem@d0014000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0014000 0x0 0x1000>; + no-map; + }; + + shmem21: scmi-mem@d0015000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0015000 0x0 0x1000>; + no-map; + }; + + shmem22: scmi-mem@d0016000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0016000 0x0 0x1000>; + no-map; + }; + + shmem23: scmi-mem@d0017000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0017000 0x0 0x1000>; + no-map; + }; + + shmem24: scmi-mem@d0018000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0018000 0x0 0x1000>; + no-map; + }; + + shmem25: scmi-mem@d0019000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0019000 0x0 0x1000>; + no-map; + }; + + shmem26: scmi-mem@d001a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd001a000 0x0 0x1000>; + no-map; + }; + + shmem27: scmi-mem@d001b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd001b000 0x0 0x1000>; + no-map; + }; + + shmem28: scmi-mem@d001c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd001c000 0x0 0x1000>; + no-map; + }; + + shmem29: scmi-mem@d001d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd001d000 0x0 0x1000>; + no-map; + }; + + shmem30: scmi-mem@d001e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd001e000 0x0 0x1000>; + no-map; + }; + + shmem31: scmi-mem@d001f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd001f000 0x0 0x1000>; + no-map; + }; + + shmem32: scmi-mem@d0020000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0020000 0x0 0x1000>; + no-map; + }; + + shmem33: scmi-mem@d0021000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0021000 0x0 0x1000>; + no-map; + }; + + shmem34: scmi-mem@d0022000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0022000 0x0 0x1000>; + no-map; + }; + + shmem35: scmi-mem@d0023000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0023000 0x0 0x1000>; + no-map; + }; + + shmem36: scmi-mem@d0024000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0024000 0x0 0x1000>; + no-map; + }; + + shmem37: scmi-mem@d0025000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0025000 0x0 0x1000>; + no-map; + }; + + shmem38: scmi-mem@d0026000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0026000 0x0 0x1000>; + no-map; + }; + + shmem39: scmi-mem@d0027000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0027000 0x0 0x1000>; + no-map; + }; + + shmem40: scmi-mem@d0028000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0028000 0x0 0x1000>; + no-map; + }; + + shmem41: scmi-mem@d0029000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0029000 0x0 0x1000>; + no-map; + }; + + shmem42: scmi-mem@d002a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd002a000 0x0 0x1000>; + no-map; + }; + + shmem43: scmi-mem@d002b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd002b000 0x0 0x1000>; + no-map; + }; + + shmem44: scmi-mem@d002c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd002c000 0x0 0x1000>; + no-map; + }; + + shmem45: scmi-mem@d002d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd002d000 0x0 0x1000>; + no-map; + }; + + shmem46: scmi-mem@d002e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd002e000 0x0 0x1000>; + no-map; + }; + + shmem47: scmi-mem@d002f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd002f000 0x0 0x1000>; + no-map; + }; + + shmem48: scmi-mem@d0030000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0030000 0x0 0x1000>; + no-map; + }; + + shmem49: scmi-mem@d0031000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0031000 0x0 0x1000>; + no-map; + }; + + shmem50: scmi-mem@d0032000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0032000 0x0 0x1000>; + no-map; + }; + + shmem51: scmi-mem@d0033000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0033000 0x0 0x1000>; + no-map; + }; + + shmem52: scmi-mem@d0034000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0034000 0x0 0x1000>; + no-map; + }; + + shmem53: scmi-mem@d0035000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0035000 0x0 0x1000>; + no-map; + }; + + shmem54: scmi-mem@d0036000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0036000 0x0 0x1000>; + no-map; + }; + + shmem55: scmi-mem@d0037000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0037000 0x0 0x1000>; + no-map; + }; + + shmem56: scmi-mem@d0038000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0038000 0x0 0x1000>; + no-map; + }; + + shmem57: scmi-mem@d0039000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd0039000 0x0 0x1000>; + no-map; + }; + + shmem58: scmi-mem@d003a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd003a000 0x0 0x1000>; + no-map; + }; + + shmem59: scmi-mem@d003b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd003b000 0x0 0x1000>; + no-map; + }; + + shmem60: scmi-mem@d003c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd003c000 0x0 0x1000>; + no-map; + }; + + shmem61: scmi-mem@d003d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd003d000 0x0 0x1000>; + no-map; + }; + + shmem62: scmi-mem@d003e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd003e000 0x0 0x1000>; + no-map; + }; + + shmem63: scmi-mem@d003f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0xd003f000 0x0 0x1000>; + no-map; + }; + + firmware_logs_mem: firmware-logs@d0040000 { + reg =3D <0x0 0xd0040000 0x0 0x10000>; + no-map; + }; + + firmware_audio_mem: firmware-audio@d0050000 { + reg =3D <0x0 0xd0050000 0x0 0x4000>; + no-map; + }; + + firmware_camera_mem: firmware-camera@d0054000 { + no-map; + reg =3D <0x0 0xd0054000 0x0 0x2000>; + }; + + firmware_reserved_mem: firmware-reserved@d0056000 { + reg =3D <0x0 0xd0056000 0x0 0x9a000>; + no-map; + }; + + firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { + reg =3D <0x0 0xd00f0000 0x0 0x10000>; + no-map; + }; + + tags_mem: tags@d0100000 { + reg =3D <0x0 0xd0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@d1300000 { + reg =3D <0x0 0xd1300000 0x0 0x500000>; + no-map; + }; + + deepsleep_backup_mem: deepsleep-backup@d1800000 { + reg =3D <0x0 0xd1800000 0x0 0x100000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@d1900000 { + reg =3D <0x0 0xd1900000 0x0 0x3800000>; + no-map; + }; + + tz_stat_mem: tz-stat@db100000 { + reg =3D <0x0 0xdb100000 0x0 0x100000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw@db200000 { + reg =3D <0x0 0xdb200000 0x0 0x100000>; + no-map; + }; + + cma: linux,cma { + compatible =3D "shared-dma-pool"; + alloc-ranges =3D <0x0 0x00000000 0x0 0xdfffffff>; + reusable; + alignment =3D <0x0 0x400000>; + size =3D <0x0 0x2000000>; + linux,cma-default; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + + ipcc0: mailbox@408000 { + compatible =3D "qcom,sa8255p-ipcc", "qcom,ipcc"; + reg =3D <0x0 0x00408000 0x0 0x1000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + #mbox-cells =3D <2>; + }; + + ipcc1: mailbox@488000 { + compatible =3D "qcom,sa8255p-ipcc", "qcom,ipcc"; + reg =3D <0x0 0x00488000 0x0 0x1000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + qupv3_id_2: geniqup@8c0000 { + compatible =3D "qcom,sa8255p-geni-se-qup"; + reg =3D <0x0 0x008c0000 0x0 0x6000>; + ranges; + iommus =3D <&apps_smmu 0x5a3 0x0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + status =3D "disabled"; + + uart14: serial@880000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart15: serial@884000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart16: serial@888000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart17: serial@88c000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart18: serial@890000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart19: serial@894000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00894000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart20: serial@898000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00898000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible =3D "qcom,sa8255p-geni-se-qup"; + reg =3D <0x0 0x9c0000 0x0 0x6000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + iommus =3D <&apps_smmu 0x403 0x0>; + status =3D "disabled"; + + uart0: serial@980000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x980000 0x0 0x4000>; + interrupts =3D ; + power-domains =3D <&scmi11_pd 0>, <&scmi11_dvfs 0>; + power-domain-names =3D "power", "perf"; + status =3D "disabled"; + }; + + uart1: serial@984000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x984000 0x0 0x4000>; + interrupts =3D ; + power-domains =3D <&scmi11_pd 1>, <&scmi11_dvfs 1>; + power-domain-names =3D "power", "perf"; + status =3D "disabled"; + }; + + uart2: serial@988000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x988000 0x0 0x4000>; + interrupts =3D ; + power-domains =3D <&scmi11_pd 2>, <&scmi11_dvfs 2>; + power-domain-names =3D "power", "perf"; + status =3D "disabled"; + }; + + uart3: serial@98c000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x98c000 0x0 0x4000>; + interrupts =3D ; + power-domains =3D <&scmi11_pd 3>, <&scmi11_dvfs 3>; + power-domain-names =3D "power", "perf"; + status =3D "disabled"; + }; + + uart4: serial@990000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x990000 0x0 0x4000>; + interrupts =3D ; + power-domains =3D <&scmi11_pd 4>, <&scmi11_dvfs 4>; + power-domain-names =3D "power", "perf"; + status =3D "disabled"; + }; + + uart5: serial@994000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x994000 0x0 0x4000>; + interrupts =3D ; + power-domains =3D <&scmi11_pd 5>, <&scmi11_dvfs 5>; + power-domain-names =3D "power", "perf"; + status =3D "disabled"; + }; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible =3D "qcom,sa8255p-geni-se-qup"; + reg =3D <0x0 0x00ac0000 0x0 0x6000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + iommus =3D <&apps_smmu 0x443 0x0>; + status =3D "disabled"; + + uart7: serial@a80000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + interrupts =3D ; + power-domains =3D <&scmi11_pd 7>, <&scmi11_dvfs 7>; + power-domain-names =3D "power", "perf"; + status =3D "disabled"; + }; + + uart8: serial@a84000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + interrupts =3D ; + power-domains =3D <&scmi11_pd 8>, <&scmi11_dvfs 8>; + power-domain-names =3D "power", "perf"; + status =3D "disabled"; + }; + + uart9: serial@a88000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0xa88000 0x0 0x4000>; + interrupts =3D ; + power-domains =3D <&scmi11_pd 9>, <&scmi11_dvfs 9>; + power-domain-names =3D "power", "perf"; + status =3D "disabled"; + }; + + uart10: serial@a8c000 { + compatible =3D "qcom,sa8255p-geni-debug-uart"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + interrupts =3D ; + power-domains =3D <&scmi11_pd 10>, <&scmi11_dvfs 10>; + power-domain-names =3D "power", "perf"; + status =3D "disabled"; + }; + + uart11: serial@a90000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + interrupts =3D ; + power-domains =3D <&scmi11_pd 11>, <&scmi11_dvfs 11>; + power-domain-names =3D "power", "perf"; + status =3D "disabled"; + }; + + uart12: serial@a94000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + interrupts =3D ; + power-domains =3D <&scmi11_pd 12>, <&scmi11_dvfs 12>; + power-domain-names =3D "power", "perf"; + status =3D "disabled"; + }; + + }; + + qupv3_id_3: geniqup@bc0000 { + compatible =3D "qcom,sa8255p-geni-se-qup"; + reg =3D <0x0 0xbc0000 0x0 0x6000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + iommus =3D <&apps_smmu 0x43 0x0>; + status =3D "disabled"; + + uart21: serial@b80000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00b80000 0x0 0x4000>; + interrupts =3D ; + power-domains =3D <&scmi11_pd 21>, <&scmi11_dvfs 21>; + power-domain-names =3D "power", "perf"; + status =3D "disabled"; + }; + }; + + rng: rng@10d2000 { + compatible =3D "qcom,sa8255p-trng", "qcom,trng"; + reg =3D <0x0 0x010d2000 0x0 0x1000>; + }; + + pcie0_ep: pcie-ep@1c00000 { + compatible =3D "qcom,sa8255p-pcie-ep"; + reg =3D <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40200000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>, + <0x0 0x40005000 0x0 0x2000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + interrupts =3D , + , + ; + interrupt-names =3D "global", "doorbell", "dma"; + + dma-coherent; + iommus =3D <&pcie_smmu 0x0000 0x7f>; + + num-lanes =3D <2>; + power-domains =3D <&scmi5_pd 1>; + + status =3D "disabled"; + }; + + pcie1_ep: pcie-ep@1c10000 { + compatible =3D "qcom,sa8255p-pcie-ep"; + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60200000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>, + <0x0 0x60005000 0x0 0x2000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + interrupts =3D , + , + ; + + interrupt-names =3D "global", "doorbell", "dma"; + + dma-coherent; + iommus =3D <&pcie_smmu 0x80 0x7f>; + num-lanes =3D <4>; + power-domains =3D <&scmi6_pd 1>; + + status =3D "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible =3D "qcom,sa8255p-ufshc"; + reg =3D <0x0 0x01d84000 0x0 0x3000>; + + interrupts =3D ; + + iommus =3D <&apps_smmu 0x100 0x0>; + dma-coherent; + + lanes-per-direction =3D <2>; + power-domains =3D <&scmi3_pd 0>; + + status =3D "disabled"; + }; + + ufs_mem_hc2: ufs2@1da4000 { + compatible =3D "qcom,sa8255p-ufshc"; + reg =3D <0x0 0x1da4000 0x0 0x3000>; + + interrupts =3D ; + + iommus =3D <&apps_smmu 0x420 0x0>; + dma-coherent; + + lanes-per-direction =3D <2>; + power-domains =3D <&scmi4_pd 0>; + + status =3D "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1fc0000 { + compatible =3D "qcom,sa8255p-tcsr", "syscon"; + reg =3D <0x0 0x1fc0000 0x0 0x30000>; + }; + + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,sa8255p-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x20000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <2>; + dma-coherent; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + power-domains =3D <&scmi15_pd 0>; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,sa8255p-pdc", "qcom,pdc"; + reg =3D <0x0 0x0b220000 0x0 0x30000>, + <0x0 0x17c000f0 0x0 0x64>; + qcom,pdc-ranges =3D <0 480 40>, + <40 140 14>, + <54 263 1>, + <55 306 4>, + <59 312 3>, + <62 374 2>, + <64 434 2>, + <66 438 2>, + <70 520 1>, + <73 523 1>, + <118 568 6>, + <124 609 3>, + <159 638 1>, + <160 720 3>, + <169 728 30>, + <199 416 2>, + <201 449 1>, + <202 89 1>, + <203 451 1>, + <204 462 1>, + <205 264 1>, + <206 579 1>, + <207 653 1>, + <208 656 1>, + <209 659 1>, + <210 122 1>, + <211 699 1>, + <212 705 1>, + <213 450 1>, + <214 643 2>, + <216 646 5>, + <221 390 5>, + <226 700 2>, + <228 440 1>, + <229 663 1>, + <230 524 2>, + <232 612 3>, + <235 723 5>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + tsens2: thermal-sensor@c251000 { + compatible =3D "qcom,sa8255p-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c251000 0x0 0x1ff>, + <0x0 0x0c224000 0x0 0x8>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + #qcom,sensors =3D <13>; + }; + + tsens3: thermal-sensor@c252000 { + compatible =3D "qcom,sa8255p-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c252000 0x0 0x1ff>, + <0x0 0x0c225000 0x0 0x8>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + #qcom,sensors =3D <13>; + }; + + tsens0: thermal-sensor@c263000 { + compatible =3D "qcom,sa8255p-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c263000 0x0 0x1ff>, + <0x0 0x0c222000 0x0 0x8>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + #qcom,sensors =3D <12>; + }; + + tsens1: thermal-sensor@c265000 { + compatible =3D "qcom,sa8255p-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c265000 0x0 0x1ff>, + <0x0 0x0c223000 0x0 0x8>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + #qcom,sensors =3D <12>; + }; + + aoss_qmp: power-management@c300000 { + compatible =3D "qcom,sa8255p-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0x0 0x0c300000 0x0 0x400>; + interrupts-extended =3D <&ipcc0 IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc0 IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + #clock-cells =3D <0>; + }; + + tlmm: pinctrl@f000000 { + compatible =3D "qcom,sa8255p-tlmm", "qcom,sa8775p-tlmm"; + reg =3D <0x0 0x0f000000 0x0 0x1000000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 149>; + wakeup-parent =3D <&pdc>; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,sa8255p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x15000000 0x0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <2>; + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pcie_smmu: iommu@15200000 { + compatible =3D "qcom,sa8255p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x15200000 0x0 0x80000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <2>; + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17a00000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupt-controller; + #address-cells =3D <2>; + #size-cells =3D <2>; + #interrupt-cells =3D <3>; + interrupts =3D ; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x20000>; + }; + + watchdog@17c10000 { + compatible =3D "qcom,apss-wdt-sa8255p", "qcom,kpss-wdt"; + reg =3D <0x0 0x17c10000 0x0 0x1000>; + clocks =3D <&sleep_clk>; + interrupts =3D ; + }; + + memtimer: timer@17c20000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17c20000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x0 0x20000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@17c21000 { + reg =3D <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + interrupts =3D , + ; + frame-number =3D <0>; + }; + + frame@17c23000 { + reg =3D <0x17c23000 0x1000>; + interrupts =3D ; + frame-number =3D <1>; + status =3D "disabled"; + }; + + frame@17c25000 { + reg =3D <0x17c25000 0x1000>; + interrupts =3D ; + frame-number =3D <2>; + status =3D "disabled"; + }; + + frame@17c27000 { + reg =3D <0x17c27000 0x1000>; + interrupts =3D ; + frame-number =3D <3>; + status =3D "disabled"; + }; + + frame@17c29000 { + reg =3D <0x17c29000 0x1000>; + interrupts =3D ; + frame-number =3D <4>; + status =3D "disabled"; + }; + + frame@17c2b000 { + reg =3D <0x17c2b000 0x1000>; + interrupts =3D ; + frame-number =3D <5>; + status =3D "disabled"; + }; + + frame@17c2d000 { + reg =3D <0x17c2d000 0x1000>; + interrupts =3D ; + frame-number =3D <6>; + status =3D "disabled"; + }; + }; + + cpufreq_hw: cpufreq@18591000 { + compatible =3D "qcom,sa8255p-cpufreq-epss", + "qcom,cpufreq-epss"; + reg =3D <0x0 0x18591000 0x0 0x1000>, + <0x0 0x18593000 0x0 0x1000>; + reg-names =3D "freq-domain0", "freq-domain1"; + clocks =3D <&bi_tcxo_div2>, <&gpll0_board_clk>; + clock-names =3D "xo", "alternate"; + interrupts =3D , + ; + interrupt-names =3D "dcvsh-irq-0", "dcvsh-irq-1"; + #freq-domain-cells =3D <1>; + }; + + pcie0: pcie@400000000 { + compatible =3D "qcom,pcie-sa8255p"; + reg =3D <0x4 0x00000000 0x0 0x10000000>; + device_type =3D "pci"; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>, + <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x100000>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <0>; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + interrupt-parent =3D <&intc>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + iommu-map =3D <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>, + <0x200 &pcie_smmu 0x0002 0x1>, + <0x300 &pcie_smmu 0x0003 0x1>; + + power-domains =3D <&scmi5_pd 0>; + status =3D "disabled"; + + pcieport0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie1: pcie@600000000 { + compatible =3D "qcom,pcie-sa8255p"; + reg =3D <0x6 0x00000000 0x0 0x10000000>; + + device_type =3D "pci"; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x02000000 0x0 0x60100000 0x0 0x60100000 0x0 0x1ff00000>, + <0x43000000 0x6 0x10100000 0x6 0x10100000 0x0 0x100000>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <1>; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + + interrupt-parent =3D <&intc>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + iommu-map =3D <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>, + <0x200 &pcie_smmu 0x0082 0x1>, + <0x208 &pcie_smmu 0x0083 0x1>, + <0x210 &pcie_smmu 0x0084 0x1>, + <0x300 &pcie_smmu 0x0085 0x1>, + <0xab00 &pcie_smmu 0x0086 0x1>; + + power-domains =3D <&scmi6_pd 0>; + status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + }; + + thermal-zones { + aoss-0-thermal { + thermal-sensors =3D <&tsens0 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-0-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-1-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-2-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-3-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + audio-thermal { + thermal-sensors =3D <&tsens0 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + camss-0-thermal { + thermal-sensors =3D <&tsens0 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + pcie-0-thermal { + thermal-sensors =3D <&tsens0 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpuss-0-0-thermal { + thermal-sensors =3D <&tsens0 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + aoss-1-thermal { + thermal-sensors =3D <&tsens1 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-0-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-1-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-2-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-3-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-3-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-4-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + gpuss-5-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + video-thermal { + thermal-sensors =3D <&tsens1 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + camss-1-thermal { + thermal-sensors =3D <&tsens1 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + pcie-1-thermal { + thermal-sensors =3D <&tsens1 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpuss-0-1-thermal { + thermal-sensors =3D <&tsens1 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + aoss-2-thermal { + thermal-sensors =3D <&tsens2 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-0-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-1-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-2-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-3-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-0-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-1-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-2-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-0-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-1-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-2-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddrss-0-thermal { + thermal-sensors =3D <&tsens2 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpuss-1-0-thermal { + thermal-sensors =3D <&tsens2 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + aoss-3-thermal { + thermal-sensors =3D <&tsens3 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-0-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-1-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-2-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-3-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-0-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-1-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-2-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-0-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-1-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-2-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + ddrss-1-thermal { + thermal-sensors =3D <&tsens3 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + }; + }; + + cpuss-1-1-thermal { + thermal-sensors =3D <&tsens3 12>; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1279cbd1993sm11164942c88.2.2026.03.04.20.28.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 20:28:54 -0800 (PST) From: Deepti Jaggi Date: Wed, 04 Mar 2026 20:28:30 -0800 Subject: [PATCH v5 3/3] arm64: dts: qcom: sa8255p: Enable sa8255p-ride board support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260304-b4-scmi-upstream-v5-3-f8fc763d8da0@oss.qualcomm.com> References: <20260304-b4-scmi-upstream-v5-0-f8fc763d8da0@oss.qualcomm.com> In-Reply-To: <20260304-b4-scmi-upstream-v5-0-f8fc763d8da0@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prasad Sodagudi , Nikunj Kela , Shazad Hussain , Deepti Jaggi X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772684930; l=5572; i=deepti.jaggi@oss.qualcomm.com; s=20250501; h=from:subject:message-id; bh=IWhdCAnf38p0QfUFQDDgfqqYqbAllDJ54p52qROUU6s=; b=R9+F4R3m9iwbJxBDMl8BD3dpDGb1Lvq4GkQD2BbdQGucbUmEF/6HRusPiIcr69QDCDzFTCTxc YEROYTS18rPDGYXGPct1UC5vJ/polrlWP1TFlvvR59WmduDzFzwsiPD X-Developer-Key: i=deepti.jaggi@oss.qualcomm.com; a=ed25519; pk=+b3H5UC/u0pUK5+btJ+35nW+6vKwJV1CfjJ1CJWuOZw= X-Proofpoint-ORIG-GUID: NULfid22CVEiHsuT659v77KqSiBVdvs0 X-Authority-Analysis: v=2.4 cv=Gu9PO01C c=1 sm=1 tr=0 ts=69a90688 cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=FU41NW7tA04laxmgGA4A:9 a=QEXdDO2ut3YA:10 a=Kq8ClHjjuc5pcCNDwlU0:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: NULfid22CVEiHsuT659v77KqSiBVdvs0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDAzMSBTYWx0ZWRfX2VSQgmZrK4FV w6u4L3P6LKFpVStw9jkZhZUpwkgME6SYalloW09A14uAch5Z5ZJHdDeWWVx3LPvXkb0reWD7H5/ A9tI/EtnSRLAb4lpnxVaxiSNn6mBfnuF4117OVcK/lA5m9C5pnnfVzrwOE25QOyW38J62fbyMHI YGtrxqzguiF0Ues7yD5dh9WS1Kiln8QFD9tAI2bA4jtonyKwdiHay+00mUbBiSa7NMkOjl5zVwB 5gf7U/kmWCm5TijFoyv4gDmiBGUoWWn/frTD8fE2ApDOGXjL7PqHAIU8MkymAtVu2wDXpONoPGU mOjvaYSCtP/yucN1xePs8guoCfNqhd1KLgIyJdA71vFV2bIKDSLJ1NHs+defgPLFFnq8irq97rr J8ZvDQXGldGVQ26xVhtZ7fjCxI32loSxSToqjzPeMasMC805SfnjmGLxU+K8X2kZQKza27knE6v lNX9NgwufqYiGNNavSg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-04_09,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 adultscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603050031 From: Nikunj Kela Add initial device tree support for sa822p-ride board, to boot to shell with ramdisk and rootfs on ufs and uart10 as serial console. Co-developed-by: Shazad Hussain Signed-off-by: Shazad Hussain Signed-off-by: Nikunj Kela Co-developed-by: Deepti Jaggi Signed-off-by: Deepti Jaggi Reviewed-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8255p-ride.dts | 222 ++++++++++++++++++++++++++= ++++ 2 files changed, 223 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index f80b5d9cf1e8..facfe99c2d97 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -172,6 +172,7 @@ qrb5165-rb5-vision-mezzanine-dtbs :=3D qrb5165-rb5.dtb = qrb5165-rb5-vision-mezzanin dtb-$(CONFIG_ARCH_QCOM) +=3D qrb5165-rb5-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8155p-adp.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sa8255p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8540p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8775p-ride.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8255p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8255p-ride.dts new file mode 100644 index 000000000000..6cf277fcc072 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include + +#include "sa8255p.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. SA8255P Ride"; + compatible =3D "qcom,sa8255p-ride", "qcom,sa8255p"; + + aliases { + serial0 =3D &uart10; + serial1 =3D &uart4; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + thermal-zones { + pmm8654au_0_thermal: pm8255-0-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 0>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + pmm8654au_1_thermal: pm8255-1-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 1>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + pmm8654au_2_thermal: pm8255-2-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 2>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + pmm8654au_3_thermal: pm8255-3-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&scmi23_sensor 3>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; +}; + +&gpll0_board_clk { + clock-frequency =3D <300000000>; +}; + +&pcie0_ep { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_ep_clkreq_default &pcie0_ep_perst_default + &pcie0_ep_wake_default>; + reset-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 0 GPIO_ACTIVE_HIGH>; +}; + +&pcie1_ep { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_ep_clkreq_default &pcie1_ep_perst_default + &pcie1_ep_wake_default>; + reset-gpios =3D <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 5 GPIO_ACTIVE_HIGH>; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&scmi3 { + status =3D "okay"; +}; + +&scmi4 { + status =3D "okay"; +}; + +&scmi5 { + status =3D "okay"; +}; + +&scmi6 { + status =3D "okay"; +}; + +&scmi11 { + status =3D "okay"; +}; + +&scmi15 { + status =3D "okay"; +}; + +&scmi23 { + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&uart4 { + status =3D "okay"; +}; + +&uart10 { + status =3D "okay"; +}; + +&tlmm { + pcie0_ep_clkreq_default: pcie-ep-clkreq-default-state { + pins =3D "gpio1"; + function =3D "pcie0_clkreq"; + drive-strength =3D <2>; + bias-disable; + }; + + pcie0_ep_perst_default: pcie-ep-perst-default-state { + pins =3D "gpio2"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-pull-down; + }; + + pcie0_ep_wake_default: pcie-ep-wake-default-state { + pins =3D "gpio0"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + pcie1_ep_clkreq_default: pcie-ep-clkreq-default-state { + pins =3D "gpio3"; + function =3D "pcie1_clkreq"; + drive-strength =3D <2>; + bias-disable; + }; + + pcie1_ep_perst_default: pcie-ep-perst-default-state { + pins =3D "gpio4"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + pcie1_ep_wake_default: pcie-ep-wake-default-state { + pins =3D "gpio5"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; +}; + +&ufs_mem_hc { + status =3D "okay"; +}; + +&xo_board_clk { + clock-frequency =3D <38400000>; +}; --=20 2.43.0