From nobody Thu Apr 9 19:19:00 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF85030EF92; Tue, 3 Mar 2026 19:10:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772565043; cv=none; b=XpLDxsGtsnsXslQGnVco7ZB0BKHHTvsM0bPRwlDE0a/QxQWPKdD+1eXAtPwwcxUJGXBrueBu9x8UJCsA7ubJuIdnHPEzQFFOLzlN/6/6/YYZkl86KTAcmj5nkDiZEXAfDO2iBjGsqWxqLmLLQWj3SWL7Qx+ZqV+bXZJMP8IS7CY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772565043; c=relaxed/simple; bh=FrKhKH8u6PYA+AIVV2zodeRPna/4G+MWYdfsznb+nOU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hTTvBRj43/0Ny3l2mkOzrMm5NYj5CHH8iMskpbtsOFJ28B37U8KHsbg4J7EwVHXJ58oPLtZkNZqO6507itQY21ncTuNyKG0hRCV7MOdQLW1xdErRF41KYv9iAfEJvPZi4VKMbP+BVtWeCQ+05bngaCythQDPuyn2ADiCHPUcdvU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=oaJHT7LM; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="oaJHT7LM" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B452020CDA2; Tue, 3 Mar 2026 20:10:34 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1772565039; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=W+99vBF6+noQZFKfqEyxi1GoYX1wO7PB5DYOpXOMID0=; b=oaJHT7LM++Tg5TrOr4NzzfntKBvw+DcjZV+6UerjhwD9eSAooNp7LI1vDK9Z/TP6f5PB6Y Ed3mh6JR8dgT0fo4PFQDrzY8CZiOii3y6Z6wH1fdZk/TeqsIco7/3TbifrQyBNkGtssPnA +Vem5nbk51HFBaJ6g6jcRVkWQwLl9dNtt1sSUnQDgKGZXAg1NVxsiEgNcwCQpaOBv9XWfC qcD+u6FFg//aYqjtablpWLfF+NJ0vcc2QSOzqPekv5FK1IWZwgX0wvjvMtJWFLvqwoe95/ xjgK+tQEEtf93AiFE5bUk9eGdhZWEh5AfFC+DUGD3fmHPSIxBMZKYFD0o+1V7A== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: naseefkm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, cjd@cjdns.fr, tsbogend@alpha.franken.de, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com, vkoul@kernel.org, neil.armstrong@linaro.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, nbd@nbd.name, ansuelsmth@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/8] phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs. Date: Tue, 3 Mar 2026 19:09:44 +0000 Message-Id: <20260303190948.694783-5-cjd@cjdns.fr> In-Reply-To: <20260303190948.694783-1-cjd@cjdns.fr> References: <20260303190948.694783-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Introduce support for EcoNet PCIe PHY controllers found in EN751221 and EN7528 SoCs, these SoCs are not identical but are similar, each having one Gen1 port, and one Gen1/Gen2 port. Co-developed-by: Ahmed Naseef Signed-off-by: Ahmed Naseef [cjd@cjdns.fr: add EN751221 support and refactor for clarity] Co-developed-by: Caleb James DeLisle Signed-off-by: Caleb James DeLisle --- MAINTAINERS | 1 + drivers/phy/Kconfig | 12 +++ drivers/phy/Makefile | 1 + drivers/phy/phy-econet-pcie.c | 180 ++++++++++++++++++++++++++++++++++ 4 files changed, 194 insertions(+) create mode 100644 drivers/phy/phy-econet-pcie.c diff --git a/MAINTAINERS b/MAINTAINERS index ae053b1f174f..5d4544590069 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9128,6 +9128,7 @@ M: Caleb James DeLisle L: linux-mips@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml +F: drivers/phy/phy-econet-pcie.c =20 ECRYPT FILE SYSTEM M: Tyler Hicks diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 02467dfd4fb0..60efc37f6eb0 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -123,6 +123,18 @@ config PHY_AIROHA_PCIE This driver create the basic PHY instance and provides initialize callback for PCIe GEN3 port. =20 +config PHY_ECONET_PCIE + tristate "EcoNet PCIe-PHY Driver" + depends on ECONET || COMPILE_TEST + depends on OF + select GENERIC_PHY + select REGMAP_MMIO + help + Say Y here to add support for EcoNet PCIe PHY driver. + This driver create the basic PHY instance and provides initialize + callback for PCIe GEN1 and GEN2 ports. This PHY is found on + EcoNet SoCs including EN751221 and EN7528. + config PHY_NXP_PTN3222 tristate "NXP PTN3222 1-port eUSB2 to USB2 redriver" depends on I2C diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index a648c2e02a83..a77f182ee8f3 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) +=3D phy-pistachio-usb.o obj-$(CONFIG_PHY_SNPS_EUSB2) +=3D phy-snps-eusb2.o obj-$(CONFIG_USB_LGM_PHY) +=3D phy-lgm-usb.o obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o +obj-$(CONFIG_PHY_ECONET_PCIE) +=3D phy-econet-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) +=3D phy-nxp-ptn3222.o obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) +=3D phy-spacemit-k1-pcie.o obj-$(CONFIG_GENERIC_PHY) +=3D allwinner/ \ diff --git a/drivers/phy/phy-econet-pcie.c b/drivers/phy/phy-econet-pcie.c new file mode 100644 index 000000000000..f9d6d061f54a --- /dev/null +++ b/drivers/phy/phy-econet-pcie.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Author: Caleb James DeLisle + * Ahmed Naseef + */ + +#include +#include +#include +#include +#include +#include + +/* Rx detection timing for EN751221: 16*8 clock cycles */ +#define EN751221_RXDET_VAL 16 + +/* Rx detection timing when in power mode 3 */ +#define EN75_RXDET_P3_REG 0xa28 +#define EN75_RXDET_P3_MASK GENMASK(17, 9) + +/* Rx detection timing when in power mode 2 */ +#define EN75_RXDET_P2_REG 0xa2c +#define EN75_RXDET_P2_MASK GENMASK(8, 0) + +/* Rx impedance */ +#define EN75_RX_IMPEDANCE_REG 0xb2c +#define EN75_RX_IMPEDANCE_MASK GENMASK(13, 12) +enum en75_rx_impedance { + EN75_RX_IMPEDANCE_100_OHM =3D 0, + EN75_RX_IMPEDANCE_95_OHM =3D 1, + EN75_RX_IMPEDANCE_90_OHM =3D 2, +}; + +/* PLL Invert clock */ +#define EN75_PLL_PH_INV_REG 0x4a0 +#define EN75_PLL_PH_INV_MASK BIT(5) + +struct en75_phy_op { + u32 reg; + u32 mask; + u32 val; +}; + +struct en7528_pcie_phy { + struct regmap *regmap; + const struct en75_phy_op *data; +}; + +/* Port 0 PHY: set LCDDS_CLK_PH_INV for PLL operation */ +static const struct en75_phy_op en7528_phy_port0[] =3D { + { + .reg =3D EN75_PLL_PH_INV_REG, + .mask =3D EN75_PLL_PH_INV_MASK, + .val =3D 1, + }, + { /* sentinel */ } +}; + +/* EN7528 Port 1 PHY: Rx impedance tuning, target R -5 Ohm */ +static const struct en75_phy_op en7528_phy_port1[] =3D { + { + .reg =3D EN75_RX_IMPEDANCE_REG, + .mask =3D EN75_RX_IMPEDANCE_MASK, + .val =3D EN75_RX_IMPEDANCE_95_OHM, + }, + { /* sentinel */ } +}; + +/* EN751221 Port 1 PHY, set RX detect to 16*8 clock cycles */ +static const struct en75_phy_op en751221_phy_port1[] =3D { + { + .reg =3D EN75_RXDET_P3_REG, + .mask =3D EN75_RXDET_P3_MASK, + .val =3D EN751221_RXDET_VAL, + }, + { + .reg =3D EN75_RXDET_P2_REG, + .mask =3D EN75_RXDET_P2_MASK, + .val =3D EN751221_RXDET_VAL, + }, + { /* sentinel */ } +}; + +static int en75_pcie_phy_init(struct phy *phy) +{ + struct en7528_pcie_phy *ephy =3D phy_get_drvdata(phy); + const struct en75_phy_op *data =3D ephy->data; + int i, ret; + u32 val; + + for (i =3D 0; data[i].mask || data[i].val; i++) { + if (i) + usleep_range(1000, 2000); + + val =3D field_prep(data[i].mask, data[i].val); + + ret =3D regmap_update_bits(ephy->regmap, data[i].reg, + data[i].mask, val); + if (ret) + return ret; + } + + return 0; +} + +static const struct phy_ops en75_pcie_phy_ops =3D { + .init =3D en75_pcie_phy_init, + .owner =3D THIS_MODULE, +}; + +static int en75_pcie_phy_probe(struct platform_device *pdev) +{ + struct regmap_config regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + }; + struct device *dev =3D &pdev->dev; + const struct en75_phy_op *data; + struct phy_provider *provider; + struct en7528_pcie_phy *ephy; + void __iomem *base; + struct phy *phy; + int i; + + data =3D of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + ephy =3D devm_kzalloc(dev, sizeof(*ephy), GFP_KERNEL); + if (!ephy) + return -ENOMEM; + + ephy->data =3D data; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + /* Set max_register to highest used register */ + for (i =3D 0; data[i].mask || data[i].val; i++) + if (data[i].reg > regmap_config.max_register) + regmap_config.max_register =3D data[i].reg; + + ephy->regmap =3D devm_regmap_init_mmio(dev, base, ®map_config); + if (IS_ERR(ephy->regmap)) + return PTR_ERR(ephy->regmap); + + phy =3D devm_phy_create(dev, dev->of_node, &en75_pcie_phy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_drvdata(phy, ephy); + + provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id en75_pcie_phy_ids[] =3D { + { .compatible =3D "econet,en7528-pcie-phy0", .data =3D en7528_phy_port0 }, + { .compatible =3D "econet,en7528-pcie-phy1", .data =3D en7528_phy_port1 }, + { .compatible =3D "econet,en751221-pcie-phy0", .data =3D en7528_phy_port0= }, + { .compatible =3D "econet,en751221-pcie-phy1", .data =3D en751221_phy_por= t1 }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, en75_pcie_phy_ids); + +static struct platform_driver en75_pcie_phy_driver =3D { + .probe =3D en75_pcie_phy_probe, + .driver =3D { + .name =3D "econet-pcie-phy", + .of_match_table =3D en75_pcie_phy_ids, + }, +}; +module_platform_driver(en75_pcie_phy_driver); + +MODULE_AUTHOR("Caleb James DeLisle "); +MODULE_DESCRIPTION("EcoNet PCIe PHY driver"); +MODULE_LICENSE("GPL"); --=20 2.39.5