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Tue, 03 Mar 2026 03:56:30 -0800 (PST) Received: from nuvole ([144.202.86.13]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2adfb5dbac7sm227765195ad.37.2026.03.03.03.56.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2026 03:56:29 -0800 (PST) From: Pengyu Luo To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, White Lewis , Pengyu Luo Subject: [PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers Date: Tue, 3 Mar 2026 19:55:50 +0800 Message-ID: <20260303115550.9279-1-mitltlatltl@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: White Lewis The four byte_div_clk_src dividers (disp{0,1}_cc_mdss_byte{0,1}_div_clk_src) had CLK_SET_RATE_PARENT set. When the DSI driver calls clk_set_rate() on byte_intf_clk, the rate-change propagates through the divider up to the parent PLL (byte_clk_src), halving the byte clock rate. A simiar issue had been also encountered on SM8750. b8501febdc51 ("clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT= on byte intf parent"). Likewise, remove CLK_SET_RATE_PARENT from all four byte divider clocks so that clk_set_rate() on the divider adjusts only the divider ratio, leaving the parent PLL untouched. Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller") Signed-off-by: White Lewis [pengyu: reword] Signed-off-by: Pengyu Luo Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/dispcc-sc8280xp.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-s= c8280xp.c index 5903a759d..e91dfed0f 100644 --- a/drivers/clk/qcom/dispcc-sc8280xp.c +++ b/drivers/clk/qcom/dispcc-sc8280xp.c @@ -1160,7 +1160,6 @@ static struct clk_regmap_div disp0_cc_mdss_byte0_div_= clk_src =3D { &disp0_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; @@ -1175,7 +1174,6 @@ static struct clk_regmap_div disp1_cc_mdss_byte0_div_= clk_src =3D { &disp1_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; @@ -1190,7 +1188,6 @@ static struct clk_regmap_div disp0_cc_mdss_byte1_div_= clk_src =3D { &disp0_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; @@ -1205,7 +1202,6 @@ static struct clk_regmap_div disp1_cc_mdss_byte1_div_= clk_src =3D { &disp1_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; --=20 2.53.0