From nobody Thu Apr 2 18:47:40 2026 Received: from mail-lj1-f182.google.com (mail-lj1-f182.google.com [209.85.208.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F373389DE6 for ; Tue, 3 Mar 2026 08:43:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772527390; cv=none; b=KC8ex0siYeXwEwhq6PhSYv4K+bbPhjChiQx7H4YxoJj5ffBfzOUEpZDw3bEUzEBmNTzPyktUyyZsxT341DmPeuc04mJMQM/9KaUnM4q7NLCzbekgRb5O6GSG6O/DrMOHZigXXhnF6VktdwyAf62aCn6ZBq21SsBKcM6V7b4T7+I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772527390; c=relaxed/simple; bh=Wf0dy01upHUUUcUAKy8dIbGY/d5SUS2MJZNikXi5lc8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sfWTbaUsHMJ7ZlnhFRvdQmLP8tTVdD1VJYyz5L3gAoXHjw2czYmfpc6TaGlvzBH4N6UeabAQ2MlHFFVeQfrKndINJgpaj+FmWqHMeyE9kLRr6CAlqKl2k4cphcKRutvx/0GLoZxX5HsBKMraMDSONyVmWCUv+YNPUzct7cXAU8w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=VXqreeYf; arc=none smtp.client-ip=209.85.208.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VXqreeYf" Received: by mail-lj1-f182.google.com with SMTP id 38308e7fff4ca-38706b10b3bso98973921fa.1 for ; Tue, 03 Mar 2026 00:43:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772527383; x=1773132183; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f6KZvaBGZ/GU736NZrNzu56KlpQD0HwXdD7kW+frTF8=; b=VXqreeYfmVkxK6RVfJo8pIRiqyKmbFSsx0x15FoVyVQu5KLNtHrRhWxLzNHIOAYbO7 gEnhjWyTjseePWUFQ7dxmsUcxQ+q8Wa0E/lf0pm70NoA69ZB15nL4XVxfQFjsDHpLq8g d1Tcyu42lg1jXIN0PAKJ5VqM+37A2m2DUasYir5jRnFR4HZqbqCGlFpZ+Zyxk4MWtf1a FxdNikGRqD7gdWuHT/6mO2p2kaCqDN8gP5iOjxEUWakgckEj5xEsJCqf/y2Ntv/+9d+3 +FqINoHGzcBtknvnXwBqJB3ltruujL2g/D2d7AX907XNDPdi1jTpJ1Cwy+zw/FSrPIdL 1+IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772527383; x=1773132183; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=f6KZvaBGZ/GU736NZrNzu56KlpQD0HwXdD7kW+frTF8=; b=C7ud706JUTkqW1KMYQiZOT3qWNnqwUZ1hOSiUKW9KoUSGthxlLcNvz69dc71XjKt/5 DRXWD+4V5VmnrzZTXrJpgjzAWqQ+sR7UlO5yt7NV85U2domnYRY0Fg5DergnZdLoTG6C XESRGh0dd4h7O+9D4RKRtt4QFs1mV5ZB7TYjFIaggc38G98CuBX0fbcxQW8+yoYiFLlX vV5Ji9RdKEcoqeSv+NCXtRJ9Sg4WVEaUkuG7RWgKKiS4KW9yi5bKECQ3pG2EVESq4Svd 4VFtB7SqiWfa00RZlxOggmnuEailrVwx5/dV2Pbggvuwx9X4q1X9JVSKUxj/HNewCkPi ZfRQ== X-Gm-Message-State: AOJu0YyOj/FNb3LpVOF1wSQLQ2wxe38vYHCGXtpomFUnYb2Mviz/7B8J S8zXv6/1iyhhsIdRW20ZUL6jZpPCBnhGysUuxxVQNXmS6Fw9VLKFz7Jx X-Gm-Gg: ATEYQzyZ3uNG9UzKANhWqEeeAPgL+/MtG1qu9rLQZrNQoZLXk+PX9IpOAmZ/askz09u blcZNrnVZooIlc9vUFYAUCdQn2933+MAZHzR+m0z/PBjbejVtTQqFnbAOQhETMFQ7J6hJygTB4h l7yMlbwCboklNHcztm44mhiInGMbAyMNNLo+Z/I0f0LTa5GUYdjYZbCJEiRSNza2meYPsET9LQA hB2elw4TbBdbLlk1hKntnfIcP7xaxY3ILx8WNNkDU3YRDN0OS1ovbnCfEaz36vRaZ4Y6gRRqnbr vmSjav6Z2zjv+PUi44nC6+2bCdCI5HIAHlh0ObKZO0PFTGoLK1voZvpZ02U3sf7z/QfUB71NnkK 5PytE6rxpWo+w7VXwHvuPA8NJ7J7Wt/ZUvBn0z9BGQQXYR2Say1kNvMoQJNFrzo7dOlvg/ZHQUY BFrn/+V1Bx9ry3SGBVltUsMwk= X-Received: by 2002:a2e:94c4:0:b0:387:2df:f3ee with SMTP id 38308e7fff4ca-389ff34ee5amr91156871fa.33.1772527382459; Tue, 03 Mar 2026 00:43:02 -0800 (PST) Received: from xeon ([188.163.112.72]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-389f30227a9sm32599471fa.42.2026.03.03.00.43.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2026 00:43:01 -0800 (PST) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , David Airlie , Simona Vetter , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , Mauro Carvalho Chehab , Greg Kroah-Hartman , Hans Verkuil , Svyatoslav Ryhel Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v7 09/15] staging: media: tegra-video: tegra20: add support for second output of VI Date: Tue, 3 Mar 2026 10:42:32 +0200 Message-ID: <20260303084239.15007-10-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260303084239.15007-1-clamor95@gmail.com> References: <20260303084239.15007-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" VI in Tegra20/Tegra30 has 2 VI outputs with different set of supported formats. Convert output registers to macros for simpler work with both outputs since apart formats their layout matches. Tested-by: Luca Ceresoli # tegra20, parallel ca= mera Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/staging/media/tegra-video/tegra20.c | 83 ++++++++++++--------- 1 file changed, 47 insertions(+), 36 deletions(-) diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/= media/tegra-video/tegra20.c index b2e706fa727b..c8afc6f2adf2 100644 --- a/drivers/staging/media/tegra-video/tegra20.c +++ b/drivers/staging/media/tegra-video/tegra20.c @@ -28,13 +28,19 @@ #define TEGRA20_MIN_HEIGHT 32U #define TEGRA20_MAX_HEIGHT 8190U =20 +/* Tegra20/Tegra30 has 2 outputs in VI */ +enum tegra_vi_out { + TEGRA_VI_OUT_1 =3D 0, + TEGRA_VI_OUT_2 =3D 1, +}; + /* -----------------------------------------------------------------------= --- * Registers */ =20 -#define TEGRA_VI_CONT_SYNCPT_OUT_1 0x0060 -#define VI_CONT_SYNCPT_OUT_1_CONTINUOUS_SYNCPT BIT(8) -#define VI_CONT_SYNCPT_OUT_1_SYNCPT_IDX_SFT 0 +#define TEGRA_VI_CONT_SYNCPT_OUT(n) (0x0060 + (n) * 4) +#define VI_CONT_SYNCPT_OUT_CONTINUOUS_SYNCPT BIT(8) +#define VI_CONT_SYNCPT_OUT_SYNCPT_IDX_SFT 0 =20 #define TEGRA_VI_VI_INPUT_CONTROL 0x0088 #define VI_INPUT_FIELD_DETECT BIT(27) @@ -46,6 +52,7 @@ #define VI_INPUT_YUV_INPUT_FORMAT_YVYU (3 << VI_INPUT_YUV_INPUT_FOR= MAT_SFT) #define VI_INPUT_INPUT_FORMAT_SFT 2 /* bits [5:2] */ #define VI_INPUT_INPUT_FORMAT_YUV422 (0 << VI_INPUT_INPUT_FORMAT_SF= T) +#define VI_INPUT_INPUT_FORMAT_BAYER (2 << VI_INPUT_INPUT_FORMAT_SFT) #define VI_INPUT_VIP_INPUT_ENABLE BIT(1) =20 #define TEGRA_VI_VI_CORE_CONTROL 0x008c @@ -66,7 +73,7 @@ #define VI_VI_CORE_CONTROL_OUTPUT_TO_EPP_SFT 2 #define VI_VI_CORE_CONTROL_OUTPUT_TO_ISP_SFT 0 =20 -#define TEGRA_VI_VI_FIRST_OUTPUT_CONTROL 0x0090 +#define TEGRA_VI_VI_OUTPUT_CONTROL(n) (0x0090 + (n) * 4) #define VI_OUTPUT_FORMAT_EXT BIT(22) #define VI_OUTPUT_V_DIRECTION BIT(20) #define VI_OUTPUT_H_DIRECTION BIT(19) @@ -80,6 +87,8 @@ #define VI_OUTPUT_OUTPUT_FORMAT_SFT 0 #define VI_OUTPUT_OUTPUT_FORMAT_YUV422POST (3 << VI_OUTPUT_OUTPUT_FO= RMAT_SFT) #define VI_OUTPUT_OUTPUT_FORMAT_YUV420PLANAR (6 << VI_OUTPUT_OUTPUT_= FORMAT_SFT) +/* TEGRA_VI_OUT_2 supported formats */ +#define VI_OUTPUT_OUTPUT_FORMAT_VIP_BAYER_DIRECT (9 << VI_OUTPUT_OUT= PUT_FORMAT_SFT) =20 #define TEGRA_VI_VIP_H_ACTIVE 0x00a4 #define VI_VIP_H_ACTIVE_PERIOD_SFT 16 /* active pixels/line, must b= e even */ @@ -89,26 +98,26 @@ #define VI_VIP_V_ACTIVE_PERIOD_SFT 16 /* active lines */ #define VI_VIP_V_ACTIVE_START_SFT 0 =20 -#define TEGRA_VI_VB0_START_ADDRESS_FIRST 0x00c4 -#define TEGRA_VI_VB0_BASE_ADDRESS_FIRST 0x00c8 +#define TEGRA_VI_VB0_START_ADDRESS(n) (0x00c4 + (n) * 44) +#define TEGRA_VI_VB0_BASE_ADDRESS(n) (0x00c8 + (n) * 44) #define TEGRA_VI_VB0_START_ADDRESS_U 0x00cc #define TEGRA_VI_VB0_BASE_ADDRESS_U 0x00d0 #define TEGRA_VI_VB0_START_ADDRESS_V 0x00d4 #define TEGRA_VI_VB0_BASE_ADDRESS_V 0x00d8 =20 -#define TEGRA_VI_FIRST_OUTPUT_FRAME_SIZE 0x00e0 -#define VI_FIRST_OUTPUT_FRAME_HEIGHT_SFT 16 -#define VI_FIRST_OUTPUT_FRAME_WIDTH_SFT 0 +#define TEGRA_VI_OUTPUT_FRAME_SIZE(n) (0x00e0 + (n) * 24) +#define VI_OUTPUT_FRAME_HEIGHT_SFT 16 +#define VI_OUTPUT_FRAME_WIDTH_SFT 0 =20 -#define TEGRA_VI_VB0_COUNT_FIRST 0x00e4 +#define TEGRA_VI_VB0_COUNT(n) (0x00e4 + (n) * 24) =20 -#define TEGRA_VI_VB0_SIZE_FIRST 0x00e8 -#define VI_VB0_SIZE_FIRST_V_SFT 16 -#define VI_VB0_SIZE_FIRST_H_SFT 0 +#define TEGRA_VI_VB0_SIZE(n) (0x00e8 + (n) * 24) +#define VI_VB0_SIZE_V_SFT 16 +#define VI_VB0_SIZE_H_SFT 0 =20 -#define TEGRA_VI_VB0_BUFFER_STRIDE_FIRST 0x00ec -#define VI_VB0_BUFFER_STRIDE_FIRST_CHROMA_SFT 30 -#define VI_VB0_BUFFER_STRIDE_FIRST_LUMA_SFT 0 +#define TEGRA_VI_VB0_BUFFER_STRIDE(n) (0x00ec + (n) * 24) +#define VI_VB0_BUFFER_STRIDE_CHROMA_SFT 30 +#define VI_VB0_BUFFER_STRIDE_LUMA_SFT 0 =20 #define TEGRA_VI_H_LPF_CONTROL 0x0108 #define VI_H_LPF_CONTROL_CHROMA_SFT 16 @@ -136,7 +145,7 @@ #define VI_CAMERA_CONTROL_TEST_MODE BIT(1) #define VI_CAMERA_CONTROL_VIP_ENABLE BIT(0) =20 -#define TEGRA_VI_VI_ENABLE 0x01a4 +#define TEGRA_VI_VI_ENABLE(n) (0x01a4 + (n) * 4) #define VI_VI_ENABLE_SW_FLOW_CONTROL_OUT1 BIT(1) #define VI_VI_ENABLE_FIRST_OUTPUT_TO_MEM_DISABLE BIT(0) =20 @@ -366,8 +375,8 @@ static void tegra20_channel_vi_buffer_setup(struct tegr= a_vi_channel *chan, case V4L2_PIX_FMT_VYUY: case V4L2_PIX_FMT_YUYV: case V4L2_PIX_FMT_YVYU: - tegra20_vi_write(chan, TEGRA_VI_VB0_BASE_ADDRESS_FIRST, base); - tegra20_vi_write(chan, TEGRA_VI_VB0_START_ADDRESS_FIRST, base + chan->st= art_offset); + tegra20_vi_write(chan, TEGRA_VI_VB0_BASE_ADDRESS(TEGRA_VI_OUT_1), base); + tegra20_vi_write(chan, TEGRA_VI_VB0_START_ADDRESS(TEGRA_VI_OUT_1), base = + chan->start_offset); break; } } @@ -455,6 +464,7 @@ static void tegra20_camera_capture_setup(struct tegra_v= i_channel *chan) int stride_l =3D chan->format.bytesperline; int stride_c =3D (output_fourcc =3D=3D V4L2_PIX_FMT_YUV420 || output_fourcc =3D=3D V4L2_PIX_FMT_YVU420) ? 1 : 0; + enum tegra_vi_out output_channel =3D TEGRA_VI_OUT_1; int main_output_format; int yuv_output_format; =20 @@ -472,33 +482,33 @@ static void tegra20_camera_capture_setup(struct tegra= _vi_channel *chan) /* Set up raise-on-edge, so we get an interrupt on end of frame. */ tegra20_vi_write(chan, TEGRA_VI_VI_RAISE, VI_VI_RAISE_ON_EDGE); =20 - tegra20_vi_write(chan, TEGRA_VI_VI_FIRST_OUTPUT_CONTROL, + tegra20_vi_write(chan, TEGRA_VI_VI_OUTPUT_CONTROL(output_channel), (chan->vflip ? VI_OUTPUT_V_DIRECTION : 0) | (chan->hflip ? VI_OUTPUT_H_DIRECTION : 0) | yuv_output_format << VI_OUTPUT_YUV_OUTPUT_FORMAT_SFT | main_output_format << VI_OUTPUT_OUTPUT_FORMAT_SFT); =20 /* Set up frame size */ - tegra20_vi_write(chan, TEGRA_VI_FIRST_OUTPUT_FRAME_SIZE, - height << VI_FIRST_OUTPUT_FRAME_HEIGHT_SFT | - width << VI_FIRST_OUTPUT_FRAME_WIDTH_SFT); + tegra20_vi_write(chan, TEGRA_VI_OUTPUT_FRAME_SIZE(output_channel), + height << VI_OUTPUT_FRAME_HEIGHT_SFT | + width << VI_OUTPUT_FRAME_WIDTH_SFT); =20 /* First output memory enabled */ - tegra20_vi_write(chan, TEGRA_VI_VI_ENABLE, 0); + tegra20_vi_write(chan, TEGRA_VI_VI_ENABLE(output_channel), 0); =20 /* Set the number of frames in the buffer */ - tegra20_vi_write(chan, TEGRA_VI_VB0_COUNT_FIRST, 1); + tegra20_vi_write(chan, TEGRA_VI_VB0_COUNT(output_channel), 1); =20 /* Set up buffer frame size */ - tegra20_vi_write(chan, TEGRA_VI_VB0_SIZE_FIRST, - height << VI_VB0_SIZE_FIRST_V_SFT | - width << VI_VB0_SIZE_FIRST_H_SFT); + tegra20_vi_write(chan, TEGRA_VI_VB0_SIZE(output_channel), + height << VI_VB0_SIZE_V_SFT | + width << VI_VB0_SIZE_H_SFT); =20 - tegra20_vi_write(chan, TEGRA_VI_VB0_BUFFER_STRIDE_FIRST, - stride_l << VI_VB0_BUFFER_STRIDE_FIRST_LUMA_SFT | - stride_c << VI_VB0_BUFFER_STRIDE_FIRST_CHROMA_SFT); + tegra20_vi_write(chan, TEGRA_VI_VB0_BUFFER_STRIDE(output_channel), + stride_l << VI_VB0_BUFFER_STRIDE_LUMA_SFT | + stride_c << VI_VB0_BUFFER_STRIDE_CHROMA_SFT); =20 - tegra20_vi_write(chan, TEGRA_VI_VI_ENABLE, 0); + tegra20_vi_write(chan, TEGRA_VI_VI_ENABLE(output_channel), 0); } =20 static int tegra20_vi_start_streaming(struct vb2_queue *vq, u32 count) @@ -587,7 +597,7 @@ const struct tegra_vi_soc tegra20_vi_soc =3D { .nformats =3D ARRAY_SIZE(tegra20_video_formats), .default_video_format =3D &tegra20_video_formats[0], .ops =3D &tegra20_vi_ops, - .vi_max_channels =3D 1, /* parallel input (VIP) */ + .vi_max_channels =3D 2, /* TEGRA_VI_OUT_1 and TEGRA_VI_OUT_2 */ .vi_max_clk_hz =3D 150000000, .has_h_v_flip =3D true, }; @@ -607,6 +617,7 @@ static int tegra20_vip_start_streaming(struct tegra_vip= _channel *vip_chan) struct tegra_vi_channel *vi_chan =3D v4l2_get_subdev_hostdata(&vip_chan->= subdev); int width =3D vi_chan->format.width; int height =3D vi_chan->format.height; + enum tegra_vi_out output_channel =3D TEGRA_VI_OUT_1; =20 unsigned int main_input_format; unsigned int yuv_input_format; @@ -637,10 +648,10 @@ static int tegra20_vip_start_streaming(struct tegra_v= ip_channel *vip_chan) GENMASK(9, 2) << VI_DATA_INPUT_SFT); tegra20_vi_write(vi_chan, TEGRA_VI_PIN_INVERSION, 0); =20 - tegra20_vi_write(vi_chan, TEGRA_VI_CONT_SYNCPT_OUT_1, - VI_CONT_SYNCPT_OUT_1_CONTINUOUS_SYNCPT | + tegra20_vi_write(vi_chan, TEGRA_VI_CONT_SYNCPT_OUT(output_channel), + VI_CONT_SYNCPT_OUT_CONTINUOUS_SYNCPT | host1x_syncpt_id(vi_chan->mw_ack_sp[0]) - << VI_CONT_SYNCPT_OUT_1_SYNCPT_IDX_SFT); + << VI_CONT_SYNCPT_OUT_SYNCPT_IDX_SFT); =20 tegra20_vi_write(vi_chan, TEGRA_VI_CAMERA_CONTROL, VI_CAMERA_CONTROL_STOP= _CAPTURE); =20 --=20 2.51.0