From nobody Fri Apr 3 04:40:02 2026 Received: from out-171.mta0.migadu.com (out-171.mta0.migadu.com [91.218.175.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A7902F12AF for ; Tue, 3 Mar 2026 03:49:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772509782; cv=none; b=pfTAnEdGiAani0uHBi//2mSppnIqd3inZY5rlRHFmr/wwHLtcbTq8i1Mw0Azi38BP+N4E+RO1w2G7HnuwSREl9ZiKudZEImM3E1P22zznM1qywi6LsVhiJnLhTU/UbZdgqlhGymoX2O8PTZvpuhAWfMTOFlumjEEe1LXeeauBm4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772509782; c=relaxed/simple; bh=6XdLF9JTJRWCKGHMMMV7qKvxDe5yc3EsPTrCvvgF8cc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HrmlfdMswTEfl6loiyJBfVx9il5SE75fgQ1bBf5SPRERt0Zc4P2PfX6tbNHyrGBpNNLD6IUwurS1VHghnK+ARyYCR49OUk44JnslsYrcW1l585TRFhDWvp5TtPcrFTOkvt1LkW9bQQDcTa6FYKB0kV7KNugqa5M1UHhuzfATqXw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=Ka6Fp41m; arc=none smtp.client-ip=91.218.175.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="Ka6Fp41m" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1772509779; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0i1+OkKQaK2cithGqyj/94PMbbQBAN7UMU6yAQl/SDo=; b=Ka6Fp41mwfpSRUTGZDriy6FIzzgbilDRsL+YJh7jUOfVID9K0vj0xG/kjbzqJYt7LfYzNL 3FpNSkIHRUrZkdoNLZ3AgXrjzHeeV8vqwpc0FSjpgc+x1HpP6BXQ2wES2VVUhQ8LgRKpKk zPJA4muRXNRX9swGyP0fuY214IrXZ41EyDm/Cr3dWq+8b5qOQ8CmRfw79q3ZPp3Jucb2HV pqoMSw6em6jCz+l2eWdufA4Fx92TO0zT9Gdp6xpjNO0uqM9Tb0dY3cpquoU9eW0w1Sbf5o NEGPKsv1RrzzLOTqQ0SVo9qaSStFgneYoDQO0hRdvQ/gTIWWM++Eb9HqtsF6mg== From: Val Packett To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adam Skladowski Cc: Val Packett , linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v3 5/6] arm64: dts: qcom: sm6115: Add missing MDSS core reset Date: Tue, 3 Mar 2026 00:41:24 -0300 Message-ID: <20260303034847.13870-6-val@packett.cool> In-Reply-To: <20260303034847.13870-1-val@packett.cool> References: <20260303034847.13870-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" To make sure the display subsystem starts in a predictable state, we need to reset it. Otherwise, unpredictable issues can happen, e.g. on the motorola-guamp smartphone DSI would not transmit anything. Wire up the reset to fix. Fixes: 705e50427d81 ("arm64: dts: qcom: sm6115: Add mdss/dpu node") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Val Packett Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qco= m/sm6115.dtsi index e9336adbc391..3a9a1ad8d581 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1864,6 +1864,8 @@ mdss: display-subsystem@5e00000 { <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; =20 + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + interrupts =3D ; interrupt-controller; #interrupt-cells =3D <1>; --=20 2.52.0