From nobody Fri Apr 3 04:58:55 2026 Received: from out-178.mta0.migadu.com (out-178.mta0.migadu.com [91.218.175.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 351062737E3; Tue, 3 Mar 2026 03:49:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772509777; cv=none; b=ed8zX8gRfC2lVR4u1jvD9sQPjaDLtZhCxa72xoeGtAox2miAeSjM1Xb2nZtaTSnV8S4AdYIntN3zf3cyVq5Mm2WP3odv6KnjxMGIdH5RVOBMN6QzJ+Tr/DOVYfH46v15nMbV3grUCaf7P2umSz2OIVevyieMD5sQhUheKHyh9cU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772509777; c=relaxed/simple; bh=758NQLV26iLjFlPnugp6UymqkgFeKb0vZm5scqECkO0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mULGY9BoEudxlCQtXtL0Ls8YfUUSNmOMiNBBRsKWEgfmVDaSly0liDEPtim5xk2rjzUzrnXIMt9dM7xOvqZ7MgH/eLPBlJs48MVuH2AhugBLOm5jar04jD+Q+IiTZcjplpqDs3YNxNCNh4uJPDIwg3WzAkaZnstHnl4BBeDxFso= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=OsRFolDC; arc=none smtp.client-ip=91.218.175.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="OsRFolDC" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1772509774; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=F6eVMQMkXuZNpLHxQKItqT1Sc2r+WN+cU+XtpyRC/H8=; b=OsRFolDCu9IEcD37vkP3+U6UbAtmNWxC7FaAfAxT5vkxiIhhxognyTc+uTxP79D24QGgHl hFv6euDUgS+Yjnbs8nyaVIjjWJZ+YspFKm+VTl+Vx3cTHRd/ow+wMLNqlwHVNQV/6HO+iZ kkg4dPXXW0L3VOyQTZBF2rfVtcSLVSepjqguvXWd36h2AM4XkaooiPxXNVX9ISWFUMD4nd WY1qTLHXyTNUH06SYQ/iRf7F8XFq92zjTkisftTAwRly0yBz44nrZ3Jl1fu2B2lgHJQDw1 UDIHdwiCsOdXC2YTu5m7enJBKF/GIeu6BYqICR5jpW5dlme6JliJJe7B9OY1bA== From: Val Packett To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Adam Skladowski Cc: Val Packett , linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v3 4/6] clk: qcom: dispcc-sm6125: Add missing MDSS resets Date: Tue, 3 Mar 2026 00:41:23 -0300 Message-ID: <20260303034847.13870-5-val@packett.cool> In-Reply-To: <20260303034847.13870-1-val@packett.cool> References: <20260303034847.13870-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The MDSS resets were left undescribed. Add them to allow resetting the display subsystem, which is necessary to avoid issues caused by state left over from the bootloader on various platforms. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Val Packett Reviewed-by: Krzysztof Kozlowski --- drivers/clk/qcom/dispcc-sm6125.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/qcom/dispcc-sm6125.c b/drivers/clk/qcom/dispcc-sm6= 125.c index 851d38a487d3..2c67abcfef12 100644 --- a/drivers/clk/qcom/dispcc-sm6125.c +++ b/drivers/clk/qcom/dispcc-sm6125.c @@ -17,6 +17,7 @@ #include "clk-regmap.h" #include "common.h" #include "gdsc.h" +#include "reset.h" =20 enum { P_BI_TCXO, @@ -607,6 +608,10 @@ static struct clk_branch disp_cc_xo_clk =3D { }, }; =20 +static const struct qcom_reset_map disp_cc_sm6125_resets[] =3D { + [DISP_CC_MDSS_CORE_BCR] =3D { 0x2000 }, +}; + static struct gdsc mdss_gdsc =3D { .gdscr =3D 0x3000, .pd =3D { @@ -663,6 +668,8 @@ static const struct qcom_cc_desc disp_cc_sm6125_desc = =3D { .config =3D &disp_cc_sm6125_regmap_config, .clks =3D disp_cc_sm6125_clocks, .num_clks =3D ARRAY_SIZE(disp_cc_sm6125_clocks), + .resets =3D disp_cc_sm6125_resets, + .num_resets =3D ARRAY_SIZE(disp_cc_sm6125_resets), .gdscs =3D disp_cc_sm6125_gdscs, .num_gdscs =3D ARRAY_SIZE(disp_cc_sm6125_gdscs), }; --=20 2.52.0