From nobody Thu Apr 9 19:21:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C101F384241; Tue, 3 Mar 2026 19:52:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772567550; cv=none; b=K07le5b/m6m2wt8Qw23CxwN5IUNBXnp23g0N8b/jHoqGXI8gkRx/13AJvHanp45CRsbVeBSVoLQThAKMji0PCGzmSi6XEA6DVud/VY1MTkXppohmVsSsJDdjv6kFGG3TmcgQW8HHzMblnJDL0Aaq0u0/gElDDOTJ9OBLYc9IG2U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772567550; c=relaxed/simple; bh=5YFZUcbTUgRm5DTNoNPFw3sTzCo45qe21WCODDGKvS0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pkbUUcuykG9LEsZ7CxxsH6Y9f4sqIsIrs0LOxQUnjz5nq/78Z9NvWwFtu9MaSAkjesBSr8c5/Wvd/Dw9tfN55EUxSaSxGf/D2B2e5WhhW1JGLeobe+eTBPoMn+8BjWZFixFiXPS3f7dhvRTPgpvIrHYy+xkN/DAo3Y50DwHtEXQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=H50g3wSB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="H50g3wSB" Received: by smtp.kernel.org (Postfix) with ESMTPS id A05BEC2BCB1; Tue, 3 Mar 2026 19:52:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772567550; bh=5YFZUcbTUgRm5DTNoNPFw3sTzCo45qe21WCODDGKvS0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=H50g3wSBgM1LjRrLe+T/UIcSXH7xANuYVo2Vfs8LxGm/JXP9ffECm5DhBktBs0xD1 +9deEUV9qwxElksYzk4a8zemc1M2rA0R0o8p4077bWJOsDh3edbqDTl6s5DW4ryTIL 8iev0NOWYU6temBQ0eA16lR2JE0v7bPPHSvZ0Z1M7bVA5xDe+to/MaaL43Dl6qL1i8 z1TW0Z8heTx9DUGJdlwk5F9shjw3KACGgJ6gxWMp7bvepR5C7n/0xvtST6ergB0htd 5p0kdP2caqTk8s4Q7tDvhIvFXow3+qO7F0sA+HJZvPgsnPNqvWx7RV1NHc8mM6tFB4 LW/j0PK7OjpHA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90A01EDEBEF; Tue, 3 Mar 2026 19:52:30 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Tue, 03 Mar 2026 20:52:29 +0100 Subject: [PATCH v3 3/4] arm64: dts: rockchip: Use reference PCIe clock generator for BPI-R2-Pro Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-3-af5a5207b0a1@ixit.cz> References: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-0-af5a5207b0a1@ixit.cz> In-Reply-To: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-0-af5a5207b0a1@ixit.cz> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Frank Wunderlich Cc: Martin Filla , Charalampos Mitrodimas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3580; i=david@ixit.cz; h=from:subject:message-id; bh=ErDena6uQvd0JzFK1uxs+tYPpVApCktOwvCHIp0f9fM=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBppzv8NGkEODwhzAbXCqppzfwNaLpq0XZL0mqZd I/ZhEoi+d6JAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaac7/AAKCRBgAj/E00kg cv5LD/4qAWipALq+N7TdC2t3WCrg3REaLfx5ZbkwdflIivDNk0hv0MBM5PSkOXmM1hFF6d83DCG xuJ9ICz5bqUT9qOulKIzdjAWqBXO6GNT5x/eAIdWujRmITN7ik4Mj8x8KJW4go1yYecuYtfMGOG SHUyU5sWesQsJoM/JU/ENp2ov/fzE8/2bKjVZdmDBqrjJzfMUQFawjTwiE5+rB3Zs8fhJX2bc6D HzB2i6p77zRbU9iPjxCvaH39YB/X6GZbXMPIVUGvoqIiZaC55fmNCpMjJOJRiZaseuKaVwSqZzl /tfIvXpXSOenFcfmNeCZhEvQUYFzxp5t1BWag7/6kz9RqufdKEjKHaHwb3eDjqJSuBF1SbB9J+u VN9RbhHNAZ6VOvXmKwB9PkO6rM5a8Aom4wnSqA6/GrdNoT9AwhEIPjEcgm6cyXL9YkzVfMff+6x OhqL1rDqrJxl1qm/eU4l2UkfO03bEgL5DzEG7PxEFX8Dja1T5wmMtpFW9spl2xu5nnLyUC2mUE2 2b0gMPZ/vdYsym0O7jfFQtIx2A2HHsGNVNwig2t+tl66iBL23ZQys2c5gQI/N4PvOI5C3AJty8/ R8WfdceqAaweEoIpkF1kKynWnrU1dxhJ7I6CpJGyGy8mOES99XmY9ImDREXcKRKbMXdoJtG444C akzUKBzT/d/NbFg== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Describe properly PCIe clock, which allows us correct the toplogy (removing the vcc3v3-{minipcie,ngff} dependency on pi6c as supply) and adding the clock dependency in the PCIe nodes. Suggested-by: Heiko Stuebner Tested-by: Martin Filla Signed-off-by: David Heidelberg --- arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 47 +++++++++++++++---= ---- 1 file changed, 33 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm6= 4/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index d02b82c5f979a..3cdea9456a28c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -120,18 +120,13 @@ pcie_refclk_gen: pcie-refclk-gen-clock { clock-frequency =3D <100000000>; }; =20 - vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { - compatible =3D "regulator-fixed"; - regulator-name =3D "vcc3v3_pcie"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - enable-active-high; - gpios =3D <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - startup-delay-us =3D <200000>; - vin-supply =3D <&vcc5v0_sys>; + pcie_refclk: pcie-refclk-clock { + compatible =3D "gpio-gate-clock"; + clocks =3D <&pcie_refclk_gen>; + #clock-cells =3D <0>; + enable-gpios =3D <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; }; =20 - /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ vcc3v3_minipcie: regulator-vcc3v3-minipcie { compatible =3D "regulator-fixed"; regulator-name =3D "vcc3v3_minipcie"; @@ -142,10 +137,9 @@ vcc3v3_minipcie: regulator-vcc3v3-minipcie { pinctrl-names =3D "default"; pinctrl-0 =3D <&minipcie_enable_h>; startup-delay-us =3D <50000>; - vin-supply =3D <&vcc3v3_pi6c_05>; + vin-supply =3D <&vcc3v3_sys>; }; =20 - /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ vcc3v3_ngff: regulator-vcc3v3-ngff { compatible =3D "regulator-fixed"; regulator-name =3D "vcc3v3_ngff"; @@ -156,7 +150,7 @@ vcc3v3_ngff: regulator-vcc3v3-ngff { pinctrl-names =3D "default"; pinctrl-0 =3D <&ngffpcie_enable_h>; startup-delay-us =3D <50000>; - vin-supply =3D <&vcc3v3_pi6c_05>; + vin-supply =3D <&vcc3v3_sys>; }; =20 vcc5v0_usb: regulator-vcc5v0-usb { @@ -586,12 +580,24 @@ rgmii_phy1: ethernet-phy@0 { =20 &pcie30phy { data-lanes =3D <1 2>; - phy-supply =3D <&vcc3v3_pi6c_05>; + status =3D "okay"; }; =20 &pcie3x1 { /* M.2 slot */ + /* + * The board has a gpio-controlled "pcie_refclk" generator, + * so add it to the list of clocks. + */ + clocks =3D <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, + <&cru CLK_PCIE30X1_AUX_NDFT>, + <&cru CLK_PCIE30X1_PIPE_DFT>, + <&pcie_refclk>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "pipe", "ref"; num-lanes =3D <1>; pinctrl-names =3D "default"; pinctrl-0 =3D <&ngffpcie_reset_h>; @@ -602,6 +608,19 @@ &pcie3x1 { =20 &pcie3x2 { /* mPCIe slot */ + /* + * The board has a gpio-controlled "pcie_refclk" generator, + * so add it to the list of clocks. + */ + clocks =3D <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&cru CLK_PCIE30X2_PIPE_DFT>, + <&pcie_refclk>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "pipe", "ref"; + num-lanes =3D <1>; pinctrl-names =3D "default"; pinctrl-0 =3D <&minipcie_reset_h>; --=20 2.53.0