From nobody Thu Apr 9 18:01:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B956435F199; Tue, 3 Mar 2026 19:52:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772567550; cv=none; b=A/QgD7FlGf6QFiIlKbhgBJhqlJLGAzCRz8CDk/k/d401DWTw5BLbfqT+APWrOoMWGKjIT8nZNshJsDyjxBshcXvkdvHMGFmnja/f4UizjmUE1zYB7A+Vhk1JinodLuzYQB4wWp2SUTuT3YHTTn+dKi31GIqajqsyUr9p/+Xdid4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772567550; c=relaxed/simple; bh=oHis0oNWG8f5L9e3rDYPqCCkd9XkQEAtq1esFIHDMUU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ibhjdRVr/J39Ic/7v9cnAeH7RDRKDRXdQtYDh7J821DcHfT/qOL1t+WiH2C28JJ8XsInYU+ZLGoz/GbkHN9l0s2HLKDWKwGCrWVFSnyf8mID907IoAw5J2F+cP9Sd9rcpfIVUGGj2y9QW1LsCBQBq6XhY4HuFLyMcUv9c1P9DAA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iJfSUWV/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iJfSUWV/" Received: by smtp.kernel.org (Postfix) with ESMTPS id 76775C2BC87; Tue, 3 Mar 2026 19:52:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772567550; bh=oHis0oNWG8f5L9e3rDYPqCCkd9XkQEAtq1esFIHDMUU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=iJfSUWV/dv7huAy8kvxJJz4EZlGAgXuzNtuAs9i+2K3ynBZE5LdVQ7+MZnhAxtY5N Y+zdFUFvhULsfAzYhuHRMhiTPnPpc3qyCj38opcCj/RAgYdZhHkhjiNs8UCt8vyUDB 9jaGh020BSVGZ7ExGLMlwhAs/6lJG9ZBKgCg5CxXXlfHdPeSw0EYoz208vtsEQpB/w cEMo02vUbrSaAo0ALQulQZAP4nbySIVpUKZzlYUPNW8a0UQ8PPP7zyNyHaswHMM/Rv H8eyRiEUf55vtTPKOPdevrW81f/yVrflplxoWEHwWsy7APZAYJBY5n0g2W42c1oHCn fvDuEXdnZRx2Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58DFDEDEBED; Tue, 3 Mar 2026 19:52:30 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Tue, 03 Mar 2026 20:52:27 +0100 Subject: [PATCH v3 1/4] arm64: dts: rockchip: assign pipe clock to rk3568 PCIe lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-1-af5a5207b0a1@ixit.cz> References: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-0-af5a5207b0a1@ixit.cz> In-Reply-To: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-0-af5a5207b0a1@ixit.cz> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Frank Wunderlich Cc: Martin Filla , Charalampos Mitrodimas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1684; i=david@ixit.cz; h=from:subject:message-id; bh=kBL8DfIbMEZId/mS9aT/ZMrXznRqWhpDEYin4PccSE4=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBppzv7Wv3xTTAHuxiN/ZqvtT/LDbQ8kHANgL2gf 2gYzFH1ituJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaac7+wAKCRBgAj/E00kg cg18EAC4Hcmjx5yPY78MeXIWdgDG5ds2l3Pxnhjtmy7lALsL4hCfW4aX9rahnv14dF8xPR2D0pP z2m+aVGb7e4fwBBn5TCtS6+TxuZSFbyw9/TTI3te5JcoGtrs8GSAQOl4WtWVRNfOqOVrRqUJk/x feoSjS/zLrcpaBAr5dtw24bdps8H1k+5g/kLV0z9PZd8XHTq1YZwo2Ms5uzYRAVR9qrNEH8TC2J /mJQWinn76+YtotO9QUukpg45y2UzvUtxnA2EoyMQ85SLSiFRYKgmFZDzZZHXj/GIBteQh30MS8 1kXUuGMWpx23ADPgCOESGsEv+VCQ+6plKjSKpMoQhUkpz0zdsH5eDKjw4VX3Ex/24+l42sVDRvc GNgLYWRkJvt6Z2p2Vt+ijJqglH0VZQrkv6MkTrpw7fTo8CgdyRVo0h5zJPPtHoc5I4GB2nUFef/ gvtHFPRERqnXJEhz3P7xoHhgUtZO4H4ALZi+/GbjQb9mAOER2onws7ZtLyveHBR6Ww/jrre7ALG cgMP6BsOTDaYOA2v5gX+gX4JYv/0fVBfbAZT1qLcLEfbFjwh/irNWPlhwQRyri4IaqNKpFjobi2 LwMBnOkWQKQzfUrZ9T0iJEv4zyntNxY5NMPMKg+chORgsV7j51PJIJ/5eswvCyU42dngK5iyaQk FM32cyvEh/DnvrQ== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg These clocks are used by PCIe lanes, but we're missing from the definition. Suggested-by: Charalampos Mitrodimas Signed-off-by: David Heidelberg --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts= /rockchip/rk3568.dtsi index 658097ed69714..3bc653f027f1f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -155,9 +155,11 @@ pcie3x1: pcie@fe270000 { bus-range =3D <0x10 0x1f>; clocks =3D <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, - <&cru CLK_PCIE30X1_AUX_NDFT>; + <&cru CLK_PCIE30X1_AUX_NDFT>, + <&cru CLK_PCIE30X1_PIPE_DFT>; clock-names =3D "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; + "aclk_dbi", "pclk", "aux", + "pipe"; device_type =3D "pci"; interrupts =3D , , @@ -208,9 +210,11 @@ pcie3x2: pcie@fe280000 { bus-range =3D <0x20 0x2f>; clocks =3D <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, - <&cru CLK_PCIE30X2_AUX_NDFT>; + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&cru CLK_PCIE30X2_PIPE_DFT>; clock-names =3D "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; + "aclk_dbi", "pclk", "aux", + "pipe"; device_type =3D "pci"; interrupts =3D , , --=20 2.53.0 From nobody Thu Apr 9 18:01:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1C252FF164; Tue, 3 Mar 2026 19:52:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772567550; cv=none; b=rkWmFw104jv5iEz5ks1CYCVAHvVFad3xG9f4rbZEOHbHsJGkDJtwl7b4Dt59wcDhYujsuo2I9WEiMU7iBd7fNVEO+r0WS08hacaiAllllD2dTz85SZnMR2FCKBimy5/CidQryduKcukZRwL+YTmcbgbBVBA0gWwtjjeF7c4vg/0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Tue, 3 Mar 2026 19:52:30 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Tue, 03 Mar 2026 20:52:28 +0100 Subject: [PATCH v3 2/4] arm64: dts: rockchip: Introduce the reference PCIe clk generator for BPI-R2-Pro Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-2-af5a5207b0a1@ixit.cz> References: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-0-af5a5207b0a1@ixit.cz> In-Reply-To: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-0-af5a5207b0a1@ixit.cz> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Frank Wunderlich Cc: Martin Filla , Charalampos Mitrodimas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; 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fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg This clocks provides for both PCIe lanes. In following commit will be utilized by PCIe clock. Most likely PI6CG33602C or some variant of it. Suggested-by: Heiko Stuebner Tested-by: Martin Filla Signed-off-by: David Heidelberg --- arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm6= 4/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index 4d3ebe50b90ba..d02b82c5f979a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -114,6 +114,12 @@ pcie30_avdd1v8: regulator-pcie30-avdd1v8 { }; =20 /* pi6c pcie clock generator feeds both ports */ + pcie_refclk_gen: pcie-refclk-gen-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100000000>; + }; + vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { compatible =3D "regulator-fixed"; regulator-name =3D "vcc3v3_pcie"; --=20 2.53.0 From nobody Thu Apr 9 18:01:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C101F384241; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-3-af5a5207b0a1@ixit.cz> References: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-0-af5a5207b0a1@ixit.cz> In-Reply-To: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-0-af5a5207b0a1@ixit.cz> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Frank Wunderlich Cc: Martin Filla , Charalampos Mitrodimas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3580; i=david@ixit.cz; h=from:subject:message-id; bh=ErDena6uQvd0JzFK1uxs+tYPpVApCktOwvCHIp0f9fM=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBppzv8NGkEODwhzAbXCqppzfwNaLpq0XZL0mqZd I/ZhEoi+d6JAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaac7/AAKCRBgAj/E00kg cv5LD/4qAWipALq+N7TdC2t3WCrg3REaLfx5ZbkwdflIivDNk0hv0MBM5PSkOXmM1hFF6d83DCG xuJ9ICz5bqUT9qOulKIzdjAWqBXO6GNT5x/eAIdWujRmITN7ik4Mj8x8KJW4go1yYecuYtfMGOG SHUyU5sWesQsJoM/JU/ENp2ov/fzE8/2bKjVZdmDBqrjJzfMUQFawjTwiE5+rB3Zs8fhJX2bc6D HzB2i6p77zRbU9iPjxCvaH39YB/X6GZbXMPIVUGvoqIiZaC55fmNCpMjJOJRiZaseuKaVwSqZzl /tfIvXpXSOenFcfmNeCZhEvQUYFzxp5t1BWag7/6kz9RqufdKEjKHaHwb3eDjqJSuBF1SbB9J+u VN9RbhHNAZ6VOvXmKwB9PkO6rM5a8Aom4wnSqA6/GrdNoT9AwhEIPjEcgm6cyXL9YkzVfMff+6x OhqL1rDqrJxl1qm/eU4l2UkfO03bEgL5DzEG7PxEFX8Dja1T5wmMtpFW9spl2xu5nnLyUC2mUE2 2b0gMPZ/vdYsym0O7jfFQtIx2A2HHsGNVNwig2t+tl66iBL23ZQys2c5gQI/N4PvOI5C3AJty8/ R8WfdceqAaweEoIpkF1kKynWnrU1dxhJ7I6CpJGyGy8mOES99XmY9ImDREXcKRKbMXdoJtG444C akzUKBzT/d/NbFg== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Describe properly PCIe clock, which allows us correct the toplogy (removing the vcc3v3-{minipcie,ngff} dependency on pi6c as supply) and adding the clock dependency in the PCIe nodes. Suggested-by: Heiko Stuebner Tested-by: Martin Filla Signed-off-by: David Heidelberg --- arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 47 +++++++++++++++---= ---- 1 file changed, 33 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm6= 4/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index d02b82c5f979a..3cdea9456a28c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -120,18 +120,13 @@ pcie_refclk_gen: pcie-refclk-gen-clock { clock-frequency =3D <100000000>; }; =20 - vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { - compatible =3D "regulator-fixed"; - regulator-name =3D "vcc3v3_pcie"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - enable-active-high; - gpios =3D <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - startup-delay-us =3D <200000>; - vin-supply =3D <&vcc5v0_sys>; + pcie_refclk: pcie-refclk-clock { + compatible =3D "gpio-gate-clock"; + clocks =3D <&pcie_refclk_gen>; + #clock-cells =3D <0>; + enable-gpios =3D <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; }; =20 - /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ vcc3v3_minipcie: regulator-vcc3v3-minipcie { compatible =3D "regulator-fixed"; regulator-name =3D "vcc3v3_minipcie"; @@ -142,10 +137,9 @@ vcc3v3_minipcie: regulator-vcc3v3-minipcie { pinctrl-names =3D "default"; pinctrl-0 =3D <&minipcie_enable_h>; startup-delay-us =3D <50000>; - vin-supply =3D <&vcc3v3_pi6c_05>; + vin-supply =3D <&vcc3v3_sys>; }; =20 - /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ vcc3v3_ngff: regulator-vcc3v3-ngff { compatible =3D "regulator-fixed"; regulator-name =3D "vcc3v3_ngff"; @@ -156,7 +150,7 @@ vcc3v3_ngff: regulator-vcc3v3-ngff { pinctrl-names =3D "default"; pinctrl-0 =3D <&ngffpcie_enable_h>; startup-delay-us =3D <50000>; - vin-supply =3D <&vcc3v3_pi6c_05>; + vin-supply =3D <&vcc3v3_sys>; }; =20 vcc5v0_usb: regulator-vcc5v0-usb { @@ -586,12 +580,24 @@ rgmii_phy1: ethernet-phy@0 { =20 &pcie30phy { data-lanes =3D <1 2>; - phy-supply =3D <&vcc3v3_pi6c_05>; + status =3D "okay"; }; =20 &pcie3x1 { /* M.2 slot */ + /* + * The board has a gpio-controlled "pcie_refclk" generator, + * so add it to the list of clocks. + */ + clocks =3D <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, + <&cru CLK_PCIE30X1_AUX_NDFT>, + <&cru CLK_PCIE30X1_PIPE_DFT>, + <&pcie_refclk>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "pipe", "ref"; num-lanes =3D <1>; pinctrl-names =3D "default"; pinctrl-0 =3D <&ngffpcie_reset_h>; @@ -602,6 +608,19 @@ &pcie3x1 { =20 &pcie3x2 { /* mPCIe slot */ + /* + * The board has a gpio-controlled "pcie_refclk" generator, + * so add it to the list of clocks. + */ + clocks =3D <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&cru CLK_PCIE30X2_PIPE_DFT>, + <&pcie_refclk>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "pipe", "ref"; + num-lanes =3D <1>; pinctrl-names =3D "default"; pinctrl-0 =3D <&minipcie_reset_h>; --=20 2.53.0 From nobody Thu Apr 9 18:01:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D217238643D; Tue, 3 Mar 2026 19:52:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772567550; cv=none; b=K6ZfDRYQ7wR6UMVyLAGLoDJoio4A1HOr1a2+eF3T84IJ2Xw8E4A8vc99z+vdZT1xZhZd6mt4WF86jSfQFzrGFTVmC/PTH9dOmPfSoxq+qWoXE+eyIvk22JysBJOyVnQ1QEwdkHRUNaAQg7cpJ9CyYfKnvFps4rjWAL4u8rvXtZk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772567550; c=relaxed/simple; bh=NuR9llP7GHy9Y9058elFyhLur654m0mtWCISGmMQp1Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Tue, 3 Mar 2026 19:52:30 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Tue, 03 Mar 2026 20:52:30 +0100 Subject: [PATCH v3 4/4] arm64: dts: rockchip: Define PCIe clock pinctrl for BPI-R2-Pro Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-4-af5a5207b0a1@ixit.cz> References: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-0-af5a5207b0a1@ixit.cz> In-Reply-To: <20260303-rk3568-bri-r2-pro-fix-pcie-v3-0-af5a5207b0a1@ixit.cz> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Frank Wunderlich Cc: Martin Filla , Charalampos Mitrodimas , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1430; i=david@ixit.cz; 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Some operating systems that rely on correct pin settings may fail to boot as a result. Fixes: 86973ae0355b ("arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro= ") Reported-by: Martin Filla # reported by private message Tested-by: Martin Filla Signed-off-by: David Heidelberg --- arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm6= 4/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index 3cdea9456a28c..95cf4a6236048 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -125,6 +125,8 @@ pcie_refclk: pcie-refclk-clock { clocks =3D <&pcie_refclk_gen>; #clock-cells =3D <0>; enable-gpios =3D <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pcie_clkreq_h>; + pinctrl-names =3D "default"; }; =20 vcc3v3_minipcie: regulator-vcc3v3-minipcie { @@ -652,6 +654,10 @@ ir_receiver_pin: ir-receiver-pin { }; =20 pcie { + pcie_clkreq_h: pcie-clkreq-h { + rockchip,pins =3D <0 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>; + }; + minipcie_enable_h: minipcie-enable-h { rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; }; --=20 2.53.0