From nobody Thu Apr 9 19:21:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEB2737B018; Tue, 3 Mar 2026 15:47:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772552836; cv=none; b=a/+GSsdddgIgCH/EK6xZy7MMB0o4jzRDaxFaR7bDlD9HNK8H2XECeUmdw739irFYG0S8SQZDVq9etMtzAop6Cz+LljuyEVNz6lf+I7g/BcBEqGbwnTbjsHBhV11q7IxXpqKDfPIbyW4XcBgL1zLHCmHsstCP8QJmrL0G0GyFZV0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772552836; c=relaxed/simple; bh=WpK6TM64+IkP3lExn7Vbp3PoT5WVThNQ5k9ZpE2jVJc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jAkG682pMh2GZ9lFxTuknv60bd23HYgJK9Nj0va3E9C1IrQ9P0JBB8NRBiWjSo84IRNgiU6Mk3Pgno2vdMMx+4UVgwWL5oQB4oLfqWFAbanCqm2fwP07FXdY3vf8Xjg0XxzAdhUZ/yh5zXtTHi7ULUtD/rbdeJrHTwBMJqsSMP4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iBL7OGdS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iBL7OGdS" Received: by smtp.kernel.org (Postfix) with ESMTPS id C197DC2BCB0; Tue, 3 Mar 2026 15:47:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772552835; bh=WpK6TM64+IkP3lExn7Vbp3PoT5WVThNQ5k9ZpE2jVJc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=iBL7OGdSTGtCmYDCXcmzZ8PpgPoxXEorCWhGhusawUO8wc6LTyjTttqgwNis7gmhL lKMJYNgTd2R3wEpu0SsJxV5iWBH1KN+gVvG9Oz7dt6QRufHdo401KGczLbjhN+Stk2 L8wnvtJj9oRz5EHD2RyORZR8YjJf4rZ+BvzKDPBLtK2D81JMFrLrAO1ktRqae10Vg1 s6FH6yZvMj9rkkndz+MgCUB90uxbQJaj2/xznnKj1YJetOKf4FGCJ6FX8yIpgxjcaA KBGh6cFTZXj2K9rZ2vYLFsyMyaE0bcz6cAcy7vqhvfbHuwXFXO0LP9k5tTGgeKgHKn 7rI86VtsCryjg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9F4CEDA68E; Tue, 3 Mar 2026 15:47:15 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Tue, 03 Mar 2026 16:47:15 +0100 Subject: [PATCH v2 2/3] arm64: dts: rockchip: Use reference PCIe clock generator for BPI-R2-Pro Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260303-rk3568-bri-r2-pro-fix-pcie-v2-2-04665e55d5a8@ixit.cz> References: <20260303-rk3568-bri-r2-pro-fix-pcie-v2-0-04665e55d5a8@ixit.cz> In-Reply-To: <20260303-rk3568-bri-r2-pro-fix-pcie-v2-0-04665e55d5a8@ixit.cz> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Martin Filla , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3494; i=david@ixit.cz; h=from:subject:message-id; bh=fmz8BMbZFzyFiwv7LpD6cohFb+ECwAt+N054XIm/Qc8=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBppwKC07PB66EJZALmmA2MuLEZkOlZmUGkDjifm cRbOORhdMqJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaacCggAKCRBgAj/E00kg crzPD/9zK+HOjFGvlOcg06a70OOVQKOtQHl0mUL4O/RweCi8gkblwz53Ux1NvfvZm9sCmj6uJvc KH4dHfZbJ+jH4kjGaxRr8K8TxwJp6q5iDQrr4LnTii8f3Qdlx83UP8gfCgPYYWvfVUNqRgvgqj7 bWTBb88L5me0cIgQesJyGQ5rOqg3WVZxEtjZNDoa8NMD30nqNNZirhMfryhxqnLt0MTyayvpViM LTGPPGJwRvYEGmaUxsDy53zd0LWBnQF+4bO9/EcrYTbt0Hw07yf1CdE/Ln791BTWhWYCSiVaqxP I/ojgjms5hmZDtEitw2m1ZY/LR3nHlCGQ1CJHnXYDGa3G1/xb/0R5uq8sdiVp5KZzg6MHwu9VXI PWV2SH/n4CI6WZKm5UZYcOJJl2DcOT1lnq6wRFsSfzLScQ+AEUjHh1ZzYvC15P+k0qSwjmJ7X5B 8fXBWU5cRICI/kHjMUb7IzNaeSPMxhQyaHz1StoypBjIOqfn8tCxMxZnIf7k7Rvj+6WNtYMb8gm OklyP4HKLPPjvGTwX05aNi9tjK4lE/RcWsBC5DRKcZHasJaFd9YqC4N02FkoZLwYJBRy4UJxCUB qQyMFiTpBzz84Bk5ke1WQO/XBY5Goe7Jizb09sy23H7YOc4VKlyQ+HVpZuN21X3fYj216mIseCZ UQX0T+KwGJ9o2QA== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Describe properly PCIe clock, which allows us correct the toplogy (removing the vcc3v3-{minipcie,ngff} dependency on pi6c as supply) and adding the clock dependency in the PCIe nodes. Suggested-by: Heiko Stuebner Tested-by: Martin Filla Signed-off-by: David Heidelberg --- arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 45 +++++++++++++++---= ---- 1 file changed, 31 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm6= 4/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index d02b82c5f979a..a071cb67579c4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -120,18 +120,13 @@ pcie_refclk_gen: pcie-refclk-gen-clock { clock-frequency =3D <100000000>; }; =20 - vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { - compatible =3D "regulator-fixed"; - regulator-name =3D "vcc3v3_pcie"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - enable-active-high; - gpios =3D <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - startup-delay-us =3D <200000>; - vin-supply =3D <&vcc5v0_sys>; + pcie_refclk: pcie-refclk-clock { + compatible =3D "gpio-gate-clock"; + clocks =3D <&pcie_refclk_gen>; + #clock-cells =3D <0>; + enable-gpios =3D <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; }; =20 - /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ vcc3v3_minipcie: regulator-vcc3v3-minipcie { compatible =3D "regulator-fixed"; regulator-name =3D "vcc3v3_minipcie"; @@ -142,10 +137,9 @@ vcc3v3_minipcie: regulator-vcc3v3-minipcie { pinctrl-names =3D "default"; pinctrl-0 =3D <&minipcie_enable_h>; startup-delay-us =3D <50000>; - vin-supply =3D <&vcc3v3_pi6c_05>; + vin-supply =3D <&vcc3v3_sys>; }; =20 - /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ vcc3v3_ngff: regulator-vcc3v3-ngff { compatible =3D "regulator-fixed"; regulator-name =3D "vcc3v3_ngff"; @@ -156,7 +150,7 @@ vcc3v3_ngff: regulator-vcc3v3-ngff { pinctrl-names =3D "default"; pinctrl-0 =3D <&ngffpcie_enable_h>; startup-delay-us =3D <50000>; - vin-supply =3D <&vcc3v3_pi6c_05>; + vin-supply =3D <&vcc3v3_sys>; }; =20 vcc5v0_usb: regulator-vcc5v0-usb { @@ -586,12 +580,23 @@ rgmii_phy1: ethernet-phy@0 { =20 &pcie30phy { data-lanes =3D <1 2>; - phy-supply =3D <&vcc3v3_pi6c_05>; + status =3D "okay"; }; =20 &pcie3x1 { /* M.2 slot */ + /* + * The board has a gpio-controlled "pcie_refclk" generator, + * so add it to the list of clocks. + */ + clocks =3D <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, + <&cru CLK_PCIE30X1_AUX_NDFT>, + <&pcie_refclk>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "ref"; num-lanes =3D <1>; pinctrl-names =3D "default"; pinctrl-0 =3D <&ngffpcie_reset_h>; @@ -602,6 +607,18 @@ &pcie3x1 { =20 &pcie3x2 { /* mPCIe slot */ + /* + * The board has a gpio-controlled "pcie_refclk" generator, + * so add it to the list of clocks. + */ + clocks =3D <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&pcie_refclk>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux", + "ref"; + num-lanes =3D <1>; pinctrl-names =3D "default"; pinctrl-0 =3D <&minipcie_reset_h>; --=20 2.53.0