From nobody Thu Apr 9 19:25:38 2026 Received: from mx-2023-1.gwdg.de (mx-2023-1.gwdg.de [134.76.10.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 973723E51D7; Tue, 3 Mar 2026 14:19:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.76.10.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772547598; cv=none; b=rIQFIkDq535aNaxaNn/05tAlI3zOT6eFCMH0nNOVwBe98CptbrJN2z7JPdzaDGk3DEYKYZAMEPZk44KXUndsAiO9DOKF3ypqeMFIFRcRIVfYklD2o5nk9mOSi6cJDd10a8ZjJGSMSZ+kdk49StgS35kUghU8r1ANXptd9u24wUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772547598; c=relaxed/simple; bh=j5JRn8BDxWYEk9Bob09tmUeE0dFdl/ufaymZCcn8CKk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=t6Plk9Ptb3IT7B29ZicnjVBGJZ/o1dJPjwaXohoncSefUM79PqjMA39WXDDWAIt+3EBXxNmJshV7h4o11pcSb/p2K8lzHXpGGthduTbmQ3iMPywc4xZxbxRD/73hgxL7OGEn1OfDhyPiYIOrmwUHoGk1XsVEu2UJFXM08t5PVaI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cispa.de; spf=pass smtp.mailfrom=cispa.de; dkim=pass (2048-bit key) header.d=cispa.de header.i=@cispa.de header.b=bx+XtFRc; arc=none smtp.client-ip=134.76.10.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cispa.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cispa.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cispa.de header.i=@cispa.de header.b="bx+XtFRc" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=cispa.de; s=2023-rsa; h=CC:To:In-Reply-To:References:Message-ID: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From:Sender: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=2BcOjrNpCibrOdJLkBqx5P6cXuCy4qWNPIEqtnNoka0=; b=bx+XtFRck2NQYURZKzj0Pu2TPi ZJde3H6huowlW8yvSMUd+iaAII9CdNbcoafI4Qo2vxxXsbbc/8YBXARPdRypNtboYEx5fCGOkQCpA eB79fToU8cjQzHGxqzhX5BshdYf6S3V8kdpRrvnGGLrbNaATe7XPRBMPcpt2Ugp+MbJB23WwaCNNg Mq2RmEje/nu2X/6jZ0D8is7iwq6vzAlgdsPDu5fS2haIyUgaDcEA2cRelW8ASqOtRVpsvLTCprNoc LYuw6SBSB331PqMNqsjYUUMo+6V5+Xzg3g7qD73Mt9XKNqla7JxL9xmRUcIS51d/p2Uy/4yUnSoi8 7+nxWVkQ==; Received: from mailer.gwdg.de ([134.76.10.26]:44405) by mailer.gwdg.de with esmtp (GWDG Mailer) (envelope-from ) id 1vxQb8-00850J-11; Tue, 03 Mar 2026 15:19:43 +0100 Received: from mbx19-sub-05.um.gwdg.de ([10.108.142.70] helo=email.gwdg.de) by mailer.gwdg.de with esmtps (TLS1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (GWDG Mailer) (envelope-from ) id 1vxQb9-0006kE-0D; Tue, 03 Mar 2026 15:19:43 +0100 Received: from lukass-mbp-7.lan (10.250.9.200) by MBX19-SUB-05.um.gwdg.de (10.108.142.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Tue, 3 Mar 2026 15:19:42 +0100 From: Lukas Gerlach Date: Tue, 3 Mar 2026 15:19:41 +0100 Subject: [PATCH v2 1/4] KVM: riscv: Fix Spectre-v1 in ONE_REG register access Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260303-kvm-riscv-spectre-v1-v2-1-192caab8e0dc@cispa.de> References: <20260303-kvm-riscv-spectre-v1-v2-0-192caab8e0dc@cispa.de> In-Reply-To: <20260303-kvm-riscv-spectre-v1-v2-0-192caab8e0dc@cispa.de> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones CC: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , , , , , Daniel Weber , Michael Schwarz , Marton Bognar , Jo Van Bulck , Lukas Gerlach X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4830; i=lukas.gerlach@cispa.de; h=from:subject:message-id; bh=j5JRn8BDxWYEk9Bob09tmUeE0dFdl/ufaymZCcn8CKk=; b=owGbwMvMwCGWoTIjqP/42kTG02pJDJnL3v5dkqdzp0c7IKDp3yTmhGlzJ53VWHqdd8/mA3Ibc oSPZ67+1FHKwiDGwSArpsgyVfA1Y98eB56kzMPnYOawMoEMYeDiFICJnGZjZDgldNGT/dFhs6gj 7Du3/XynX7Hn9R9lrt5uSe5Hy6o+309kZPi3SNwklPu9y+6G4mX1Ux+4fi68LBQ5/a54+y3vIN6 GXAYA X-Developer-Key: i=lukas.gerlach@cispa.de; a=openpgp; fpr=9511EB018EBC400C6269C3CE682498528FC7AD61 X-ClientProxiedBy: MBX19-SUB-05.um.gwdg.de (10.108.142.70) To MBX19-SUB-05.um.gwdg.de (10.108.142.70) X-Virus-Scanned: (clean) by clamav X-Spam-Level: - User-controlled register indices from the ONE_REG ioctl are used to index into arrays of register values. Sanitize them with array_index_nospec() to prevent speculative out-of-bounds access. Reviewed-by: Radim Kr=C4=8Dm=C3=A1=C5=99 Signed-off-by: Lukas Gerlach --- arch/riscv/kvm/vcpu_onereg.c | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index e7ab6cb00646..a4c8703a96a9 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -127,6 +128,7 @@ static int kvm_riscv_vcpu_isa_check_host(unsigned long = kvm_ext, unsigned long *g kvm_ext >=3D ARRAY_SIZE(kvm_isa_ext_arr)) return -ENOENT; =20 + kvm_ext =3D array_index_nospec(kvm_ext, ARRAY_SIZE(kvm_isa_ext_arr)); *guest_ext =3D kvm_isa_ext_arr[kvm_ext]; switch (*guest_ext) { case RISCV_ISA_EXT_SMNPM: @@ -443,13 +445,16 @@ static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcp= u *vcpu, unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_RISCV_CORE); + unsigned long regs_max =3D sizeof(struct kvm_riscv_core) / sizeof(unsigne= d long); unsigned long reg_val; =20 if (KVM_REG_SIZE(reg->id) !=3D sizeof(unsigned long)) return -EINVAL; - if (reg_num >=3D sizeof(struct kvm_riscv_core) / sizeof(unsigned long)) + if (reg_num >=3D regs_max) return -ENOENT; =20 + reg_num =3D array_index_nospec(reg_num, regs_max); + if (reg_num =3D=3D KVM_REG_RISCV_CORE_REG(regs.pc)) reg_val =3D cntx->sepc; else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num && @@ -476,13 +481,16 @@ static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcp= u *vcpu, unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_RISCV_CORE); + unsigned long regs_max =3D sizeof(struct kvm_riscv_core) / sizeof(unsigne= d long); unsigned long reg_val; =20 if (KVM_REG_SIZE(reg->id) !=3D sizeof(unsigned long)) return -EINVAL; - if (reg_num >=3D sizeof(struct kvm_riscv_core) / sizeof(unsigned long)) + if (reg_num >=3D regs_max) return -ENOENT; =20 + reg_num =3D array_index_nospec(reg_num, regs_max); + if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) return -EFAULT; =20 @@ -507,10 +515,13 @@ static int kvm_riscv_vcpu_general_get_csr(struct kvm_= vcpu *vcpu, unsigned long *out_val) { struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; + unsigned long regs_max =3D sizeof(struct kvm_riscv_csr) / sizeof(unsigned= long); =20 - if (reg_num >=3D sizeof(struct kvm_riscv_csr) / sizeof(unsigned long)) + if (reg_num >=3D regs_max) return -ENOENT; =20 + reg_num =3D array_index_nospec(reg_num, regs_max); + if (reg_num =3D=3D KVM_REG_RISCV_CSR_REG(sip)) { kvm_riscv_vcpu_flush_interrupts(vcpu); *out_val =3D (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK; @@ -526,10 +537,13 @@ static int kvm_riscv_vcpu_general_set_csr(struct kvm_= vcpu *vcpu, unsigned long reg_val) { struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; + unsigned long regs_max =3D sizeof(struct kvm_riscv_csr) / sizeof(unsigned= long); =20 - if (reg_num >=3D sizeof(struct kvm_riscv_csr) / sizeof(unsigned long)) + if (reg_num >=3D regs_max) return -ENOENT; =20 + reg_num =3D array_index_nospec(reg_num, regs_max); + if (reg_num =3D=3D KVM_REG_RISCV_CSR_REG(sip)) { reg_val &=3D VSIP_VALID_MASK; reg_val <<=3D VSIP_TO_HVIP_SHIFT; @@ -548,11 +562,14 @@ static inline int kvm_riscv_vcpu_smstateen_set_csr(st= ruct kvm_vcpu *vcpu, unsigned long reg_val) { struct kvm_vcpu_smstateen_csr *csr =3D &vcpu->arch.smstateen_csr; + unsigned long regs_max =3D sizeof(struct kvm_riscv_smstateen_csr) / + sizeof(unsigned long); =20 - if (reg_num >=3D sizeof(struct kvm_riscv_smstateen_csr) / - sizeof(unsigned long)) + if (reg_num >=3D regs_max) return -EINVAL; =20 + reg_num =3D array_index_nospec(reg_num, regs_max); + ((unsigned long *)csr)[reg_num] =3D reg_val; return 0; } @@ -562,11 +579,14 @@ static int kvm_riscv_vcpu_smstateen_get_csr(struct kv= m_vcpu *vcpu, unsigned long *out_val) { struct kvm_vcpu_smstateen_csr *csr =3D &vcpu->arch.smstateen_csr; + unsigned long regs_max =3D sizeof(struct kvm_riscv_smstateen_csr) / + sizeof(unsigned long); =20 - if (reg_num >=3D sizeof(struct kvm_riscv_smstateen_csr) / - sizeof(unsigned long)) + if (reg_num >=3D regs_max) return -EINVAL; =20 + reg_num =3D array_index_nospec(reg_num, regs_max); + *out_val =3D ((unsigned long *)csr)[reg_num]; return 0; } --=20 2.51.0