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Sanitize them with array_index_nospec() to prevent speculative out-of-bounds access. Reviewed-by: Radim Kr=C4=8Dm=C3=A1=C5=99 Signed-off-by: Lukas Gerlach --- arch/riscv/kvm/vcpu_onereg.c | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index e7ab6cb00646..a4c8703a96a9 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -127,6 +128,7 @@ static int kvm_riscv_vcpu_isa_check_host(unsigned long = kvm_ext, unsigned long *g kvm_ext >=3D ARRAY_SIZE(kvm_isa_ext_arr)) return -ENOENT; =20 + kvm_ext =3D array_index_nospec(kvm_ext, ARRAY_SIZE(kvm_isa_ext_arr)); *guest_ext =3D kvm_isa_ext_arr[kvm_ext]; switch (*guest_ext) { case RISCV_ISA_EXT_SMNPM: @@ -443,13 +445,16 @@ static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcp= u *vcpu, unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_RISCV_CORE); + unsigned long regs_max =3D sizeof(struct kvm_riscv_core) / sizeof(unsigne= d long); unsigned long reg_val; =20 if (KVM_REG_SIZE(reg->id) !=3D sizeof(unsigned long)) return -EINVAL; - if (reg_num >=3D sizeof(struct kvm_riscv_core) / sizeof(unsigned long)) + if (reg_num >=3D regs_max) return -ENOENT; =20 + reg_num =3D array_index_nospec(reg_num, regs_max); + if (reg_num =3D=3D KVM_REG_RISCV_CORE_REG(regs.pc)) reg_val =3D cntx->sepc; else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num && @@ -476,13 +481,16 @@ static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcp= u *vcpu, unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_RISCV_CORE); + unsigned long regs_max =3D sizeof(struct kvm_riscv_core) / sizeof(unsigne= d long); unsigned long reg_val; =20 if (KVM_REG_SIZE(reg->id) !=3D sizeof(unsigned long)) return -EINVAL; - if (reg_num >=3D sizeof(struct kvm_riscv_core) / sizeof(unsigned long)) + if (reg_num >=3D regs_max) return -ENOENT; =20 + reg_num =3D array_index_nospec(reg_num, regs_max); + if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) return -EFAULT; =20 @@ -507,10 +515,13 @@ static int kvm_riscv_vcpu_general_get_csr(struct kvm_= vcpu *vcpu, unsigned long *out_val) { struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; + unsigned long regs_max =3D sizeof(struct kvm_riscv_csr) / sizeof(unsigned= long); =20 - if (reg_num >=3D sizeof(struct kvm_riscv_csr) / sizeof(unsigned long)) + if (reg_num >=3D regs_max) return -ENOENT; =20 + reg_num =3D array_index_nospec(reg_num, regs_max); + if (reg_num =3D=3D KVM_REG_RISCV_CSR_REG(sip)) { kvm_riscv_vcpu_flush_interrupts(vcpu); *out_val =3D (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK; @@ -526,10 +537,13 @@ static int kvm_riscv_vcpu_general_set_csr(struct kvm_= vcpu *vcpu, unsigned long reg_val) { struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; + unsigned long regs_max =3D sizeof(struct kvm_riscv_csr) / sizeof(unsigned= long); =20 - if (reg_num >=3D sizeof(struct kvm_riscv_csr) / sizeof(unsigned long)) + if (reg_num >=3D regs_max) return -ENOENT; =20 + reg_num =3D array_index_nospec(reg_num, regs_max); + if (reg_num =3D=3D KVM_REG_RISCV_CSR_REG(sip)) { reg_val &=3D VSIP_VALID_MASK; reg_val <<=3D VSIP_TO_HVIP_SHIFT; @@ -548,11 +562,14 @@ static inline int kvm_riscv_vcpu_smstateen_set_csr(st= ruct kvm_vcpu *vcpu, unsigned long reg_val) { struct kvm_vcpu_smstateen_csr *csr =3D &vcpu->arch.smstateen_csr; + unsigned long regs_max =3D sizeof(struct kvm_riscv_smstateen_csr) / + sizeof(unsigned long); =20 - if (reg_num >=3D sizeof(struct kvm_riscv_smstateen_csr) / - sizeof(unsigned long)) + if (reg_num >=3D regs_max) return -EINVAL; =20 + reg_num =3D array_index_nospec(reg_num, regs_max); + ((unsigned long *)csr)[reg_num] =3D reg_val; return 0; } @@ -562,11 +579,14 @@ static int kvm_riscv_vcpu_smstateen_get_csr(struct kv= m_vcpu *vcpu, unsigned long *out_val) { struct kvm_vcpu_smstateen_csr *csr =3D &vcpu->arch.smstateen_csr; + unsigned long regs_max =3D sizeof(struct kvm_riscv_smstateen_csr) / + sizeof(unsigned long); =20 - if (reg_num >=3D sizeof(struct kvm_riscv_smstateen_csr) / - sizeof(unsigned long)) + if (reg_num >=3D regs_max) return -EINVAL; =20 + reg_num =3D array_index_nospec(reg_num, regs_max); + *out_val =3D ((unsigned long *)csr)[reg_num]; return 0; } --=20 2.51.0 From nobody Thu Apr 9 17:59:30 2026 Received: from mx-2023-1.gwdg.de (mx-2023-1.gwdg.de [134.76.10.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 972B6390CA3; Tue, 3 Mar 2026 14:19:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.76.10.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772547597; cv=none; b=D1sjwUJM2CPZnx1Y3k6V9SDo+E29OucpB5yjq+KJFtUgelMGx1YoAm4iQwcYUOomFgV21qAyq3HZHPXl2C0nQIpeioGtdJLsxy+DBVSHKZXGgaO6BWQZsbzmnyd99mh0eFQ/FxImpx+W7yPajgmdS/az5SBhEYFO1YK5Y5N7lk4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772547597; c=relaxed/simple; bh=BlH7+hXy1ms4n8/da7TKhRnIXRsOiXYku1MgTJCyimE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260303-kvm-riscv-spectre-v1-v2-2-192caab8e0dc@cispa.de> References: <20260303-kvm-riscv-spectre-v1-v2-0-192caab8e0dc@cispa.de> In-Reply-To: <20260303-kvm-riscv-spectre-v1-v2-0-192caab8e0dc@cispa.de> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones CC: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , , , , , Daniel Weber , Michael Schwarz , Marton Bognar , Jo Van Bulck , Lukas Gerlach X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2077; i=lukas.gerlach@cispa.de; h=from:subject:message-id; bh=BlH7+hXy1ms4n8/da7TKhRnIXRsOiXYku1MgTJCyimE=; b=owGbwMvMwCGWoTIjqP/42kTG02pJDJnL3v69fFpB2FgmvejjhFmfOq/tboxouxV1K7+VO+ET8 1bug1ePdZSyMIhxMMiKKbJMFXzN2LfHgScp8/A5mDmsTCBDGLg4BWAiv2UY/plJBJ5lrlRUyncQ ThJybn0+2dA4MTbASW666s52j+iJvYwM73aKfH4/+VHQxQc6B02SxRweznnXE2knFn6vM4e1ofA 6PwA= X-Developer-Key: i=lukas.gerlach@cispa.de; a=openpgp; fpr=9511EB018EBC400C6269C3CE682498528FC7AD61 X-ClientProxiedBy: MBX19-SUB-05.um.gwdg.de (10.108.142.70) To MBX19-SUB-05.um.gwdg.de (10.108.142.70) X-Virus-Scanned: (clean) by clamav X-Spam-Level: - User-controlled indices are used to access AIA CSR registers. Sanitize them with array_index_nospec() to prevent speculative out-of-bounds access. Similar to x86 commit 8c86405f606c ("KVM: x86: Protect ioapic_read_indirect() from Spectre-v1/L1TF attacks") and arm64 commit 41b87599c743 ("KVM: arm/arm64: vgic: fix possible spectre-v1 in vgic_get_irq()"). Reviewed-by: Radim Kr=C4=8Dm=C3=A1=C5=99 Signed-off-by: Lukas Gerlach --- arch/riscv/kvm/aia.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c index cac3c2b51d72..38de97d2f5b8 100644 --- a/arch/riscv/kvm/aia.c +++ b/arch/riscv/kvm/aia.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -182,10 +183,13 @@ int kvm_riscv_vcpu_aia_get_csr(struct kvm_vcpu *vcpu, unsigned long *out_val) { struct kvm_vcpu_aia_csr *csr =3D &vcpu->arch.aia_context.guest_csr; + unsigned long regs_max =3D sizeof(struct kvm_riscv_aia_csr) / sizeof(unsi= gned long); =20 - if (reg_num >=3D sizeof(struct kvm_riscv_aia_csr) / sizeof(unsigned long)) + if (reg_num >=3D regs_max) return -ENOENT; =20 + reg_num =3D array_index_nospec(reg_num, regs_max); + *out_val =3D 0; if (kvm_riscv_aia_available()) *out_val =3D ((unsigned long *)csr)[reg_num]; @@ -198,10 +202,13 @@ int kvm_riscv_vcpu_aia_set_csr(struct kvm_vcpu *vcpu, unsigned long val) { struct kvm_vcpu_aia_csr *csr =3D &vcpu->arch.aia_context.guest_csr; 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Sanitize them with array_index_nospec() to prevent speculative out-of-bounds access. Reviewed-by: Radim Kr=C4=8Dm=C3=A1=C5=99 Signed-off-by: Lukas Gerlach --- arch/riscv/kvm/vcpu_fp.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kvm/vcpu_fp.c b/arch/riscv/kvm/vcpu_fp.c index 030904d82b58..bd5a9e7e7165 100644 --- a/arch/riscv/kvm/vcpu_fp.c +++ b/arch/riscv/kvm/vcpu_fp.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include =20 @@ -93,9 +94,11 @@ int kvm_riscv_vcpu_get_reg_fp(struct kvm_vcpu *vcpu, if (reg_num =3D=3D KVM_REG_RISCV_FP_F_REG(fcsr)) reg_val =3D &cntx->fp.f.fcsr; else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <=3D reg_num) && - reg_num <=3D KVM_REG_RISCV_FP_F_REG(f[31])) + reg_num <=3D KVM_REG_RISCV_FP_F_REG(f[31])) { + reg_num =3D array_index_nospec(reg_num, + ARRAY_SIZE(cntx->fp.f.f)); reg_val =3D &cntx->fp.f.f[reg_num]; - else + } else return -ENOENT; } else if ((rtype =3D=3D KVM_REG_RISCV_FP_D) && riscv_isa_extension_available(vcpu->arch.isa, d)) { @@ -107,6 +110,8 @@ int kvm_riscv_vcpu_get_reg_fp(struct kvm_vcpu *vcpu, reg_num <=3D KVM_REG_RISCV_FP_D_REG(f[31])) { if (KVM_REG_SIZE(reg->id) !=3D sizeof(u64)) return -EINVAL; + reg_num =3D array_index_nospec(reg_num, + ARRAY_SIZE(cntx->fp.d.f)); reg_val =3D &cntx->fp.d.f[reg_num]; } else return -ENOENT; @@ -138,9 +143,11 @@ int kvm_riscv_vcpu_set_reg_fp(struct kvm_vcpu *vcpu, if (reg_num =3D=3D KVM_REG_RISCV_FP_F_REG(fcsr)) reg_val =3D &cntx->fp.f.fcsr; else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <=3D reg_num) && - reg_num <=3D KVM_REG_RISCV_FP_F_REG(f[31])) + reg_num <=3D KVM_REG_RISCV_FP_F_REG(f[31])) { + reg_num =3D array_index_nospec(reg_num, + ARRAY_SIZE(cntx->fp.f.f)); reg_val =3D &cntx->fp.f.f[reg_num]; - else + } else return -ENOENT; } else if ((rtype =3D=3D KVM_REG_RISCV_FP_D) && riscv_isa_extension_available(vcpu->arch.isa, d)) { @@ -152,6 +159,8 @@ int kvm_riscv_vcpu_set_reg_fp(struct kvm_vcpu *vcpu, reg_num <=3D KVM_REG_RISCV_FP_D_REG(f[31])) { if (KVM_REG_SIZE(reg->id) !=3D sizeof(u64)) return -EINVAL; + reg_num =3D array_index_nospec(reg_num, + ARRAY_SIZE(cntx->fp.d.f)); reg_val =3D &cntx->fp.d.f[reg_num]; } else return -ENOENT; --=20 2.51.0 From nobody Thu Apr 9 17:59:30 2026 Received: from mx-2023-1.gwdg.de (mx-2023-1.gwdg.de [134.76.10.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 974E93E51EB; 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Received: from mailer.gwdg.de ([134.76.10.26]:36952) by mailer.gwdg.de with esmtp (GWDG Mailer) (envelope-from ) id 1vxQb9-00850c-1k; Tue, 03 Mar 2026 15:19:44 +0100 Received: from mbx19-sub-05.um.gwdg.de ([10.108.142.70] helo=email.gwdg.de) by mailer.gwdg.de with esmtps (TLS1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (GWDG Mailer) (envelope-from ) id 1vxQbA-0006kx-0w; Tue, 03 Mar 2026 15:19:44 +0100 Received: from lukass-mbp-7.lan (10.250.9.200) by MBX19-SUB-05.um.gwdg.de (10.108.142.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Tue, 3 Mar 2026 15:19:43 +0100 From: Lukas Gerlach Date: Tue, 3 Mar 2026 15:19:44 +0100 Subject: [PATCH v2 4/4] KVM: riscv: Fix Spectre-v1 in PMU counter access Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260303-kvm-riscv-spectre-v1-v2-4-192caab8e0dc@cispa.de> References: <20260303-kvm-riscv-spectre-v1-v2-0-192caab8e0dc@cispa.de> In-Reply-To: <20260303-kvm-riscv-spectre-v1-v2-0-192caab8e0dc@cispa.de> To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones CC: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , , , , , Daniel Weber , Michael Schwarz , Marton Bognar , Jo Van Bulck , Lukas Gerlach X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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Sanitize them with array_index_nospec() to prevent speculative out-of-bounds access. Similar to x86 commit 13c5183a4e64 ("KVM: x86: Protect MSR-based index computations in pmu.h from Spectre-v1/L1TF attacks"). Fixes: 8f0153ecd3bf ("RISC-V: KVM: Add skeleton support for perf") Reviewed-by: Radim Kr=C4=8Dm=C3=A1=C5=99 Signed-off-by: Lukas Gerlach --- arch/riscv/kvm/vcpu_pmu.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 4d8d5e9aa53d..0d626f67d08f 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -87,7 +88,8 @@ static void kvm_pmu_release_perf_event(struct kvm_pmc *pm= c) =20 static u64 kvm_pmu_get_perf_event_hw_config(u32 sbi_event_code) { - return hw_event_perf_map[sbi_event_code]; + return hw_event_perf_map[array_index_nospec(sbi_event_code, + SBI_PMU_HW_GENERAL_MAX)]; } =20 static u64 kvm_pmu_get_perf_event_cache_config(u32 sbi_event_code) @@ -218,6 +220,7 @@ static int pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, un= signed long cidx, return -EINVAL; } =20 + cidx =3D array_index_nospec(cidx, RISCV_KVM_MAX_COUNTERS); pmc =3D &kvpmu->pmc[cidx]; =20 if (pmc->cinfo.type !=3D SBI_PMU_CTR_TYPE_FW) @@ -244,6 +247,7 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned= long cidx, return -EINVAL; } =20 + cidx =3D array_index_nospec(cidx, RISCV_KVM_MAX_COUNTERS); pmc =3D &kvpmu->pmc[cidx]; =20 if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { @@ -525,6 +529,7 @@ int kvm_riscv_vcpu_pmu_ctr_info(struct kvm_vcpu *vcpu, = unsigned long cidx, return 0; } =20 + cidx =3D array_index_nospec(cidx, RISCV_KVM_MAX_COUNTERS); retdata->out_val =3D kvpmu->pmc[cidx].cinfo.value; =20 return 0; @@ -559,7 +564,8 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu,= unsigned long ctr_base, } /* Start the counters that have been configured and requested by the gues= t */ for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) { - pmc_index =3D i + ctr_base; + pmc_index =3D array_index_nospec(i + ctr_base, + RISCV_KVM_MAX_COUNTERS); if (!test_bit(pmc_index, kvpmu->pmc_in_use)) continue; /* The guest started the counter again. Reset the overflow status */ @@ -630,7 +636,8 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, = unsigned long ctr_base, =20 /* Stop the counters that have been configured and requested by the guest= */ for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) { - pmc_index =3D i + ctr_base; + pmc_index =3D array_index_nospec(i + ctr_base, + RISCV_KVM_MAX_COUNTERS); if (!test_bit(pmc_index, kvpmu->pmc_in_use)) continue; pmc =3D &kvpmu->pmc[pmc_index]; @@ -761,6 +768,7 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *v= cpu, unsigned long ctr_ba } } =20 + ctr_idx =3D array_index_nospec(ctr_idx, RISCV_KVM_MAX_COUNTERS); pmc =3D &kvpmu->pmc[ctr_idx]; pmc->idx =3D ctr_idx; =20 --=20 2.51.0