From nobody Thu Apr 16 02:01:53 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43E7338C417 for ; Tue, 3 Mar 2026 09:35:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772530546; cv=none; b=ntV8Z4mt8643tIXgtjLxTkjg6j2PFDlJNLnnoR8qy9QX3OrMHianjMzy9eX0+9FCh1CPZmNHnLVeRb+oXDHiqkmmHRnz2J0iVGtcU66V09Ofo+JismSILCNLTHz3mmQzjksP3HyPba+ukwlVc7FbTC4+1txIPs1e+Le3XyrJMV0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772530546; c=relaxed/simple; bh=m/VQMn2jp2mMRtt+R0rOjpAEwbBaQz/MuT9q1xzP0mI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uRC5n5B6jej2s2FDHPal47KO0hGfZ6By5eS/UX5H3yngyU5eC5MZUVxYbBkmxNZD3kJ2ebwwi+ozU/kWjXvvnHlLSk0EyzjZNbMtMgDyk2U0O8w7a87yA3oAGfvl2CJ6ApBnEjKY4QeKyckFwZON8NtaCLUu82et7d9dC4IwZnc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=IRplpQOu; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=PK0OR1MN; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="IRplpQOu"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="PK0OR1MN" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 623536mC3361347 for ; Tue, 3 Mar 2026 09:35:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 8f2M8NDjO2Tnl5mGOoz4d4V+Wo7DeMPNXbyqK36ibgI=; b=IRplpQOudnlOUVB/ wgacD1kdqwkL8qIqUxMv7b/zNJaY3FkDnbnQqZooovZuGi28xmPq4H6z/aCovIg4 6xVtbDWmzCrmNZxZ7yTKmL/tv8mIZAuQBIj4ph4+NAeeL8rKMUC2LEdCDs9BV0OR vwn3iymlLyGfmTKebDXnlW/CaQnn+y1zI+5rfNLpqaIb6qABdqI7xLIx3gYl+kHO HNQNQWIC/0ynTNppfvD1vhoOZWzm0dKIhWoo/C0iWClnuEkPkoYN2Axjmxoss+P9 ldy0WmsSyJLFsh5awONGJtIABZoe2KBMDqp/dbC8qiIT3x2L4IU3DFOQdW8CMqBa Yheirg== Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cns5frwmh-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 03 Mar 2026 09:35:43 +0000 (GMT) Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-c70e8e7fe55so3469335a12.2 for ; Tue, 03 Mar 2026 01:35:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772530543; x=1773135343; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8f2M8NDjO2Tnl5mGOoz4d4V+Wo7DeMPNXbyqK36ibgI=; b=PK0OR1MNDAntoouaFBEu0besRpsJS/qJtroMNGGuP1+rjfgt5y/sQKoWiN3uvemdKm p0/OzKr+ylNROBDZaqliwMx4DGtf/j6x0OY1eyP7HAVEm+NceR971mQo13inX4U05Diy AqfdtgdYcQ4GZOvFA4n0hKcQ9wEvqFUSO/PE4l0sPhXls4ev1RorkYuAu3BLPCViF1s7 CoLv0N5dMeoXwA60kdW2Y5HrzNDY94pjqS/ALdHmyi7iChRljEzsG49z1K3lglzyE08R HGa9XwwpYwVQxYwfXxVdAAEIk0DRNieD0hT29D1eHQXgfiAOys6ebBkyN4PMbnC6KEHt G5Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772530543; x=1773135343; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=8f2M8NDjO2Tnl5mGOoz4d4V+Wo7DeMPNXbyqK36ibgI=; b=P/oQ3Km0dHuseLijUpiLku+jwyjZtcjz4wpmyTLqalx61pvSL/XcB2hvRwFDOIHnUR avfnn/s68mQk0PzjyrQR1ONCJ/AJhn/OAWMcsJbHwG0wv+06H4XYCsCGFDxNQFxByo1I 7ffZOqlNLPSAOlhAWEELX3ZZTYFdW+3GMZwsd07YlDatfCcPY61aSRNvUhycxSWdz7qA bTSYu7vZjXiuSecTjNYenUaCY1c4Kuo4En37k34YtzOv6+9T/5XEKsvpVMLc34OhN2JV 6PJWe94VyoGVTVFQS9MwJ7ZMXkpN2JR1edu67XXg9xRSbjRruAXFc+3e5zp0s1OKnuMU keRg== X-Forwarded-Encrypted: i=1; AJvYcCUCh1cDaDhgoHibqmZPTHOwjtlii+VXoyn8pu9G7QwGiNfVw4DS045eqv1VI29R6UY/zf3KdWl2uUT6bzg=@vger.kernel.org X-Gm-Message-State: AOJu0YySKleUBYjbNoREO/hRlIXvkeWnlufxqWIkhc/NLT+KczdkTiVs x+7DYlQCHm3SUUOVPx0ULHtF6oMmVysJ+c89tDmW0WYEZmGkVXRMNEHhf/k1qZX8ebjuB8W4BnX PdFymRXMs/r0pMOskLB5GuKbPZ7mCtc4GwwJ1iCPbA4jgaQvXo319SJLJKXdPQquTHk8= X-Gm-Gg: ATEYQzzL3axykMjNw75XF4wk2xmyb6NcJUaRHZRGNWAbq5G7EoP0yipcrerVpK2tpfe qwxF0yq1x4eSl8ZWMWWcdOwuOIhhYoTfDloJmJAqJ6yXDy4YirLYRGib8gNG+fES/ZfjnU5gzLr acoQInkUlfRUX2+gotsEyOjBBBOAg51KbXR35S/mbMwf5Z7XsI/TQHZXk7kTNcD812VRqCq3hh5 LdWdHp0E7aweEFfJEjpJLDtDOBu2e3J4P40AaGOyg7JEiC00+l7nUSK61gGWhReCPFt/Fbc1+5L UkHxTayujUOyMuVMRoF2gzyYEVvK63eNEjaQQDbDu8kgqSjPObaOPVfIqDB/5+aHVyeP5K8JoVW Lb4AZcmCXI5YHhyafztigzvzZgukhgSFknlizp7dqXKj53A== X-Received: by 2002:a05:6a00:4143:b0:81c:c98c:aeb7 with SMTP id d2e1a72fcca58-8274d972743mr12354322b3a.7.1772530542776; Tue, 03 Mar 2026 01:35:42 -0800 (PST) X-Received: by 2002:a05:6a00:4143:b0:81c:c98c:aeb7 with SMTP id d2e1a72fcca58-8274d972743mr12354283b3a.7.1772530542133; Tue, 03 Mar 2026 01:35:42 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82739ba6275sm19644212b3a.0.2026.03.03.01.35.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2026 01:35:41 -0800 (PST) From: Taniya Das Date: Tue, 03 Mar 2026 15:05:25 +0530 Subject: [PATCH v4 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260303-gpucc_sm8750_v2-v4-1-2f28562db7c9@oss.qualcomm.com> References: <20260303-gpucc_sm8750_v2-v4-0-2f28562db7c9@oss.qualcomm.com> In-Reply-To: <20260303-gpucc_sm8750_v2-v4-0-2f28562db7c9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=Pv2ergM3 c=1 sm=1 tr=0 ts=69a6ab6f cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=lJl75u3uZd5g0oXYmjoA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: 58bYdMCT7MibvhLj_aa1SyZvEfCponWr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAzMDA3MiBTYWx0ZWRfX31DKwDU3d9iC lcunMyu9kDvGSQMUszNPVrmiop/Am7gVwf38dVtWvuYV4cxAZZ2uO442Q8yFu/U5op7tr5h8dVd jq/tG9Lv2az4kfn554xL4Kgi27nUwK4XCOw/v/BxAHh8gA2ZpU2IB7si5RMwnw2l+M6noBuPCd3 AqDvixDiM6Ex8m/hrDyQXRj8jAQfsJOJa+OHT42PH8ev5feGlhYrv7W0HikroX8asFZisAdjIpX WEyBlrEnpTW3PRPosY0vq2uw2sDOG/xMHevKAY+q6IoCxQwnE921DDJaj15f1s8Csc4gARwAjCB fE2+c3867BkQ4W1yumRygOVmWYLSVwBYBsqq/54/Bb4I8gEXVqEDI+vx9R09YP5cajskoXVPXaK bL1+U4W2TB2H/+J6QjbKQbdWxcdTWE9sQdBTRfO4twLULz1rQmFkyK3qKGYem9JdflFH9AYUdQ2 zKK0Vp56G3C5a0zwdbQ== X-Proofpoint-GUID: 58bYdMCT7MibvhLj_aa1SyZvEfCponWr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_05,2026-03-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 malwarescore=0 spamscore=0 suspectscore=0 adultscore=0 priorityscore=1501 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603030072 From: Konrad Dybcio The SM8750 features a "traditional" GPU_CC block, much of which is controlled through the GMU microcontroller. GPU_CC block requires the MX and CX rail control and thus add the corresponding power-domains and require-opps. Additionally, there's an separate GX_CC block, where the GX GDSC is moved. Update the bindings to accommodate for SM8750 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Taniya Das --- .../bindings/clock/qcom,kaanapali-gxclkctl.yaml | 1 + .../bindings/clock/qcom,sm8450-gpucc.yaml | 23 ++++++++++ include/dt-bindings/clock/qcom,sm8750-gpucc.h | 50 ++++++++++++++++++= ++++ 3 files changed, 74 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkct= l.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.ya= ml index 5490a975f3db7d253a17cc13a67f6c44e0d47ef3..1876f23c174e4ede590847d8022= 2e49b4200d8ba 100644 --- a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml @@ -21,6 +21,7 @@ properties: compatible: enum: - qcom,kaanapali-gxclkctl + - qcom,sm8750-gxclkctl =20 power-domains: description: diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index 6feaa32569f9a852c2049fee00ee7a2e2aefb558..d8828f905bc017172eb8442a8bb= 760781feb372a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -8,6 +8,7 @@ title: Qualcomm Graphics Clock & Reset Controller on SM8450 =20 maintainers: - Konrad Dybcio + - Taniya Das =20 description: | Qualcomm graphics clock control module provides the clocks, resets and p= ower @@ -22,6 +23,7 @@ description: | include/dt-bindings/clock/qcom,sm8550-gpucc.h include/dt-bindings/reset/qcom,sm8450-gpucc.h include/dt-bindings/reset/qcom,sm8650-gpucc.h + include/dt-bindings/reset/qcom,sm8750-gpucc.h include/dt-bindings/reset/qcom,x1e80100-gpucc.h =20 properties: @@ -35,6 +37,7 @@ properties: - qcom,sm8475-gpucc - qcom,sm8550-gpucc - qcom,sm8650-gpucc + - qcom,sm8750-gpucc - qcom,x1e80100-gpucc - qcom,x1p42100-gpucc =20 @@ -44,6 +47,16 @@ properties: - description: GPLL0 main branch source - description: GPLL0 div branch source =20 + power-domains: + items: + - description: A phandle to the MX power-domain + - description: A phandle to the CX power-domain + + required-opps: + items: + - description: A phandle to an OPP node describing MX performance po= ints + - description: A phandle to an OPP node describing CX performance po= ints + required: - compatible - clocks @@ -51,6 +64,16 @@ required: =20 allOf: - $ref: qcom,gcc.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8750-gpucc + then: + required: + - power-domains + - required-opps =20 unevaluatedProperties: false =20 diff --git a/include/dt-bindings/clock/qcom,sm8750-gpucc.h b/include/dt-bin= dings/clock/qcom,sm8750-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..e2143d905fece19f4ef5cf41372= 4f1597daa85ba --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8750-gpucc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DPM_CLK 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_ACCU_SHIFT_CLK 12 +#define GPU_CC_GX_ACD_AHB_FF_CLK 13 +#define GPU_CC_GX_AHB_FF_CLK 14 +#define GPU_CC_GX_GMU_CLK 15 +#define GPU_CC_GX_RCG_AHB_FF_CLK 16 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_DIV_CLK_SRC 21 +#define GPU_CC_MEMNOC_GFX_CLK 22 +#define GPU_CC_PLL0 23 +#define GPU_CC_PLL0_OUT_EVEN 24 +#define GPU_CC_RSCC_HUB_AON_CLK 25 +#define GPU_CC_RSCC_XO_AON_CLK 26 +#define GPU_CC_SLEEP_CLK 27 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 + +/* GPU_CC resets */ +#define GPU_CC_GPU_CC_CB_BCR 0 +#define GPU_CC_GPU_CC_CX_BCR 1 +#define GPU_CC_GPU_CC_FAST_HUB_BCR 2 +#define GPU_CC_GPU_CC_FF_BCR 3 +#define GPU_CC_GPU_CC_GMU_BCR 4 +#define GPU_CC_GPU_CC_GX_BCR 5 +#define GPU_CC_GPU_CC_XO_BCR 6 + +#endif --=20 2.34.1 From nobody Thu Apr 16 02:01:53 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 703BA38CFE2 for ; Tue, 3 Mar 2026 09:35:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772530551; cv=none; b=tk/axZhE8c3sJDebfjorjfAVm8KJ+FGxjYcOdfPtn8IdMSh/wlmX1jEnhyJAfyVKGGRa00sbSxOfaUKCskVr9qwfC3wdz44QSqy/nsrEc50Zf92zGK1rpWQm4bqDQbr8og3SLRAbV44V0V9KPNp1IzCagLUqjC1ehxS2v1tod/Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772530551; c=relaxed/simple; bh=Y5pAl04aUebYG/thbuchVQGiAyUs2xk6hIfZs4ndZL4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YIMMQhyYk9whAfBQqR4t1tJzDfuLFbe/srDoNSf2ckLAt282llQcZhiwU4F8dPqTKCOHUBriNzwfXrriNlXLXmFunHldbV7cNBu5XUHTSxsZ9QLX1A/TRS3bAMXyrl9Jp2CrOx0ICZ/9XB8gFTXNQnw2etmLQ4CXN29BfONjC7s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=lYFUm6l5; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=PepvdafJ; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="lYFUm6l5"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="PepvdafJ" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6235wihb2996001 for ; Tue, 3 Mar 2026 09:35:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 7GzkmwMHGXXvGp2ekHre72j6mmCg0n/yyOQ0krfKYZU=; b=lYFUm6l56y5IA12Q d4DOj/bvD/PTIdG8UzlkGlknpLJ7Jkyuk0mc2W0hXpxo8UeSoulW85d9z34O4xjs h/na6LEv0tO10EE7beAY5ogn5cswgcfq869g6XADaD55EumCJjws68G5BPv7VsZ1 tmV4MzPWsDnLwP+HPTBSBlcjVotHya/cNHPLnpt+ZNUz7NnSdIpFXBk1A9v3z3lJ j8qtsTkTov9lbxsS/ac+lnAktJRKjzZ+4iNu4iJTNCyV54jxBc6SgJpowzgvq7LF Ji6rFsCKFJiKliJ8aQXucMffKZxpUUpV8NVXo9ThV446C+Hk+oFMfQz5IBnl1wVG 2AdHPw== Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cnh6uad93-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 03 Mar 2026 09:35:48 +0000 (GMT) Received: by mail-pf1-f200.google.com with SMTP id d2e1a72fcca58-8272825e843so3457255b3a.1 for ; Tue, 03 Mar 2026 01:35:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772530548; x=1773135348; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7GzkmwMHGXXvGp2ekHre72j6mmCg0n/yyOQ0krfKYZU=; b=PepvdafJxqMuZ2mfCNP0Au6Vfc/LNcg84Qh2lgWAyoinaG51GSJJCNW9+9bZr6anhR cknQbccuUt3zt81PwzCCP6iK7Fud+jE3OsPy+LgaA5xn8ppzs3/0uERqGgJDW6TmqKPI g2ZYFpMSaBnCwAwTElfHuovr30C5egg/hypWW8H8MVVt+O9KU/vJCjDSvzo5ucSfF2Kn PspbdzCDPm3/sfD+JhKsYObQtkDGKkH1z88nAbv0qvtrRGN39y9TvSjdLpsL6VSYiSv7 iy6b0OxsjWZOng1IP7AJsnaMNMc/+5PZPooORs0zlvkhtaIg+dAo1jE9NnWMgs1eV8Js kaXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772530548; x=1773135348; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=7GzkmwMHGXXvGp2ekHre72j6mmCg0n/yyOQ0krfKYZU=; b=uPlkuIA3grB7wgBZQjThanUZIN5qaqALVNAXWMhQDbYhCLmvmc5JnS6TpZKpBUdnQg 0HwQUSKFX0qfiWuDBmU3sR7CNvU1u6MiwTRqd7tPGST8ZXJDDKTexNSiusn8GO8nDUzL rYQ6u4sz/CX7JwRuRK8V7TQ4c2lTg/amiLm/D7Rswe4evNlGS7WI07sKuqvJKHDoh4OC ibfVb1nvXNdkZGWictlnI1KgHUD4c8grH6HHqn2q8a0UMu3eGlg+ekfvQS31MOQWglG3 wUBxjqUVHDFfvMNTC1UdCa7nnCtFGd/1Xq+9Mwe3MtobEtV9SY7zH3J9WVoZh4FPGsgI dJEQ== X-Forwarded-Encrypted: i=1; AJvYcCU4qhm6glTiLQ1pzMgt+H4+SsCZZ6N1929JWLOk9x2Df9f7MFCAjsQhtxUzjSUzou72JeORe9U5t4aWJrg=@vger.kernel.org X-Gm-Message-State: AOJu0YzX+aKcxd8ykJhDFr8mfPEzsfso+W1gNQ3E4kHrkUA960ug3l9U 4jSusJocx60Prb/ykcewFyXyA02iVmR/zwhL0Y4RhIgUPRYw4wcFuPBnygNaKK7x7JM78oGO7he kRloOunBQcAii0Y1GHUY4ispYW92Te43MJhQmgUt+xcOnpluiVjZbmPhmjbIQH8pAOPs= X-Gm-Gg: ATEYQzyaApgQqsTwxmfQ+xRTFSg+unJgBQxmdh3chsPZOVel24ba+7NJs76jVbXhwJc HgtWNpvkryvvWMoWOogqQo/IK3RyrveG93CtiooaOqq2wm1Elxj+Ii7bF1YKN02qZEnNuDa0891 CHARxgf/DLG1oyUkUBZ3qp6wxM1y5VDSova+peWzqI9cpIaUlkgnCXKHbujgQuPhs0hOGXZgalw pBPFFAt+GfY3krKmZomvu/OMq81wmUQYd3mGhgGY/yr4ZIbpp8ZXI583SBK/WiJXxWixGLDTij1 xdfN1Vs5gCYIhvnUI54LDyIqyFXc2w/Z1ezr5FSp+wa2nTIxZVHP1kV4nh+F97Y9LqK+nkeX+8u yL2lQu1N3WzPyfd9C5PqbivD+kqPynIpl7ozTzUK3Tl2FGQ== X-Received: by 2002:a05:6a00:2eaa:b0:827:4a20:1dbd with SMTP id d2e1a72fcca58-8274d9ec077mr14129143b3a.32.1772530547953; Tue, 03 Mar 2026 01:35:47 -0800 (PST) X-Received: by 2002:a05:6a00:2eaa:b0:827:4a20:1dbd with SMTP id d2e1a72fcca58-8274d9ec077mr14129110b3a.32.1772530547431; Tue, 03 Mar 2026 01:35:47 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82739ba6275sm19644212b3a.0.2026.03.03.01.35.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2026 01:35:47 -0800 (PST) From: Taniya Das Date: Tue, 03 Mar 2026 15:05:26 +0530 Subject: [PATCH v4 2/3] clk: qcom: Add a driver for SM8750 GPU clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260303-gpucc_sm8750_v2-v4-2-2f28562db7c9@oss.qualcomm.com> References: <20260303-gpucc_sm8750_v2-v4-0-2f28562db7c9@oss.qualcomm.com> In-Reply-To: <20260303-gpucc_sm8750_v2-v4-0-2f28562db7c9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAzMDA3MiBTYWx0ZWRfXweNsiWKVA4O+ l13/BYhQ8kPEcoU6NX6D51laAoxkYpZWKueBKVvofsA41gij1XV8PIamB6pPPWUDRbxDhBcP5Aq wTH+LKc9S7dDIqIHUj9PxfYLTWXhN9W6vb7RTeijByqEWaRI22dfE3bzY2Mu8+3C4RvsEiVDPg/ x6wyGl9q7BYMUkg2gkhmOuG40S+tyluibruN1TGiKqMH4XgahBGYeC/2hUBH5gc68XSlwiBm31/ onFyvDJp0yRf8rfgEWBppowqATuCqj8nt1ypicTzm9OeSmAmOTTabQ4An1XKTiEpr4o0I0VAe9r kN4fTgLw/0BrATEQz5k8mq7hq089Dkn/hhLZ4tNzkkrm3tgMpak2M/nhv8S/heFGPDgeYlMNT4m iwFnBxpQ8e+biEplFNoVmMbR6p7KNmdUkZar+TGSzrjaFYCyoOhqwu/M299IjnQfV5WdJ9diBSo 1lzfwHSLhBht0vXy4Jw== X-Authority-Analysis: v=2.4 cv=MuhfKmae c=1 sm=1 tr=0 ts=69a6ab74 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=PLT511quuigA__OA0o4A:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-ORIG-GUID: WkiHtdg8ku2tm--AWka1OGVstFWR2s8J X-Proofpoint-GUID: WkiHtdg8ku2tm--AWka1OGVstFWR2s8J X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_05,2026-03-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 suspectscore=0 malwarescore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603030072 From: Konrad Dybcio Support the graphics clock controller for SM8750 for Graphics SW driver to use the clocks. GXCLKCTL (Graphics GX Clock Controller) is a block dedicated to managing clocks for the GPU subsystem on GX power domain. The GX clock controller driver manages only the GX GDSC and the rest of the resources of the controller are managed by the firmware. Update the compatible for Graphics GX Clock Controller for SM8750 as the GX clock controller is a reuse of the Kaanapali driver. Signed-off-by: Konrad Dybcio Co-developed-by: Taniya Das Signed-off-by: Taniya Das Reviewed-by: Abel Vesa --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm8750.c | 473 ++++++++++++++++++++++++++++++= ++++ drivers/clk/qcom/gxclkctl-kaanapali.c | 1 + 4 files changed, 484 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a8a86ea6bb7445e396048a5bba23fce8d719281f..e4ec41e3dc7dee43a5682a3bd93= 297785e67e41f 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1481,6 +1481,15 @@ config SM_GPUCC_8650 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. =20 +config SM_GPUCC_8750 + tristate "SM8750 Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_8750 + help + Support for the graphics clock controller on SM8750 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_LPASSCC_6115 tristate "SM6115 Low Power Audio Subsystem (LPASS) Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 6b0ad8832b55f1914079f15323b8cdd1608ad4c0..817b13f5e78cb534e165b09d95e= 70cd4a58b12bd 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -180,6 +180,7 @@ obj-$(CONFIG_SM_GPUCC_8350) +=3D gpucc-sm8350.o obj-$(CONFIG_SM_GPUCC_8450) +=3D gpucc-sm8450.o obj-$(CONFIG_SM_GPUCC_8550) +=3D gpucc-sm8550.o obj-$(CONFIG_SM_GPUCC_8650) +=3D gpucc-sm8650.o +obj-$(CONFIG_SM_GPUCC_8750) +=3D gpucc-sm8750.o gxclkctl-kaanapali.o obj-$(CONFIG_SM_GPUCC_MILOS) +=3D gpucc-milos.o obj-$(CONFIG_SM_LPASSCC_6115) +=3D lpasscc-sm6115.o obj-$(CONFIG_SM_TCSRCC_8550) +=3D tcsrcc-sm8550.o diff --git a/drivers/clk/qcom/gpucc-sm8750.c b/drivers/clk/qcom/gpucc-sm875= 0.c new file mode 100644 index 0000000000000000000000000000000000000000..ab618c440848e2e763b1a5da3e7= 0c9a97d5a61d9 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm8750.c @@ -0,0 +1,473 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_EVEN, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL0_OUT_ODD, +}; + +static const struct pll_vco taycan_elu_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x34, + .alpha =3D 0x1555, + .config_ctl_val =3D 0x19660387, + .config_ctl_hi_val =3D 0x098060a0, + .config_ctl_hi1_val =3D 0xb416cb20, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &gpu_cc_pll0_config, + .vco_table =3D taycan_elu_vco, + .num_vco =3D ARRAY_SIZE(taycan_elu_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_elu_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll0_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gpu_cc_pll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_taycan_elu_ops, + }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL0_OUT_EVEN, 2 }, + { P_GPU_CC_PLL0_OUT_ODD, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + { .fw_name =3D "bi_tcxo" }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll0_out_even.clkr.hw }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .fw_name =3D "gpll0_out_main" }, + { .fw_name =3D "gpll0_out_main_div" }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(500000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + F(687500000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x9318, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src =3D { + .cmd_rcgr =3D 0x93ec, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_div_clk_src =3D { + .reg =3D 0x942c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk =3D { + .halt_reg =3D 0x90bc, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x90bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_accu_shift_clk =3D { + .halt_reg =3D 0x910c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x910c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x90d4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk =3D { + .halt_reg =3D 0x90e4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x90e4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cxo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_demet_clk =3D { + .halt_reg =3D 0x9010, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_demet_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_dpm_clk =3D { + .halt_reg =3D 0x9110, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9110, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_dpm_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk =3D { + .halt_reg =3D 0x900c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x900c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_freq_measure_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_accu_shift_clk =3D { + .halt_reg =3D 0x9070, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk =3D { + .halt_reg =3D 0x9060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { + .halt_reg =3D 0x7000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk =3D { + .halt_reg =3D 0x93e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x93e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_aon_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk =3D { + .halt_reg =3D 0x90e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_cx_int_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk =3D { + .halt_reg =3D 0x90f4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90f4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_memnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cc_cx_gdsc =3D { + .gdscr =3D 0x9080, + .gds_hw_ctrl =3D 0x9094, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x8, + .pd =3D { + .name =3D "gpu_cc_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct clk_regmap *gpu_cc_sm8750_clocks[] =3D { + [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] =3D &gpu_cc_cx_accu_shift_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, + [GPU_CC_DEMET_CLK] =3D &gpu_cc_demet_clk.clkr, + [GPU_CC_DPM_CLK] =3D &gpu_cc_dpm_clk.clkr, + [GPU_CC_FREQ_MEASURE_CLK] =3D &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_ACCU_SHIFT_CLK] =3D &gpu_cc_gx_accu_shift_clk.clkr, + [GPU_CC_GX_GMU_CLK] =3D &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] =3D &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] =3D &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_DIV_CLK_SRC] =3D &gpu_cc_hub_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] =3D &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, + [GPU_CC_PLL0_OUT_EVEN] =3D &gpu_cc_pll0_out_even.clkr, +}; + +static struct gdsc *gpu_cc_sm8750_gdscs[] =3D { + [GPU_CC_CX_GDSC] =3D &gpu_cc_cx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_sm8750_resets[] =3D { + [GPU_CC_GPU_CC_XO_BCR] =3D { 0x9000 }, + [GPU_CC_GPU_CC_GX_BCR] =3D { 0x905c }, + [GPU_CC_GPU_CC_CX_BCR] =3D { 0x907c }, + [GPU_CC_GPU_CC_GMU_BCR] =3D { 0x9314 }, + [GPU_CC_GPU_CC_CB_BCR] =3D { 0x93a0 }, + [GPU_CC_GPU_CC_FAST_HUB_BCR] =3D { 0x93e4 }, +}; + +static const struct regmap_config gpu_cc_sm8750_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9800, + .fast_io =3D true, +}; + +static struct clk_alpha_pll *gpu_cc_alpha_plls[] =3D { + &gpu_cc_pll0, +}; + +static u32 gpu_cc_sm8750_critical_cbcrs[] =3D { + 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */ + 0x9008, /* GPU_CC_CXO_AON_CLK */ + 0x9064, /* GPU_CC_GX_AHB_FF_CLK */ + 0x90cc, /* GPU_CC_SLEEP_CLK */ + 0x93a4, /* GPU_CC_CB_CLK */ + 0x93a8, /* GPU_CC_RSCC_HUB_AON_CLK */ +}; + +static struct qcom_cc_driver_data gpu_cc_sm8750_driver_data =3D { + .alpha_plls =3D gpu_cc_alpha_plls, + .num_alpha_plls =3D ARRAY_SIZE(gpu_cc_alpha_plls), + .clk_cbcrs =3D gpu_cc_sm8750_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gpu_cc_sm8750_critical_cbcrs), +}; + +static const struct qcom_cc_desc gpu_cc_sm8750_desc =3D { + .config =3D &gpu_cc_sm8750_regmap_config, + .clks =3D gpu_cc_sm8750_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_sm8750_clocks), + .resets =3D gpu_cc_sm8750_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_sm8750_resets), + .gdscs =3D gpu_cc_sm8750_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_sm8750_gdscs), + .use_rpm =3D true, + .driver_data =3D &gpu_cc_sm8750_driver_data, +}; + +static const struct of_device_id gpu_cc_sm8750_match_table[] =3D { + { .compatible =3D "qcom,sm8750-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm8750_match_table); + +static int gpu_cc_sm8750_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gpu_cc_sm8750_desc); +} + +static struct platform_driver gpu_cc_sm8750_driver =3D { + .probe =3D gpu_cc_sm8750_probe, + .driver =3D { + .name =3D "sm8750-gpucc", + .of_match_table =3D gpu_cc_sm8750_match_table, + }, +}; +module_platform_driver(gpu_cc_sm8750_driver); + +MODULE_DESCRIPTION("QTI GPU_CC SM8750 Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/gxclkctl-kaanapali.c b/drivers/clk/qcom/gxclk= ctl-kaanapali.c index c209ce5fe4f003aabefd4421eb4f5662e257912a..d46243ee2ddaaa233361dc00a2f= 64d85ee4ebcaf 100644 --- a/drivers/clk/qcom/gxclkctl-kaanapali.c +++ b/drivers/clk/qcom/gxclkctl-kaanapali.c @@ -53,6 +53,7 @@ static const struct qcom_cc_desc gx_clkctl_kaanapali_desc= =3D { =20 static const struct of_device_id gx_clkctl_kaanapali_match_table[] =3D { { .compatible =3D "qcom,kaanapali-gxclkctl" }, + { .compatible =3D "qcom,sm8750-gxclkctl" }, { } }; MODULE_DEVICE_TABLE(of, gx_clkctl_kaanapali_match_table); --=20 2.34.1 From nobody Thu Apr 16 02:01:53 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87BD6264A65 for ; Tue, 3 Mar 2026 09:35:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772530555; cv=none; b=KFsOb42j9LOH4fmiAGgehE8SzD9/YybUIKH9y3jih28qBK0sGU9hUoEYgAs3hi9tm6EgeiNA7Wetiq7uGj68UaWZ6h2PEyFaqNPsE/8JDJf1Zpl7YvsabuE5eCOjglRt7BxmPQQP0n7oFI1ubhQEzG0ypvAaw65ZSjFy8qNLk/k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772530555; c=relaxed/simple; bh=8vsjqlI+M7EUJrSbJtNAl+t9LeIssW4qbD3UCATYSdw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dSp5q85h/VKRU3tHOO6giAgFM6yDKaLbhXOaKXdiCuSWKC7lm0xTY+A+l81ZPIqt8nLMhbMGs8kkETnL09SGe1Rrx79LOxLzLLO2YL6U02bwmxyPIBEansIhQ2P8ihh7/UzaXCtlGl0WBf++K8VTFct0oJ4AdQrKqce/GOJtf2M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=FyKq62Tz; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=GNd8rZBk; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="FyKq62Tz"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="GNd8rZBk" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6236KVxm1675548 for ; Tue, 3 Mar 2026 09:35:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= pUsyPGULo0g+sI7esZM5K99WIPpuSyqC3mxWOFAeYks=; b=FyKq62TzG64YBtpN eWbsCHcYMaC0YlnmRwInuzTEH92wVhS1C1wEpcEFIej06BlO/L14bauu2L+h9ocS 1xbn6m4yLHK7pE/CydDDL/L6hw7w9IL4KE41bYZItmzuStQ9YKFzYkDVe6Qs3zBg 88uESSCp8aINGqflhlXtirns36NsExwRuv7JwbDJnqmvzd2ha1skFDYWAo9b9HCp gfopZqc06YF0s/h35R3DJTAtrpB/D/5H/EtmObl/cKh/gzFU64bhpknkk4dqufBw RxvocLyeOmskOl6WY04m5oyRYDUlwLVrfaimI6F36hpDGyLUiW51kZkJA+DC+L6+ kJF5ig== Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cnhxsa7p4-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 03 Mar 2026 09:35:53 +0000 (GMT) Received: by mail-pf1-f199.google.com with SMTP id d2e1a72fcca58-824a02e4d29so2264060b3a.1 for ; Tue, 03 Mar 2026 01:35:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772530553; x=1773135353; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=pUsyPGULo0g+sI7esZM5K99WIPpuSyqC3mxWOFAeYks=; b=GNd8rZBkA75scV1D9mS+lXQsiiCEVw/RrwizibHoBFDHwWKt8OvDj8guHn6Yhxvwho Z0UYPh7iUYKXYuYS2+bZ6wasyVVAgXCVDjxpITxuaiqbrJSgGUbll5sXhthpuswgJNjh i15dUfZPqd6uaZaBaU9NjMu+TxjwvLEUqiMjADZvvG8krQTXAndtEAmhRY9asrSbQ11S CGpMGG/NliGvSUasnLnhjFGvzmYzoSMcO7eYOWzcqIwEqGbNaVtPdq2v+HiR2Tz137TC lOHTAKXeAPLCXX6Oj8KDGGqbxLRKXMbBKZwDz/wcjeAZTuMduBE2HBE5qsqy9b9y3M3s WAdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772530553; x=1773135353; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=pUsyPGULo0g+sI7esZM5K99WIPpuSyqC3mxWOFAeYks=; b=n3gWDRH1dFWNgAdZsxgALbIflLtLgkFx7Ic33YaTRSEjfL8y8tab3gpoBoPs3hJKW9 Blh81Pex1n6Syu7LX4eUPXxLZuxQQPfR1jpiF56T6wG1olYMC1OPXWqTL1gavwr70nHJ +eMYZfeQ+/U+Bhj93l+DNO/WosTXRZVdB2xbuA5wL3/7/XY1Uml9cyJ/qpI6IeaeWfx6 Nw7NFs70tJDcHTJwSJfogRpLUo/A1cPSYaotY0rjxQPVlveZ4YgWBQYSt54xWu/o4tSh Ohau0a6jwgbmX1VU2PwWxaPJ6erJLCoxga5EjLdA+RFts7P2DwFjDZtfaY+YtCLFlVj6 QS9Q== X-Forwarded-Encrypted: i=1; AJvYcCWcCHl3kRPlzwDsCb3IlzcmYKuNZR47+heYm7xG9Q+Lb4LBdYJQpiKdgj2iWi9nI9cb/3gd2yxNx2fJuNc=@vger.kernel.org X-Gm-Message-State: AOJu0YwIkSyqG0vyYhv+JkRincR0BtinMM3YbDi5vFzcLjeH67Gi0PLH cjUnlw0eeaQfRzDb+Lmkj9YgSvVRC3+Ze0wC0WRhNJgYTCMHYEwudutj20cKG1QnqGkpXYuK7rb FmP2MWrTQRJkgSBJTI7UCWM0KMKOsuZJhKjLliDQUmCr75SVZb+AqpvSZrAFAz53cC2E= X-Gm-Gg: ATEYQzx1Tnrd3n6W7igWgTd/u5G6AiVVbrXBrOSRqCroRUq/dTLwGn1yUCZXB/Jkx7p oQpJk0L/oLpptfknugpKwuvghp6YWhAviaqgi2uLY9xL0joeVOAJDa4bPm/E0ZYWr/oR3gkEJsW 5eCN8JGHEBJkIfazidcYEgWFQObnYEznUET8/vbQuJgg3CBWCggxOrPMPXl3rFJmJRyo6cTqeQI Jn6y5T8AlQhUar8JM+Ko9HHOFfWNm2UAJ3bJBqjG3UdTEsjldIGkbO8C6TczLMInHnRBoZabQoR UyfpNHjS9EKlpc+H+p0sywHebnparEAVuXmW7yN+5F1w1C7bS/TQ5/NXXpUILQkgi5ammGh/oEg iqoeH6aoc5H6cjiZ4CcQb1/fXX0Br8Pbund5pNzHbE+iLIg== X-Received: by 2002:a05:6a00:2e98:b0:81f:44f9:7c1a with SMTP id d2e1a72fcca58-8274d974eb1mr13967537b3a.3.1772530553071; Tue, 03 Mar 2026 01:35:53 -0800 (PST) X-Received: by 2002:a05:6a00:2e98:b0:81f:44f9:7c1a with SMTP id d2e1a72fcca58-8274d974eb1mr13967513b3a.3.1772530552541; Tue, 03 Mar 2026 01:35:52 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82739ba6275sm19644212b3a.0.2026.03.03.01.35.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2026 01:35:52 -0800 (PST) From: Taniya Das Date: Tue, 03 Mar 2026 15:05:27 +0530 Subject: [PATCH v4 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260303-gpucc_sm8750_v2-v4-3-2f28562db7c9@oss.qualcomm.com> References: <20260303-gpucc_sm8750_v2-v4-0-2f28562db7c9@oss.qualcomm.com> In-Reply-To: <20260303-gpucc_sm8750_v2-v4-0-2f28562db7c9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-ORIG-GUID: mpHVLYUtFebfV8ETwXTkFL7iiB4yCHbJ X-Authority-Analysis: v=2.4 cv=dfmNHHXe c=1 sm=1 tr=0 ts=69a6ab7a cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=CyMIzFe51rGKrm3YhSgA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: mpHVLYUtFebfV8ETwXTkFL7iiB4yCHbJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAzMDA3MiBTYWx0ZWRfXyn7VafPsFn7K xq3bPNztZHUj7f6/WsDKInlPVVnxYbEnF/ZmNcj/1hIszVH9fTJvk+xI7XqZBD/LP+iPUm6AeUn C3tk1zkkndWdqs9T6whkmLPOTIqfmLx0xa7tjWE5UF4DgOc4rr/LRtDGCGxeSczDYLi1GFxwnkm H0s8DmhmV5ErdpoaYLCmjGRolLfaj8sIVz3ZeZpn8BAToIfwHuxOvM/tWVsyIJoM/i4+j2HKRld 7ytGbIOzJlsM+ppxC34rZkhMmxxgnqNG2u+iyZh7EVJt2+tZgHq4yIe9hDgvSeIRSQuwqpq+Bq4 31XX8pWCTIz0SpbfFsXnoGmNn94DD07y52BlT+yY6q4pYuuqP1U+EeSCn6UaVUvLhx5fzL4KVco Enrl6c+j2ZhJvQG/BFKsjxS1V+t7TUAExtRshKqYIu/armd7Tl6UYtt9tI6dEmxjZNb219yh0TD WRgiaFS//gFvUpRD+Ow== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_05,2026-03-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 impostorscore=0 phishscore=0 clxscore=1015 spamscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603030072 From: Konrad Dybcio Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this is simply a separate block housing the GX GDSC) nodes, required to power up the graphics-related hardware. Make use of it by enabling the associated IOMMU as well. The GPU itself needs some more work and will be enabled later. Signed-off-by: Konrad Dybcio Co-developed-by: Taniya Das Signed-off-by: Taniya Das Reviewed-by: Abel Vesa --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 68 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index f56b1f889b857a28859910f5c4465c8ce3473b00..0e7a343297e3f5d7a8189f50726= dc6279078c21c 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -4,7 +4,9 @@ */ =20 #include +#include #include +#include #include #include #include @@ -3001,6 +3003,34 @@ videocc: clock-controller@aaf0000 { #power-domain-cells =3D <1>; }; =20 + gxclkctl: clock-controller@3d64000 { + compatible =3D "qcom,sm8750-gxclkctl"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells =3D <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,sm8750-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + power-domains =3D <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm8750-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; @@ -4515,6 +4545,44 @@ tpdm_swao_out: endpoint { }; }; =20 + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,sm8750-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names =3D "hlos"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + apps_smmu: iommu@15000000 { compatible =3D "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg =3D <0x0 0x15000000 0x0 0x100000>; --=20 2.34.1