From nobody Thu Apr 9 19:23:16 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E96A346A13; Tue, 3 Mar 2026 12:23:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772540639; cv=none; b=eZEYLDeh0HTB4CFv9Y0vjZ/pj3UYxfTqaVNugi7jwg0ye1886Iady0NBSMbvtfeWZTaUHR7xn8eT1xZb1rmcSs9XyDyTe62/CBBvoAdm/6rAhYgWErOvHJcnb4Dm4wOm2ZHvdaBD+TGiJKRXej4r8ShyixyQ12HuQMuUoYMkrDo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772540639; c=relaxed/simple; bh=k2psSwtt7pFUpyYbX9P1rSi0M2ajHVy38X5PZXJoMz4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=KCkkZmxqusC+wG15oSvsp8HdC57sj/MQmPuEF0eWG7pYcvnvlp6DwrnO9+rOn5IpZaDyPw9GGJ1YQfkEGnYw4ZbmCtqfB/tQTQ7ksLkeLjgmIYHYDKmiB5uLpanx/Rbn65F8iDB7BgSJ0k6rFQ7oAHTv/9pO/JCfHHqstANfbtU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=MnrWgzq/; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="MnrWgzq/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1772540636; x=1804076636; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=k2psSwtt7pFUpyYbX9P1rSi0M2ajHVy38X5PZXJoMz4=; b=MnrWgzq/wanDpalxfVbZk5oKkx+SDgLR1+DybxINWpec/yHhxZZQ7tJZ gg3CWy5RbZtupi/M/fKCA/sLHAi3HjdZbw7grka8HMQlQhlmBICrxFzzE ORrp+6tj4XA0az1nn7M79NaVoQw1fvKH58lQO2CsEe2aTv5AC06BSp2w3 OgvDrENGejp0X2N3e6S57S5DcVllP4zaQK2Enwkd5dz820RfJOLseb6ch agi2BE1UWsqLpzm0YJJoGFkDwpFaZtZgd1uZkAZSlwWlrpKeW7caanoOW kZrTSbroEaahyZpEJ/FVMslZ7FyD6uPtqkRLGw+Q3IltsyziYgMDl768z A==; X-CSE-ConnectionGUID: kEh2OTZzQEmVJ8+VJRukVw== X-CSE-MsgGUID: uy86kYEqRCWZk68AYCAj5Q== X-IronPort-AV: E=Sophos;i="6.21,321,1763449200"; d="scan'208";a="54568222" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2026 05:23:52 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Tue, 3 Mar 2026 05:23:47 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 3 Mar 2026 05:23:44 -0700 From: =?utf-8?q?Jens_Emil_Schulz_=C3=98stergaard?= Date: Tue, 3 Mar 2026 13:22:34 +0100 Subject: [PATCH net-next 8/8] net: dsa: lan9645x: add port statistics Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260303-dsa_lan9645x_switch_driver_base-v1-8-bff8ca1396f5@microchip.com> References: <20260303-dsa_lan9645x_switch_driver_base-v1-0-bff8ca1396f5@microchip.com> In-Reply-To: <20260303-dsa_lan9645x_switch_driver_base-v1-0-bff8ca1396f5@microchip.com> To: , Andrew Lunn , "Vladimir Oltean" , "David S. Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Simon Horman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Woojung Huh , Russell King , Steen Hegelund , Daniel Machon CC: , , , =?utf-8?q?Jens_Emil_Schulz_=C3=98stergaard?= X-Mailer: b4 0.15-dev Add statistics support for the port counters. Chip registers are 32 bit, so this unit is responsible maintaining a 64bit software cache, and updating it frequently to handle overflows in hardware. Reviewed-by: Steen Hegelund Signed-off-by: Jens Emil Schulz =C3=98stergaard --- drivers/net/dsa/microchip/lan9645x/Makefile | 1 + drivers/net/dsa/microchip/lan9645x/lan9645x_main.c | 82 ++ drivers/net/dsa/microchip/lan9645x/lan9645x_main.h | 3 + .../net/dsa/microchip/lan9645x/lan9645x_stats.c | 825 +++++++++++++++++= ++++ .../net/dsa/microchip/lan9645x/lan9645x_stats.h | 288 +++++++ 5 files changed, 1199 insertions(+) diff --git a/drivers/net/dsa/microchip/lan9645x/Makefile b/drivers/net/dsa/= microchip/lan9645x/Makefile index a90a46f81c72..486b005cf740 100644 --- a/drivers/net/dsa/microchip/lan9645x/Makefile +++ b/drivers/net/dsa/microchip/lan9645x/Makefile @@ -7,3 +7,4 @@ mchp-lan9645x-objs :=3D lan9645x_main.o \ lan9645x_phylink.o \ lan9645x_vlan.o \ lan9645x_mac.o \ + lan9645x_stats.o \ diff --git a/drivers/net/dsa/microchip/lan9645x/lan9645x_main.c b/drivers/n= et/dsa/microchip/lan9645x/lan9645x_main.c index ba76279b4414..8a1de2588ab8 100644 --- a/drivers/net/dsa/microchip/lan9645x/lan9645x_main.c +++ b/drivers/net/dsa/microchip/lan9645x/lan9645x_main.c @@ -7,6 +7,7 @@ #include =20 #include "lan9645x_main.h" +#include "lan9645x_stats.h" =20 static const char *lan9645x_resource_names[NUM_TARGETS + 1] =3D { [TARGET_GCB] =3D "gcb", @@ -79,6 +80,7 @@ static void lan9645x_teardown(struct dsa_switch *ds) debugfs_remove_recursive(lan9645x->debugfs_root); lan9645x_npi_port_deinit(lan9645x, lan9645x->npi); lan9645x_mac_deinit(lan9645x); + lan9645x_stats_deinit(lan9645x); } =20 static int lan9645x_change_mtu(struct dsa_switch *ds, int port, int new_mt= u) @@ -274,6 +276,12 @@ static int lan9645x_setup(struct dsa_switch *ds) =20 lan9645x_port_set_tail_drop_wm(lan9645x); =20 + err =3D lan9645x_stats_init(lan9645x); + if (err) { + dev_err(dev, "Lan9645x setup: failed to init stats."); + return err; + } + ds->mtu_enforcement_ingress =3D true; ds->assisted_learning_on_cpu_port =3D true; ds->fdb_isolation =3D true; @@ -636,6 +644,68 @@ static int lan9645x_fdb_del(struct dsa_switch *ds, int= port, return __lan9645x_fdb_del(lan9645x, port, addr, vid, br); } =20 +static void lan9645x_get_strings(struct dsa_switch *ds, int port, u32 stri= ngset, + uint8_t *data) +{ + lan9645x_stats_get_strings(ds->priv, port, stringset, data); +} + +static void lan9645x_get_ethtool_stats(struct dsa_switch *ds, int port, + uint64_t *data) +{ + lan9645x_stats_get_ethtool_stats(ds->priv, port, data); +} + +static int lan9645x_get_sset_count(struct dsa_switch *ds, int port, int ss= et) +{ + return lan9645x_stats_get_sset_count(ds->priv, port, sset); +} + +static void lan9645x_get_eth_mac_stats(struct dsa_switch *ds, int port, + struct ethtool_eth_mac_stats *mac_stats) +{ + lan9645x_stats_get_eth_mac_stats(ds->priv, port, mac_stats); +} + +static void +lan9645x_get_rmon_stats(struct dsa_switch *ds, int port, + struct ethtool_rmon_stats *rmon_stats, + const struct ethtool_rmon_hist_range **ranges) +{ + lan9645x_stats_get_rmon_stats(ds->priv, port, rmon_stats, ranges); +} + +static void lan9645x_get_stats64(struct dsa_switch *ds, int port, + struct rtnl_link_stats64 *s) +{ + lan9645x_stats_get_stats64(ds->priv, port, s); +} + +static void lan9645x_get_pause_stats(struct dsa_switch *ds, int port, + struct ethtool_pause_stats *pause_stats) +{ + lan9645x_stats_get_pause_stats(ds->priv, port, pause_stats); +} + +static void lan9645x_get_mm_stats(struct dsa_switch *ds, int port, + struct ethtool_mm_stats *stats) +{ + lan9645x_stats_get_mm_stats(ds->priv, port, stats); +} + +static void lan9645x_get_eth_phy_stats(struct dsa_switch *ds, int port, + struct ethtool_eth_phy_stats *phy_stats) +{ + lan9645x_stats_get_eth_phy_stats(ds->priv, port, phy_stats); +} + +static void +lan9645x_get_eth_ctrl_stats(struct dsa_switch *ds, int port, + struct ethtool_eth_ctrl_stats *ctrl_stats) +{ + lan9645x_stats_get_eth_ctrl_stats(ds->priv, port, ctrl_stats); +} + static const struct dsa_switch_ops lan9645x_switch_ops =3D { .get_tag_protocol =3D lan9645x_get_tag_protocol, .connect_tag_protocol =3D lan9645x_connect_tag_protocol, @@ -668,6 +738,18 @@ static const struct dsa_switch_ops lan9645x_switch_ops= =3D { .port_fdb_dump =3D lan9645x_fdb_dump, .port_fdb_add =3D lan9645x_fdb_add, .port_fdb_del =3D lan9645x_fdb_del, + + /* Port statistics counters. */ + .get_strings =3D lan9645x_get_strings, + .get_ethtool_stats =3D lan9645x_get_ethtool_stats, + .get_sset_count =3D lan9645x_get_sset_count, + .get_eth_mac_stats =3D lan9645x_get_eth_mac_stats, + .get_rmon_stats =3D lan9645x_get_rmon_stats, + .get_stats64 =3D lan9645x_get_stats64, + .get_pause_stats =3D lan9645x_get_pause_stats, + .get_mm_stats =3D lan9645x_get_mm_stats, + .get_eth_phy_stats =3D lan9645x_get_eth_phy_stats, + .get_eth_ctrl_stats =3D lan9645x_get_eth_ctrl_stats, }; =20 static int lan9645x_request_target_regmaps(struct lan9645x *lan9645x) diff --git a/drivers/net/dsa/microchip/lan9645x/lan9645x_main.h b/drivers/n= et/dsa/microchip/lan9645x/lan9645x_main.h index 4c7111375918..fe801d0ed39a 100644 --- a/drivers/net/dsa/microchip/lan9645x/lan9645x_main.h +++ b/drivers/net/dsa/microchip/lan9645x/lan9645x_main.h @@ -217,6 +217,9 @@ struct lan9645x { u8 vlan_flags[VLAN_N_VID]; DECLARE_BITMAP(cpu_vlan_mask, VLAN_N_VID); /* CPU VLAN membership */ =20 + /* Statistics */ + struct lan9645x_stats *stats; + int num_port_dis; bool dd_dis; bool tsn_dis; diff --git a/drivers/net/dsa/microchip/lan9645x/lan9645x_stats.c b/drivers/= net/dsa/microchip/lan9645x/lan9645x_stats.c new file mode 100644 index 000000000000..43078e441e55 --- /dev/null +++ b/drivers/net/dsa/microchip/lan9645x/lan9645x_stats.c @@ -0,0 +1,825 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (C) 2026 Microchip Technology Inc. + */ + +#include +#include + +#include "lan9645x_main.h" +#include "lan9645x_stats.h" + +#define LAN9645X_STATS_CHECK_DELAY (3 * HZ) + +static const struct lan9645x_stat_region lan9645x_port_stat_regions[] =3D { + /* RX region */ + { .base_offset =3D 0x0, .cnt =3D 67, .cnts_base_idx =3D 0 }, + /* TX region */ + { .base_offset =3D 0x80, .cnt =3D 48, .cnts_base_idx =3D 67 }, + /* DR region */ + { .base_offset =3D 0x100, .cnt =3D 18, .cnts_base_idx =3D 115 }, +}; + +static const struct lan9645x_stat_layout lan9645x_port_stats_layout[] =3D { + { .name =3D "rx_oct", .offset =3D 0x0 }, + { .name =3D "rx_uc", .offset =3D 0x1 }, + { .name =3D "rx_mc", .offset =3D 0x2 }, + { .name =3D "rx_bc", .offset =3D 0x3 }, + { .name =3D "rx_short", .offset =3D 0x4 }, + { .name =3D "rx_frag", .offset =3D 0x5 }, + { .name =3D "rx_jabber", .offset =3D 0x6 }, + { .name =3D "rx_crc", .offset =3D 0x7 }, + { .name =3D "rx_symbol_err", .offset =3D 0x8 }, + { .name =3D "rx_sz_64", .offset =3D 0x9 }, + { .name =3D "rx_sz_65_127", .offset =3D 0xa }, + { .name =3D "rx_sz_128_255", .offset =3D 0xb }, + { .name =3D "rx_sz_256_511", .offset =3D 0xc }, + { .name =3D "rx_sz_512_1023", .offset =3D 0xd }, + { .name =3D "rx_sz_1024_1526", .offset =3D 0xe }, + { .name =3D "rx_sz_jumbo", .offset =3D 0xf }, + { .name =3D "rx_pause", .offset =3D 0x10 }, + { .name =3D "rx_control", .offset =3D 0x11 }, + { .name =3D "rx_long", .offset =3D 0x12 }, + { .name =3D "rx_cat_drop", .offset =3D 0x13 }, + { .name =3D "rx_red_prio_0", .offset =3D 0x14 }, + { .name =3D "rx_red_prio_1", .offset =3D 0x15 }, + { .name =3D "rx_red_prio_2", .offset =3D 0x16 }, + { .name =3D "rx_red_prio_3", .offset =3D 0x17 }, + { .name =3D "rx_red_prio_4", .offset =3D 0x18 }, + { .name =3D "rx_red_prio_5", .offset =3D 0x19 }, + { .name =3D "rx_red_prio_6", .offset =3D 0x1a }, + { .name =3D "rx_red_prio_7", .offset =3D 0x1b }, + { .name =3D "rx_yellow_prio_0", .offset =3D 0x1c }, + { .name =3D "rx_yellow_prio_1", .offset =3D 0x1d }, + { .name =3D "rx_yellow_prio_2", .offset =3D 0x1e }, + { .name =3D "rx_yellow_prio_3", .offset =3D 0x1f }, + { .name =3D "rx_yellow_prio_4", .offset =3D 0x20 }, + { .name =3D "rx_yellow_prio_5", .offset =3D 0x21 }, + { .name =3D "rx_yellow_prio_6", .offset =3D 0x22 }, + { .name =3D "rx_yellow_prio_7", .offset =3D 0x23 }, + { .name =3D "rx_green_prio_0", .offset =3D 0x24 }, + { .name =3D "rx_green_prio_1", .offset =3D 0x25 }, + { .name =3D "rx_green_prio_2", .offset =3D 0x26 }, + { .name =3D "rx_green_prio_3", .offset =3D 0x27 }, + { .name =3D "rx_green_prio_4", .offset =3D 0x28 }, + { .name =3D "rx_green_prio_5", .offset =3D 0x29 }, + { .name =3D "rx_green_prio_6", .offset =3D 0x2a }, + { .name =3D "rx_green_prio_7", .offset =3D 0x2b }, + { .name =3D "rx_assembly_err", .offset =3D 0x2c }, + { .name =3D "rx_smd_err", .offset =3D 0x2d }, + { .name =3D "rx_assembly_ok", .offset =3D 0x2e }, + { .name =3D "rx_merge_frag", .offset =3D 0x2f }, + { .name =3D "rx_pmac_oct", .offset =3D 0x30 }, + { .name =3D "rx_pmac_uc", .offset =3D 0x31 }, + { .name =3D "rx_pmac_mc", .offset =3D 0x32 }, + { .name =3D "rx_pmac_bc", .offset =3D 0x33 }, + { .name =3D "rx_pmac_short", .offset =3D 0x34 }, + { .name =3D "rx_pmac_frag", .offset =3D 0x35 }, + { .name =3D "rx_pmac_jabber", .offset =3D 0x36 }, + { .name =3D "rx_pmac_crc", .offset =3D 0x37 }, + { .name =3D "rx_pmac_symbol_err", .offset =3D 0x38 }, + { .name =3D "rx_pmac_sz_64", .offset =3D 0x39 }, + { .name =3D "rx_pmac_sz_65_127", .offset =3D 0x3a }, + { .name =3D "rx_pmac_sz_128_255", .offset =3D 0x3b }, + { .name =3D "rx_pmac_sz_256_511", .offset =3D 0x3c }, + { .name =3D "rx_pmac_sz_512_1023", .offset =3D 0x3d }, + { .name =3D "rx_pmac_sz_1024_1526", .offset =3D 0x3e }, + { .name =3D "rx_pmac_sz_jumbo", .offset =3D 0x3f }, + { .name =3D "rx_pmac_pause", .offset =3D 0x40 }, + { .name =3D "rx_pmac_control", .offset =3D 0x41 }, + { .name =3D "rx_pmac_long", .offset =3D 0x42 }, + { .name =3D "tx_oct", .offset =3D 0x80 }, + { .name =3D "tx_uc", .offset =3D 0x81 }, + { .name =3D "tx_mc", .offset =3D 0x82 }, + { .name =3D "tx_bc", .offset =3D 0x83 }, + { .name =3D "tx_col", .offset =3D 0x84 }, + { .name =3D "tx_drop", .offset =3D 0x85 }, + { .name =3D "tx_pause", .offset =3D 0x86 }, + { .name =3D "tx_sz_64", .offset =3D 0x87 }, + { .name =3D "tx_sz_65_127", .offset =3D 0x88 }, + { .name =3D "tx_sz_128_255", .offset =3D 0x89 }, + { .name =3D "tx_sz_256_511", .offset =3D 0x8a }, + { .name =3D "tx_sz_512_1023", .offset =3D 0x8b }, + { .name =3D "tx_sz_1024_1526", .offset =3D 0x8c }, + { .name =3D "tx_sz_jumbo", .offset =3D 0x8d }, + { .name =3D "tx_yellow_prio_0", .offset =3D 0x8e }, + { .name =3D "tx_yellow_prio_1", .offset =3D 0x8f }, + { .name =3D "tx_yellow_prio_2", .offset =3D 0x90 }, + { .name =3D "tx_yellow_prio_3", .offset =3D 0x91 }, + { .name =3D "tx_yellow_prio_4", .offset =3D 0x92 }, + { .name =3D "tx_yellow_prio_5", .offset =3D 0x93 }, + { .name =3D "tx_yellow_prio_6", .offset =3D 0x94 }, + { .name =3D "tx_yellow_prio_7", .offset =3D 0x95 }, + { .name =3D "tx_green_prio_0", .offset =3D 0x96 }, + { .name =3D "tx_green_prio_1", .offset =3D 0x97 }, + { .name =3D "tx_green_prio_2", .offset =3D 0x98 }, + { .name =3D "tx_green_prio_3", .offset =3D 0x99 }, + { .name =3D "tx_green_prio_4", .offset =3D 0x9a }, + { .name =3D "tx_green_prio_5", .offset =3D 0x9b }, + { .name =3D "tx_green_prio_6", .offset =3D 0x9c }, + { .name =3D "tx_green_prio_7", .offset =3D 0x9d }, + { .name =3D "tx_aged", .offset =3D 0x9e }, + { .name =3D "tx_llct", .offset =3D 0x9f }, + { .name =3D "tx_ct", .offset =3D 0xa0 }, + { .name =3D "tx_bufdrop", .offset =3D 0xa1 }, + { .name =3D "tx_mm_hold", .offset =3D 0xa2 }, + { .name =3D "tx_merge_frag", .offset =3D 0xa3 }, + { .name =3D "tx_pmac_oct", .offset =3D 0xa4 }, + { .name =3D "tx_pmac_uc", .offset =3D 0xa5 }, + { .name =3D "tx_pmac_mc", .offset =3D 0xa6 }, + { .name =3D "tx_pmac_bc", .offset =3D 0xa7 }, + { .name =3D "tx_pmac_pause", .offset =3D 0xa8 }, + { .name =3D "tx_pmac_sz_64", .offset =3D 0xa9 }, + { .name =3D "tx_pmac_sz_65_127", .offset =3D 0xaa }, + { .name =3D "tx_pmac_sz_128_255", .offset =3D 0xab }, + { .name =3D "tx_pmac_sz_256_511", .offset =3D 0xac }, + { .name =3D "tx_pmac_sz_512_1023", .offset =3D 0xad }, + { .name =3D "tx_pmac_sz_1024_1526", .offset =3D 0xae }, + { .name =3D "tx_pmac_sz_jumbo", .offset =3D 0xaf }, + { .name =3D "dr_local", .offset =3D 0x100 }, + { .name =3D "dr_tail", .offset =3D 0x101 }, + { .name =3D "dr_yellow_prio_0", .offset =3D 0x102 }, + { .name =3D "dr_yellow_prio_1", .offset =3D 0x103 }, + { .name =3D "dr_yellow_prio_2", .offset =3D 0x104 }, + { .name =3D "dr_yellow_prio_3", .offset =3D 0x105 }, + { .name =3D "dr_yellow_prio_4", .offset =3D 0x106 }, + { .name =3D "dr_yellow_prio_5", .offset =3D 0x107 }, + { .name =3D "dr_yellow_prio_6", .offset =3D 0x108 }, + { .name =3D "dr_yellow_prio_7", .offset =3D 0x109 }, + { .name =3D "dr_green_prio_0", .offset =3D 0x10a }, + { .name =3D "dr_green_prio_1", .offset =3D 0x10b }, + { .name =3D "dr_green_prio_2", .offset =3D 0x10c }, + { .name =3D "dr_green_prio_3", .offset =3D 0x10d }, + { .name =3D "dr_green_prio_4", .offset =3D 0x10e }, + { .name =3D "dr_green_prio_5", .offset =3D 0x10f }, + { .name =3D "dr_green_prio_6", .offset =3D 0x110 }, + { .name =3D "dr_green_prio_7", .offset =3D 0x111 }, +}; + +static const struct lan9645x_view_stats lan9645x_view_stat_cfgs[] =3D { + [LAN9645X_STAT_PORTS] =3D { + .name =3D "ports", + .type =3D LAN9645X_STAT_PORTS, + .layout =3D lan9645x_port_stats_layout, + .num_cnts =3D ARRAY_SIZE(lan9645x_port_stats_layout), + .num_indexes =3D NUM_PHYS_PORTS, + .regions =3D lan9645x_port_stat_regions, + .num_regions =3D ARRAY_SIZE(lan9645x_port_stat_regions), + }, +}; + +static void __lan9645x_stats_view_idx_update(struct lan9645x *lan9645x, + enum lan9645x_view_stat_type vtype, + int idx) +{ + struct lan9645x_stat_region region; + struct lan9645x_view_stats *vstats; + u64 *idx_counters; + u32 *region_buf; + int cntr; + int err; + + lockdep_assert_held(&lan9645x->stats->hw_lock); + + vstats =3D lan9645x_get_vstats(lan9645x, vtype); + if (!vstats || idx < 0 || idx >=3D vstats->num_indexes) + return; + + lan_wr(SYS_STAT_CFG_STAT_VIEW_SET(idx), lan9645x, SYS_STAT_CFG); + + idx_counters =3D STATS_INDEX(vstats, idx); + region_buf =3D &vstats->buf[vstats->num_cnts * idx]; + + /* Each region for this index contains counters which are at sequential + * addresses, so we can use bulk reads to ease lock pressure a bit. + */ + for (int r =3D 0; r < vstats->num_regions; r++) { + region =3D vstats->regions[r]; + err =3D lan_bulk_rd(®ion_buf[region.cnts_base_idx], region.cnt, + lan9645x, SYS_CNT(region.base_offset)); + if (err) { + dev_err(lan9645x->dev, + "stats bulk read err vtype=3D%d idx=3D%d err=3D%d", + vtype, idx, err); + return; + } + } + + for (cntr =3D 0; cntr < vstats->num_cnts; cntr++) + lan9645x_stats_add_cnt(&idx_counters[cntr], region_buf[cntr]); +} + +void lan9645x_stats_view_idx_update(struct lan9645x *lan9645x, + enum lan9645x_view_stat_type vtype, int idx) +{ + struct lan9645x_stats *s =3D lan9645x->stats; + + mutex_lock(&s->hw_lock); + __lan9645x_stats_view_idx_update(lan9645x, vtype, idx); + mutex_unlock(&s->hw_lock); +} + +void lan9645x_stats_view_update(struct lan9645x *lan9645x, + enum lan9645x_view_stat_type vtype) +{ + struct lan9645x_stats *s =3D lan9645x->stats; + struct lan9645x_view_stats *vstats; + int idx =3D 0; + + vstats =3D lan9645x_get_vstats(lan9645x, vtype); + if (!vstats) + return; + + switch (vtype) { + case LAN9645X_STAT_PORTS: + mutex_lock(&s->hw_lock); + for (idx =3D 0; idx < vstats->num_indexes; idx++) { + if (lan9645x_port_is_used(lan9645x, idx)) + __lan9645x_stats_view_idx_update(lan9645x, + vtype, idx); + } + mutex_unlock(&s->hw_lock); + return; + default: + return; + } +} + +static void lan9645x_stats_update(struct lan9645x *lan9645x) +{ + for (int vtype =3D 0; vtype < LAN9645X_STAT_NUM; vtype++) + lan9645x_stats_view_update(lan9645x, vtype); +} + +void lan9645x_stats_get_strings(struct lan9645x *lan9645x, int port, + u32 stringset, u8 *data) +{ + struct lan9645x_view_stats *port_stats; + int i; + + if (stringset !=3D ETH_SS_STATS) + return; + + port_stats =3D lan9645x_get_vstats(lan9645x, LAN9645X_STAT_PORTS); + + for (i =3D 0; i < port_stats->num_cnts; i++) + memcpy(data + i * ETH_GSTRING_LEN, port_stats->layout[i].name, + ETH_GSTRING_LEN); +} + +int lan9645x_stats_get_sset_count(struct lan9645x *lan9645x, int port, int= sset) +{ + struct lan9645x_view_stats *port_stats; + + if (sset !=3D ETH_SS_STATS) + return -EOPNOTSUPP; + + port_stats =3D lan9645x_get_vstats(lan9645x, LAN9645X_STAT_PORTS); + + return port_stats->num_cnts; +} + +void lan9645x_stats_get_ethtool_stats(struct lan9645x *lan9645x, int port, + u64 *data) +{ + struct lan9645x_view_stats *port_stats; + int cntr; + u64 *s; + + mutex_lock(&lan9645x->stats->hw_lock); + + __lan9645x_stats_view_idx_update(lan9645x, LAN9645X_STAT_PORTS, port); + + port_stats =3D lan9645x_get_vstats(lan9645x, LAN9645X_STAT_PORTS); + + s =3D STATS_INDEX(port_stats, port); + + for (cntr =3D 0; cntr < port_stats->num_cnts; cntr++) + *data++ =3D s[cntr]; + + mutex_unlock(&lan9645x->stats->hw_lock); +} + +void lan9645x_stats_get_eth_mac_stats(struct lan9645x *lan9645x, int port, + struct ethtool_eth_mac_stats *mac_stats) +{ + u64 *port_counters; + + mutex_lock(&lan9645x->stats->hw_lock); + + __lan9645x_stats_view_idx_update(lan9645x, LAN9645X_STAT_PORTS, port); + + port_counters =3D STAT_COUNTERS(lan9645x, LAN9645X_STAT_PORTS, port); + + mac_stats->FramesTransmittedOK =3D + port_counters[SCNT_TX_UC] + + port_counters[SCNT_TX_MC] + + port_counters[SCNT_TX_BC] + + port_counters[SCNT_TX_PMAC_UC] + + port_counters[SCNT_TX_PMAC_MC] + + port_counters[SCNT_TX_PMAC_BC]; + mac_stats->SingleCollisionFrames =3D port_counters[SCNT_TX_COL]; + mac_stats->FramesReceivedOK =3D port_counters[SCNT_RX_UC] + + port_counters[SCNT_RX_MC] + + port_counters[SCNT_RX_BC]; + mac_stats->FrameCheckSequenceErrors =3D + port_counters[SCNT_RX_CRC] + + port_counters[SCNT_RX_PMAC_CRC]; + mac_stats->OctetsTransmittedOK =3D + port_counters[SCNT_TX_OCT] + + port_counters[SCNT_TX_PMAC_OCT]; + mac_stats->FramesWithDeferredXmissions =3D port_counters[SCNT_TX_MM_HOLD]; + mac_stats->OctetsReceivedOK =3D + port_counters[SCNT_RX_OCT] + + port_counters[SCNT_RX_PMAC_OCT]; + mac_stats->MulticastFramesXmittedOK =3D + port_counters[SCNT_TX_MC] + + port_counters[SCNT_TX_PMAC_MC]; + mac_stats->BroadcastFramesXmittedOK =3D + port_counters[SCNT_TX_BC] + + port_counters[SCNT_TX_PMAC_BC]; + mac_stats->MulticastFramesReceivedOK =3D + port_counters[SCNT_RX_MC] + + port_counters[SCNT_RX_PMAC_MC]; + mac_stats->BroadcastFramesReceivedOK =3D + port_counters[SCNT_RX_BC] + + port_counters[SCNT_RX_PMAC_BC]; + mac_stats->InRangeLengthErrors =3D + port_counters[SCNT_RX_FRAG] + + port_counters[SCNT_RX_JABBER] + + port_counters[SCNT_RX_CRC] + + port_counters[SCNT_RX_PMAC_FRAG] + + port_counters[SCNT_RX_PMAC_JABBER] + + port_counters[SCNT_RX_PMAC_CRC]; + mac_stats->OutOfRangeLengthField =3D port_counters[SCNT_RX_SHORT] + + port_counters[SCNT_RX_PMAC_SHORT] + + port_counters[SCNT_RX_LONG] + + port_counters[SCNT_RX_PMAC_LONG]; + mac_stats->FrameTooLongErrors =3D + port_counters[SCNT_RX_LONG] + + port_counters[SCNT_RX_PMAC_LONG]; + + mutex_unlock(&lan9645x->stats->hw_lock); +} + +static const struct ethtool_rmon_hist_range lan9645x_rmon_ranges[] =3D { + { 0, 64 }, + { 65, 127 }, + { 128, 255 }, + { 256, 511 }, + { 512, 1023 }, + { 1024, 1526 }, + { 1527, 0xffff }, + {} +}; + +void +lan9645x_stats_get_rmon_stats(struct lan9645x *lan9645x, int port, + struct ethtool_rmon_stats *rmon_stats, + const struct ethtool_rmon_hist_range **ranges) +{ + u64 *port_cnt; + + mutex_lock(&lan9645x->stats->hw_lock); + + __lan9645x_stats_view_idx_update(lan9645x, LAN9645X_STAT_PORTS, port); + + port_cnt =3D STAT_COUNTERS(lan9645x, LAN9645X_STAT_PORTS, port); + + rmon_stats->undersize_pkts =3D + port_cnt[SCNT_RX_SHORT] + + port_cnt[SCNT_RX_PMAC_SHORT]; + rmon_stats->oversize_pkts =3D + port_cnt[SCNT_RX_LONG] + + port_cnt[SCNT_RX_PMAC_LONG]; + rmon_stats->fragments =3D + port_cnt[SCNT_RX_FRAG] + + port_cnt[SCNT_RX_PMAC_FRAG]; + rmon_stats->jabbers =3D + port_cnt[SCNT_RX_JABBER] + + port_cnt[SCNT_RX_PMAC_JABBER]; + + rmon_stats->hist[0] =3D + port_cnt[SCNT_RX_SZ_64] + + port_cnt[SCNT_RX_PMAC_SZ_64]; + rmon_stats->hist[1] =3D + port_cnt[SCNT_RX_SZ_65_127] + + port_cnt[SCNT_RX_PMAC_SZ_65_127]; + rmon_stats->hist[2] =3D + port_cnt[SCNT_RX_SZ_128_255] + + port_cnt[SCNT_RX_PMAC_SZ_128_255]; + rmon_stats->hist[3] =3D + port_cnt[SCNT_RX_SZ_256_511] + + port_cnt[SCNT_RX_PMAC_SZ_256_511]; + rmon_stats->hist[4] =3D + port_cnt[SCNT_RX_SZ_512_1023] + + port_cnt[SCNT_RX_PMAC_SZ_512_1023]; + rmon_stats->hist[5] =3D + port_cnt[SCNT_RX_SZ_1024_1526] + + port_cnt[SCNT_RX_PMAC_SZ_1024_1526]; + rmon_stats->hist[6] =3D + port_cnt[SCNT_RX_SZ_JUMBO] + + port_cnt[SCNT_RX_PMAC_SZ_JUMBO]; + + rmon_stats->hist_tx[0] =3D + port_cnt[SCNT_TX_SZ_64] + + port_cnt[SCNT_TX_PMAC_SZ_64]; + rmon_stats->hist_tx[1] =3D + port_cnt[SCNT_TX_SZ_65_127] + + port_cnt[SCNT_TX_PMAC_SZ_65_127]; + rmon_stats->hist_tx[2] =3D + port_cnt[SCNT_TX_SZ_128_255] + + port_cnt[SCNT_TX_PMAC_SZ_128_255]; + rmon_stats->hist_tx[3] =3D + port_cnt[SCNT_TX_SZ_256_511] + + port_cnt[SCNT_TX_PMAC_SZ_256_511]; + rmon_stats->hist_tx[4] =3D + port_cnt[SCNT_TX_SZ_512_1023] + + port_cnt[SCNT_TX_PMAC_SZ_512_1023]; + rmon_stats->hist_tx[5] =3D + port_cnt[SCNT_TX_SZ_1024_1526] + + port_cnt[SCNT_TX_PMAC_SZ_1024_1526]; + rmon_stats->hist_tx[6] =3D + port_cnt[SCNT_TX_SZ_JUMBO] + + port_cnt[SCNT_TX_PMAC_SZ_JUMBO]; + + mutex_unlock(&lan9645x->stats->hw_lock); + + *ranges =3D lan9645x_rmon_ranges; +} + +void lan9645x_stats_get_stats64(struct lan9645x *lan9645x, int port, + struct rtnl_link_stats64 *stats) +{ + u64 *port_cnt; + + /* Avoid stats update, as this is called very often by DSA. */ + mutex_lock(&lan9645x->stats->hw_lock); + + port_cnt =3D STAT_COUNTERS(lan9645x, LAN9645X_STAT_PORTS, port); + + stats->rx_bytes =3D port_cnt[SCNT_RX_OCT] + + port_cnt[SCNT_RX_PMAC_OCT]; + + stats->rx_packets =3D port_cnt[SCNT_RX_SHORT] + + port_cnt[SCNT_RX_FRAG] + + port_cnt[SCNT_RX_JABBER] + + port_cnt[SCNT_RX_CRC] + + port_cnt[SCNT_RX_SYMBOL_ERR] + + port_cnt[SCNT_RX_SZ_64] + + port_cnt[SCNT_RX_SZ_65_127] + + port_cnt[SCNT_RX_SZ_128_255] + + port_cnt[SCNT_RX_SZ_256_511] + + port_cnt[SCNT_RX_SZ_512_1023] + + port_cnt[SCNT_RX_SZ_1024_1526] + + port_cnt[SCNT_RX_SZ_JUMBO] + + port_cnt[SCNT_RX_LONG] + + port_cnt[SCNT_RX_PMAC_SHORT] + + port_cnt[SCNT_RX_PMAC_FRAG] + + port_cnt[SCNT_RX_PMAC_JABBER] + + port_cnt[SCNT_RX_PMAC_SZ_64] + + port_cnt[SCNT_RX_PMAC_SZ_65_127] + + port_cnt[SCNT_RX_PMAC_SZ_128_255] + + port_cnt[SCNT_RX_PMAC_SZ_256_511] + + port_cnt[SCNT_RX_PMAC_SZ_512_1023] + + port_cnt[SCNT_RX_PMAC_SZ_1024_1526] + + port_cnt[SCNT_RX_PMAC_SZ_JUMBO]; + + stats->multicast =3D port_cnt[SCNT_RX_MC] + + port_cnt[SCNT_RX_PMAC_MC]; + + stats->rx_errors =3D port_cnt[SCNT_RX_SHORT] + + port_cnt[SCNT_RX_FRAG] + + port_cnt[SCNT_RX_JABBER] + + port_cnt[SCNT_RX_CRC] + + port_cnt[SCNT_RX_SYMBOL_ERR] + + port_cnt[SCNT_RX_LONG] + + port_cnt[SCNT_RX_PMAC_SHORT] + + port_cnt[SCNT_RX_PMAC_FRAG] + + port_cnt[SCNT_RX_PMAC_JABBER] + + port_cnt[SCNT_RX_PMAC_CRC] + + port_cnt[SCNT_RX_PMAC_SYMBOL_ERR] + + port_cnt[SCNT_RX_PMAC_LONG]; + + stats->rx_dropped =3D port_cnt[SCNT_RX_LONG] + + port_cnt[SCNT_DR_LOCAL] + + port_cnt[SCNT_DR_TAIL] + + port_cnt[SCNT_RX_CAT_DROP] + + port_cnt[SCNT_RX_RED_PRIO_0] + + port_cnt[SCNT_RX_RED_PRIO_1] + + port_cnt[SCNT_RX_RED_PRIO_2] + + port_cnt[SCNT_RX_RED_PRIO_3] + + port_cnt[SCNT_RX_RED_PRIO_4] + + port_cnt[SCNT_RX_RED_PRIO_5] + + port_cnt[SCNT_RX_RED_PRIO_6] + + port_cnt[SCNT_RX_RED_PRIO_7]; + + for (int i =3D 0; i < LAN9645X_NUM_TC; i++) { + stats->rx_dropped +=3D port_cnt[SCNT_DR_YELLOW_PRIO_0 + i] + + port_cnt[SCNT_DR_GREEN_PRIO_0 + i]; + } + + stats->tx_bytes =3D port_cnt[SCNT_TX_OCT] + + port_cnt[SCNT_TX_PMAC_OCT]; + + stats->tx_packets =3D port_cnt[SCNT_TX_SZ_64] + + port_cnt[SCNT_TX_SZ_65_127] + + port_cnt[SCNT_TX_SZ_128_255] + + port_cnt[SCNT_TX_SZ_256_511] + + port_cnt[SCNT_TX_SZ_512_1023] + + port_cnt[SCNT_TX_SZ_1024_1526] + + port_cnt[SCNT_TX_SZ_JUMBO] + + port_cnt[SCNT_TX_PMAC_SZ_64] + + port_cnt[SCNT_TX_PMAC_SZ_65_127] + + port_cnt[SCNT_TX_PMAC_SZ_128_255] + + port_cnt[SCNT_TX_PMAC_SZ_256_511] + + port_cnt[SCNT_TX_PMAC_SZ_512_1023] + + port_cnt[SCNT_TX_PMAC_SZ_1024_1526] + + port_cnt[SCNT_TX_PMAC_SZ_JUMBO]; + + stats->tx_dropped =3D port_cnt[SCNT_TX_DROP] + + port_cnt[SCNT_TX_AGED]; + + stats->collisions =3D port_cnt[SCNT_TX_COL]; + + mutex_unlock(&lan9645x->stats->hw_lock); +} + +void lan9645x_stats_get_eth_phy_stats(struct lan9645x *lan9645x, int port, + struct ethtool_eth_phy_stats *phy_stats) +{ + u64 *port_cnt; + + mutex_lock(&lan9645x->stats->hw_lock); + + __lan9645x_stats_view_idx_update(lan9645x, LAN9645X_STAT_PORTS, port); + + port_cnt =3D STAT_COUNTERS(lan9645x, LAN9645X_STAT_PORTS, port); + + switch (phy_stats->src) { + case ETHTOOL_MAC_STATS_SRC_EMAC: + phy_stats->SymbolErrorDuringCarrier =3D + port_cnt[SCNT_RX_SYMBOL_ERR]; + break; + case ETHTOOL_MAC_STATS_SRC_PMAC: + phy_stats->SymbolErrorDuringCarrier =3D + port_cnt[SCNT_RX_PMAC_SYMBOL_ERR]; + break; + default: + break; + } + + mutex_unlock(&lan9645x->stats->hw_lock); +} + +void +lan9645x_stats_get_eth_ctrl_stats(struct lan9645x *lan9645x, int port, + struct ethtool_eth_ctrl_stats *ctrl_stats) +{ + u64 *port_cnt; + + mutex_lock(&lan9645x->stats->hw_lock); + + __lan9645x_stats_view_idx_update(lan9645x, LAN9645X_STAT_PORTS, port); + + port_cnt =3D STAT_COUNTERS(lan9645x, LAN9645X_STAT_PORTS, port); + + switch (ctrl_stats->src) { + case ETHTOOL_MAC_STATS_SRC_EMAC: + ctrl_stats->MACControlFramesReceived =3D + port_cnt[SCNT_RX_CONTROL]; + break; + case ETHTOOL_MAC_STATS_SRC_PMAC: + ctrl_stats->MACControlFramesReceived =3D + port_cnt[SCNT_RX_PMAC_CONTROL]; + break; + default: + break; + } + + mutex_unlock(&lan9645x->stats->hw_lock); +} + +void lan9645x_stats_get_pause_stats(struct lan9645x *lan9645x, int port, + struct ethtool_pause_stats *ps) +{ + u64 *port_cnt; + + mutex_lock(&lan9645x->stats->hw_lock); + + __lan9645x_stats_view_idx_update(lan9645x, LAN9645X_STAT_PORTS, port); + + port_cnt =3D STAT_COUNTERS(lan9645x, LAN9645X_STAT_PORTS, port); + + switch (ps->src) { + case ETHTOOL_MAC_STATS_SRC_EMAC: + ps->tx_pause_frames =3D port_cnt[SCNT_TX_PAUSE]; + ps->rx_pause_frames =3D port_cnt[SCNT_RX_PAUSE]; + break; + case ETHTOOL_MAC_STATS_SRC_PMAC: + ps->tx_pause_frames =3D port_cnt[SCNT_TX_PMAC_PAUSE]; + ps->rx_pause_frames =3D port_cnt[SCNT_RX_PMAC_PAUSE]; + break; + default: + break; + } + + mutex_unlock(&lan9645x->stats->hw_lock); +} + +void lan9645x_stats_get_mm_stats(struct lan9645x *lan9645x, int port, + struct ethtool_mm_stats *stats) +{ + u64 *port_cnt; + + mutex_lock(&lan9645x->stats->hw_lock); + + __lan9645x_stats_view_idx_update(lan9645x, LAN9645X_STAT_PORTS, port); + + port_cnt =3D STAT_COUNTERS(lan9645x, LAN9645X_STAT_PORTS, port); + + stats->MACMergeFrameAssErrorCount =3D port_cnt[SCNT_RX_ASSEMBLY_ERR]; + stats->MACMergeFrameSmdErrorCount =3D port_cnt[SCNT_RX_SMD_ERR]; + stats->MACMergeFrameAssOkCount =3D port_cnt[SCNT_RX_ASSEMBLY_OK]; + stats->MACMergeFragCountRx =3D port_cnt[SCNT_RX_MERGE_FRAG]; + stats->MACMergeFragCountTx =3D port_cnt[SCNT_TX_MERGE_FRAG]; + stats->MACMergeHoldCount =3D port_cnt[SCNT_TX_MM_HOLD]; + + mutex_unlock(&lan9645x->stats->hw_lock); +} + +void lan9645x_stats_clear_counters(struct lan9645x *lan9645x, + enum lan9645x_view_stat_type type, int idx) +{ + struct lan9645x_view_stats *vstats =3D + lan9645x_get_vstats(lan9645x, type); + u64 *idx_grp; + int cntr; + u32 sel; + + switch (type) { + case LAN9645X_STAT_PORTS: + /* Drop, TX and RX counters */ + sel =3D BIT(2) | BIT(1) | BIT(0); + break; + case LAN9645X_STAT_ISDX: + /* ISDX and FRER seq gen */ + sel =3D BIT(5) | BIT(3); + break; + case LAN9645X_STAT_ESDX: + /* ESDX */ + sel =3D BIT(6); + break; + case LAN9645X_STAT_SFID: + /* Stream filter */ + sel =3D BIT(4); + break; + default: + return; + } + + mutex_lock(&lan9645x->stats->hw_lock); + + lan_wr(SYS_STAT_CFG_STAT_CLEAR_SHOT_SET(sel) | + SYS_STAT_CFG_STAT_VIEW_SET(idx), + lan9645x, SYS_STAT_CFG); + + idx_grp =3D STATS_INDEX(vstats, idx); + for (cntr =3D 0; cntr < vstats->num_cnts; cntr++) + idx_grp[cntr] =3D 0; + + mutex_unlock(&lan9645x->stats->hw_lock); +} + +static void lan9645x_check_stats_work(struct work_struct *work) +{ + struct delayed_work *del_work =3D to_delayed_work(work); + struct lan9645x_stats *stats; + + stats =3D container_of(del_work, struct lan9645x_stats, work); + + lan9645x_stats_update(stats->lan9645x); + + queue_delayed_work(stats->queue, &stats->work, + LAN9645X_STATS_CHECK_DELAY); +} + +static int lan9645x_stats_debugfs_show(struct seq_file *m, void *unused) +{ + struct lan9645x_view_stats *vstats =3D m->private; + int idx, cntr; + size_t total; + u64 *snap; + + total =3D vstats->num_cnts * vstats->num_indexes; + + /* Snapshot counters under lock to avoid holding hw_lock during + * slow seq_printf output. + */ + snap =3D kmalloc_array(total, sizeof(u64), GFP_KERNEL); + if (!snap) + return -ENOMEM; + + mutex_lock(&vstats->stats->hw_lock); + memcpy(snap, vstats->cnts, total * sizeof(u64)); + mutex_unlock(&vstats->stats->hw_lock); + + for (idx =3D 0; idx < vstats->num_indexes; idx++) { + for (cntr =3D 0; cntr < vstats->num_cnts; cntr++) { + seq_printf(m, "%s_%d_%-*s %llu\n", vstats->name, idx, + 30, vstats->layout[cntr].name, + snap[vstats->num_cnts * idx + cntr]); + } + } + + kfree(snap); + return 0; +} +DEFINE_SHOW_ATTRIBUTE(lan9645x_stats_debugfs); + +static void lan9645x_stats_debugfs(struct lan9645x *lan9645x, + struct dentry *parent) +{ + struct lan9645x_stats *stats =3D lan9645x->stats; + struct dentry *dir; + int i; + + dir =3D debugfs_create_dir("stats", parent); + if (PTR_ERR_OR_ZERO(dir)) + return; + + for (i =3D 0; i < ARRAY_SIZE(stats->view); i++) + debugfs_create_file(stats->view[i].name, 0444, dir, + &stats->view[i], + &lan9645x_stats_debugfs_fops); +} + +static int lan9645x_view_stat_init(struct lan9645x *lan9645x, + struct lan9645x_view_stats *vstat, + const struct lan9645x_view_stats *cfg) +{ + size_t total =3D cfg->num_cnts * cfg->num_indexes; + + memcpy(vstat, cfg, sizeof(*cfg)); + + vstat->cnts =3D devm_kcalloc(lan9645x->dev, total, sizeof(u64), + GFP_KERNEL); + if (!vstat->cnts) + return -ENOMEM; + + vstat->buf =3D devm_kcalloc(lan9645x->dev, total, sizeof(u32), + GFP_KERNEL); + if (!vstat->buf) + return -ENOMEM; + + vstat->stats =3D lan9645x->stats; + + return 0; +} + +int lan9645x_stats_init(struct lan9645x *lan9645x) +{ + const struct lan9645x_view_stats *vs; + struct lan9645x_stats *stats; + int err, i; + + lan9645x->stats =3D devm_kzalloc(lan9645x->dev, sizeof(*stats), + GFP_KERNEL); + if (!lan9645x->stats) + return -ENOMEM; + + stats =3D lan9645x->stats; + stats->lan9645x =3D lan9645x; + + mutex_init(&stats->hw_lock); + stats->queue =3D alloc_ordered_workqueue("lan9645x-stats", 0); + if (!stats->queue) + return -ENOMEM; + + for (i =3D 0; i < ARRAY_SIZE(lan9645x_view_stat_cfgs); i++) { + vs =3D &lan9645x_view_stat_cfgs[i]; + + if (!vs->num_cnts) + continue; + + err =3D lan9645x_view_stat_init(lan9645x, &stats->view[vs->type], + vs); + if (err) + return err; + } + + INIT_DELAYED_WORK(&stats->work, lan9645x_check_stats_work); + queue_delayed_work(stats->queue, &stats->work, + LAN9645X_STATS_CHECK_DELAY); + + lan9645x_stats_debugfs(lan9645x, lan9645x->debugfs_root); + + return 0; +} + +void lan9645x_stats_deinit(struct lan9645x *lan9645x) +{ + cancel_delayed_work_sync(&lan9645x->stats->work); + destroy_workqueue(lan9645x->stats->queue); + mutex_destroy(&lan9645x->stats->hw_lock); + lan9645x->stats->queue =3D NULL; +} diff --git a/drivers/net/dsa/microchip/lan9645x/lan9645x_stats.h b/drivers/= net/dsa/microchip/lan9645x/lan9645x_stats.h new file mode 100644 index 000000000000..0bb1e1140cc7 --- /dev/null +++ b/drivers/net/dsa/microchip/lan9645x/lan9645x_stats.h @@ -0,0 +1,288 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (C) 2026 Microchip Technology Inc. + */ + +#ifndef _LAN9645X_STATS_H_ +#define _LAN9645X_STATS_H_ + +#include "lan9645x_main.h" + +#define STATS_INDEX(vstats, idx) (&(vstats)->cnts[(vstats)->num_cnts * (id= x)]) + +#define STAT_COUNTERS(lan9645x, type, idx) \ + STATS_INDEX(lan9645x_get_vstats(lan9645x, type), idx) + +/* Counter indices into stat layout structs */ +#define SCNT_FRER_SID_IN_PKT 0 +#define SCNT_ISDX_GREEN_OCT 1 +#define SCNT_ISDX_GREEN_PKT 2 +#define SCNT_ISDX_YELLOW_OCT 3 +#define SCNT_ISDX_YELLOW_PKT 4 +#define SCNT_ISDX_RED_OCT 5 +#define SCNT_ISDX_RED_PKT 6 +#define SCNT_ISDX_DROP_GREEN_OCT 7 +#define SCNT_ISDX_DROP_GREEN_PKT 8 +#define SCNT_ISDX_DROP_YELLOW_OCT 9 +#define SCNT_ISDX_DROP_YELLOW_PKT 10 + +#define SCNT_SF_MATCHING_FRAMES_COUNT 0 +#define SCNT_SF_NOT_PASSING_FRAMES_COUNT 1 +#define SCNT_SF_NOT_PASSING_SDU_COUNT 2 +#define SCNT_SF_RED_FRAMES_COUNT 3 +#define SCNT_SF_STREAM_BLOCK_COUNT 4 + +#define SCNT_ESDX_GREEN_OCT 0 +#define SCNT_ESDX_GREEN_PKT 1 +#define SCNT_ESDX_YELLOW_OCT 2 +#define SCNT_ESDX_YELLOW_PKT 3 + +#define SCNT_RX_OCT 0 +#define SCNT_RX_UC 1 +#define SCNT_RX_MC 2 +#define SCNT_RX_BC 3 +#define SCNT_RX_SHORT 4 +#define SCNT_RX_FRAG 5 +#define SCNT_RX_JABBER 6 +#define SCNT_RX_CRC 7 +#define SCNT_RX_SYMBOL_ERR 8 +#define SCNT_RX_SZ_64 9 +#define SCNT_RX_SZ_65_127 10 +#define SCNT_RX_SZ_128_255 11 +#define SCNT_RX_SZ_256_511 12 +#define SCNT_RX_SZ_512_1023 13 +#define SCNT_RX_SZ_1024_1526 14 +#define SCNT_RX_SZ_JUMBO 15 +#define SCNT_RX_PAUSE 16 +#define SCNT_RX_CONTROL 17 +#define SCNT_RX_LONG 18 +#define SCNT_RX_CAT_DROP 19 +#define SCNT_RX_RED_PRIO_0 20 +#define SCNT_RX_RED_PRIO_1 21 +#define SCNT_RX_RED_PRIO_2 22 +#define SCNT_RX_RED_PRIO_3 23 +#define SCNT_RX_RED_PRIO_4 24 +#define SCNT_RX_RED_PRIO_5 25 +#define SCNT_RX_RED_PRIO_6 26 +#define SCNT_RX_RED_PRIO_7 27 +#define SCNT_RX_YELLOW_PRIO_0 28 +#define SCNT_RX_YELLOW_PRIO_1 29 +#define SCNT_RX_YELLOW_PRIO_2 30 +#define SCNT_RX_YELLOW_PRIO_3 31 +#define SCNT_RX_YELLOW_PRIO_4 32 +#define SCNT_RX_YELLOW_PRIO_5 33 +#define SCNT_RX_YELLOW_PRIO_6 34 +#define SCNT_RX_YELLOW_PRIO_7 35 +#define SCNT_RX_GREEN_PRIO_0 36 +#define SCNT_RX_GREEN_PRIO_1 37 +#define SCNT_RX_GREEN_PRIO_2 38 +#define SCNT_RX_GREEN_PRIO_3 39 +#define SCNT_RX_GREEN_PRIO_4 40 +#define SCNT_RX_GREEN_PRIO_5 41 +#define SCNT_RX_GREEN_PRIO_6 42 +#define SCNT_RX_GREEN_PRIO_7 43 +#define SCNT_RX_ASSEMBLY_ERR 44 +#define SCNT_RX_SMD_ERR 45 +#define SCNT_RX_ASSEMBLY_OK 46 +#define SCNT_RX_MERGE_FRAG 47 +#define SCNT_RX_PMAC_OCT 48 +#define SCNT_RX_PMAC_UC 49 +#define SCNT_RX_PMAC_MC 50 +#define SCNT_RX_PMAC_BC 51 +#define SCNT_RX_PMAC_SHORT 52 +#define SCNT_RX_PMAC_FRAG 53 +#define SCNT_RX_PMAC_JABBER 54 +#define SCNT_RX_PMAC_CRC 55 +#define SCNT_RX_PMAC_SYMBOL_ERR 56 +#define SCNT_RX_PMAC_SZ_64 57 +#define SCNT_RX_PMAC_SZ_65_127 58 +#define SCNT_RX_PMAC_SZ_128_255 59 +#define SCNT_RX_PMAC_SZ_256_511 60 +#define SCNT_RX_PMAC_SZ_512_1023 61 +#define SCNT_RX_PMAC_SZ_1024_1526 62 +#define SCNT_RX_PMAC_SZ_JUMBO 63 +#define SCNT_RX_PMAC_PAUSE 64 +#define SCNT_RX_PMAC_CONTROL 65 +#define SCNT_RX_PMAC_LONG 66 +#define SCNT_TX_OCT 67 +#define SCNT_TX_UC 68 +#define SCNT_TX_MC 69 +#define SCNT_TX_BC 70 +#define SCNT_TX_COL 71 +#define SCNT_TX_DROP 72 +#define SCNT_TX_PAUSE 73 +#define SCNT_TX_SZ_64 74 +#define SCNT_TX_SZ_65_127 75 +#define SCNT_TX_SZ_128_255 76 +#define SCNT_TX_SZ_256_511 77 +#define SCNT_TX_SZ_512_1023 78 +#define SCNT_TX_SZ_1024_1526 79 +#define SCNT_TX_SZ_JUMBO 80 +#define SCNT_TX_YELLOW_PRIO_0 81 +#define SCNT_TX_YELLOW_PRIO_1 82 +#define SCNT_TX_YELLOW_PRIO_2 83 +#define SCNT_TX_YELLOW_PRIO_3 84 +#define SCNT_TX_YELLOW_PRIO_4 85 +#define SCNT_TX_YELLOW_PRIO_5 86 +#define SCNT_TX_YELLOW_PRIO_6 87 +#define SCNT_TX_YELLOW_PRIO_7 88 +#define SCNT_TX_GREEN_PRIO_0 89 +#define SCNT_TX_GREEN_PRIO_1 90 +#define SCNT_TX_GREEN_PRIO_2 91 +#define SCNT_TX_GREEN_PRIO_3 92 +#define SCNT_TX_GREEN_PRIO_4 93 +#define SCNT_TX_GREEN_PRIO_5 94 +#define SCNT_TX_GREEN_PRIO_6 95 +#define SCNT_TX_GREEN_PRIO_7 96 +#define SCNT_TX_AGED 97 +#define SCNT_TX_LLCT 98 +#define SCNT_TX_CT 99 +#define SCNT_TX_BUFDROP 100 +#define SCNT_TX_MM_HOLD 101 +#define SCNT_TX_MERGE_FRAG 102 +#define SCNT_TX_PMAC_OCT 103 +#define SCNT_TX_PMAC_UC 104 +#define SCNT_TX_PMAC_MC 105 +#define SCNT_TX_PMAC_BC 106 +#define SCNT_TX_PMAC_PAUSE 107 +#define SCNT_TX_PMAC_SZ_64 108 +#define SCNT_TX_PMAC_SZ_65_127 109 +#define SCNT_TX_PMAC_SZ_128_255 110 +#define SCNT_TX_PMAC_SZ_256_511 111 +#define SCNT_TX_PMAC_SZ_512_1023 112 +#define SCNT_TX_PMAC_SZ_1024_1526 113 +#define SCNT_TX_PMAC_SZ_JUMBO 114 +#define SCNT_DR_LOCAL 115 +#define SCNT_DR_TAIL 116 +#define SCNT_DR_YELLOW_PRIO_0 117 +#define SCNT_DR_YELLOW_PRIO_1 118 +#define SCNT_DR_YELLOW_PRIO_2 119 +#define SCNT_DR_YELLOW_PRIO_3 120 +#define SCNT_DR_YELLOW_PRIO_4 121 +#define SCNT_DR_YELLOW_PRIO_5 122 +#define SCNT_DR_YELLOW_PRIO_6 123 +#define SCNT_DR_YELLOW_PRIO_7 124 +#define SCNT_DR_GREEN_PRIO_0 125 +#define SCNT_DR_GREEN_PRIO_1 126 +#define SCNT_DR_GREEN_PRIO_2 127 +#define SCNT_DR_GREEN_PRIO_3 128 +#define SCNT_DR_GREEN_PRIO_4 129 +#define SCNT_DR_GREEN_PRIO_5 130 +#define SCNT_DR_GREEN_PRIO_6 131 +#define SCNT_DR_GREEN_PRIO_7 132 + +struct lan9645x_stat_layout { + u32 offset; + char name[ETH_GSTRING_LEN]; +}; + +enum lan9645x_view_stat_type { + LAN9645X_STAT_PORTS =3D 0, + LAN9645X_STAT_ISDX, + LAN9645X_STAT_ESDX, + LAN9645X_STAT_SFID, + + LAN9645X_STAT_NUM, +}; + +struct lan9645x_stat_region { + u32 base_offset; + u32 cnt; + u32 cnts_base_idx; +}; + +/* Counters are organized by indices/views such as + * + * - physical ports + * - isdx + * - esdx + * - frer + * - sfid + * + * Each view contains regions, which is a linear address range of related + * stats. I.e. the ports index has RX, TX and Drop regions. + * + * + * and you have a given counter replicated per index. + */ +struct lan9645x_view_stats { + /* Individual counter descriptions in this view */ + const struct lan9645x_stat_layout *layout; + /* Region description for this view, used for bulk reading */ + const struct lan9645x_stat_region *regions; + struct lan9645x_stats *stats; + char name[16]; + /* 64bit software counters with the same addr layout hw */ + u64 *cnts; + /* Buffer for bulk reading counter regions from hw */ + u32 *buf; + /* Number of counters per index in view */ + u32 num_cnts; + /* Number of indexes in view */ + u32 num_indexes; + /* Number of counter regions with counters at sequential addresses */ + size_t num_regions; + enum lan9645x_view_stat_type type; +}; + +struct lan9645x_stats { + struct lan9645x *lan9645x; + struct mutex hw_lock; /* lock r/w to stat registers */ + struct delayed_work work; + struct workqueue_struct *queue; + + struct lan9645x_view_stats view[LAN9645X_STAT_NUM]; +}; + +static inline struct lan9645x_view_stats * +lan9645x_get_vstats(struct lan9645x *lan9645x, + enum lan9645x_view_stat_type type) +{ + if (WARN_ON(!(type < LAN9645X_STAT_NUM))) + return NULL; + + return &lan9645x->stats->view[type]; +} + +/* Add a possibly wrapping 32 bit value to a 64 bit counter */ +static inline void lan9645x_stats_add_cnt(u64 *cnt, u32 val) +{ + if (val < (*cnt & U32_MAX)) + *cnt +=3D (u64)1 << 32; /* value has wrapped */ + + *cnt =3D (*cnt & ~(u64)U32_MAX) + val; +} + +void lan9645x_stats_clear_counters(struct lan9645x *lan9645x, + enum lan9645x_view_stat_type type, int idx); +int lan9645x_stats_init(struct lan9645x *lan9645x); +void lan9645x_stats_deinit(struct lan9645x *lan9645x); +void lan9645x_stats_get_strings(struct lan9645x *lan9645x, int port, + u32 stringset, u8 *data); +int lan9645x_stats_get_sset_count(struct lan9645x *lan9645x, int port, + int sset); +void lan9645x_stats_get_ethtool_stats(struct lan9645x *lan9645x, int port, + uint64_t *data); +void lan9645x_stats_get_eth_mac_stats(struct lan9645x *lan9645x, int port, + struct ethtool_eth_mac_stats *mac_stats); +void +lan9645x_stats_get_rmon_stats(struct lan9645x *lan9645x, int port, + struct ethtool_rmon_stats *rmon_stats, + const struct ethtool_rmon_hist_range **ranges); +void lan9645x_stats_get_stats64(struct lan9645x *lan9645x, int port, + struct rtnl_link_stats64 *s); +void lan9645x_stats_get_mm_stats(struct lan9645x *lan9645x, int port, + struct ethtool_mm_stats *stats); +void lan9645x_stats_get_pause_stats(struct lan9645x *lan9645x, int port, + struct ethtool_pause_stats *ps); +void +lan9645x_stats_get_eth_ctrl_stats(struct lan9645x *lan9645x, int port, + struct ethtool_eth_ctrl_stats *ctrl_stats); +void lan9645x_stats_get_eth_phy_stats(struct lan9645x *lan9645x, int port, + struct ethtool_eth_phy_stats *phy_stats); +void lan9645x_stats_view_update(struct lan9645x *lan9645x, + enum lan9645x_view_stat_type view_type); +void lan9645x_stats_view_idx_update(struct lan9645x *lan9645x, + enum lan9645x_view_stat_type vtype, + int idx); + +#endif --=20 2.52.0