From nobody Tue Mar 3 05:25:39 2026 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F81E379EC9; Mon, 2 Mar 2026 19:11:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.120.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478670; cv=none; b=G375beU0fZOKXuaQ8q4UsP7KNK/ui8UZ+ATU63hJDo+QNeEyelCN3ybsmulg7HycX+oz48bPG5gP5cOg4G7La8GxKfWWpedp0oSO2kn5KLyLg4iCgJgpP/jd33jO0SJrRyk61g+jG7Nhxub9qk9xTQ7rSpvwVqRxN4uFJb4vIZE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478670; c=relaxed/simple; bh=AJeYnQRs15OIr5dOs2oawchpIH1qHwZ2sibnkoH1KYw=; h=From:To:Cc:Date:Message-ID:In-Reply-To:References:MIME-Version: Subject; b=grYj1PPGmqsvL0pRsHWbbRT8HmwxMa1XwGg5Zms057keJO96HFzLOlQgCURydEsuvUtorT/RqhVOFGAslHQ97PNdfCWVrK3Jw83f16LkUA3YHWSR++hBMJS8ejn6uy61iSzmPqUvO49NpuCTOA9Ok9Sg1yDUi3aArEGgSXzPVQs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com; spf=pass smtp.mailfrom=hugovil.com; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b=Xyh1nGY4; arc=none smtp.client-ip=162.243.120.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=hugovil.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b="Xyh1nGY4" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Cc:To :From:subject:date:message-id:reply-to; bh=2cWfVNFiBN37y0sWn1ukQg9gyqiW7cmKNiCC/42PjbU=; b=Xyh1nGY4YcadeISr/vbIs4eqDj SpKlbEzdQayqOduLQ+qxPtdFNF7MjMgIS9dEX/zhvSd3h00YrsyXOUIfvQ2NCYpqTGHh9Gt6Mdad5 lw+vIKLBTUQBicqwQmaq8xo5NlxDnufaAiec+hMi7Pen8UrnJAxk4UzK45MOcFMDHhls=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:59962 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1vx8fI-0007Wl-H2; Mon, 02 Mar 2026 14:10:49 -0500 From: Hugo Villeneuve To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, shawnguo@kernel.org, laurent.pinchart+renesas@ideasonboard.com, antonin.godard@bootlin.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, hugo@hugovil.com, Hugo Villeneuve Date: Mon, 2 Mar 2026 14:03:43 -0500 Message-ID: <20260302190953.669325-8-hugo@hugovil.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302190953.669325-1-hugo@hugovil.com> References: <20260302190953.669325-1-hugo@hugovil.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: [PATCH 07/14] ARM: dts: imx6ul-var-som-concerto: Factor out common parts for all CPU variants X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Export common parts to the Variscite VAR-SOM-6UL dtsi so that they can be reused on other boards. This will simplify adding future dedicated device tree files for each CPU variant. Add i2c1 pinctrl to var-som dtsi pinmux, so that it can be reused by other boards. Reorder pinctrl_gpio_leds to respect alphabetical order. Signed-off-by: Hugo Villeneuve --- arch/arm/boot/dts/nxp/imx/Makefile | 1 + .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 7 + ...ts =3D> imx6ul-var-som-concerto-common.dtsi} | 17 +- .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 312 +----------------- .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 17 + 5 files changed, 33 insertions(+), 321 deletions(-) copy arch/arm/boot/dts/nxp/imx/{imx6ul-var-som-concerto.dts =3D> imx6ul-va= r-som-concerto-common.dtsi} (95%) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx= /Makefile index de4142e8f3ce8..bc534d0fb1412 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -376,6 +376,7 @@ dtb-$(CONFIG_SOC_IMX6UL) +=3D \ imx6ull-tarragon-slavext.dtb \ imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ull-tqma6ull2l-mba6ulx.dtb \ + imx6ull-var-som-concerto.dtb \ imx6ull-uti260b.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/ar= m/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index 2072e8ba4d469..22b0c4e0725a5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -104,6 +104,13 @@ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Ena= ble */ >; }; =20 + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + pinctrl_sai2: sai2grp { fsl,pins =3D < MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/a= rm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi similarity index 95% copy from arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts copy to arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index d16e75164fd18..10a23ae104359 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -1,19 +1,15 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL - * Variscite SoM mounted on it + * Variscite SoM mounted on it, for all CPU variants. * * Copyright 2019 Variscite Ltd. * Copyright 2025 Bootlin */ =20 -#include "imx6ul-var-som.dtsi" #include =20 / { - model =3D "Variscite VAR-SOM-6UL Concerto Board"; - compatible =3D "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fs= l,imx6ul"; - chosen { stdout-path =3D &uart1; }; @@ -144,22 +140,15 @@ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059 >; }; =20 - pinctrl_gpio_leds: gpio-ledsgrp { - fsl,pins =3D < - MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ - >; - }; - pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp { fsl,pins =3D < MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 >; }; =20 - pinctrl_i2c1: i2c1grp { + pinctrl_gpio_leds: gpio-ledsgrp { fsl,pins =3D < - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ >; }; =20 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/a= rm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index d16e75164fd18..11b45f105b7ad 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -1,320 +1,18 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL - * Variscite SoM mounted on it + * Variscite SoM mounted on it (6UL CPU variant). * * Copyright 2019 Variscite Ltd. * Copyright 2025 Bootlin */ =20 +/dts-v1/; + #include "imx6ul-var-som.dtsi" -#include +#include "imx6ul-var-som-concerto-common.dtsi" =20 / { - model =3D "Variscite VAR-SOM-6UL Concerto Board"; + model =3D "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; compatible =3D "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fs= l,imx6ul"; - - chosen { - stdout-path =3D &uart1; - }; - - gpio-keys { - compatible =3D "gpio-keys"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>; - - key-back { - gpios =3D <&gpio4 14 GPIO_ACTIVE_LOW>; - linux,code =3D ; - }; - - key-wakeup { - gpios =3D <&gpio5 8 GPIO_ACTIVE_LOW>; - linux,code =3D ; - wakeup-source; - }; - }; - - leds { - compatible =3D "gpio-leds"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_gpio_leds>; - - led-0 { - function =3D LED_FUNCTION_STATUS; - color =3D ; - label =3D "gpled2"; - gpios =3D <&gpio1 25 GPIO_ACTIVE_HIGH>; - linux,default-trigger =3D "heartbeat"; - }; - }; -}; - -&can1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_flexcan1>; - status =3D "okay"; -}; - -&fec1 { - status =3D "disabled"; -}; - -&fec2 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_md= io>; - phy-mode =3D "rmii"; - phy-handle =3D <ðphy1>; - status =3D "okay"; - - mdio { - #address-cells =3D <1>; - #size-cells =3D <0>; - - ethphy1: ethernet-phy@3 { - compatible =3D "ethernet-phy-ieee802.3-c22"; - reg =3D <3>; - clocks =3D <&rmii_ref_clk>; - clock-names =3D "rmii-ref"; - reset-gpios =3D <&gpio5 5 GPIO_ACTIVE_LOW>; - reset-assert-us =3D <100000>; - micrel,led-mode =3D <0>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - -&i2c1 { - clock-frequency =3D <100000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_i2c1>; - status =3D "okay"; - - rtc@68 { - /* - * To actually use this interrupt - * connect pins J14.8 & J14.10 on the Concerto-Board. - */ - compatible =3D "dallas,ds1337"; - reg =3D <0x68>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_rtc>; - interrupt-parent =3D <&gpio1>; - interrupts =3D <10 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&iomuxc { - pinctrl_enet2: enet2grp { - fsl,pins =3D < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_enet2_gpio: enet2-gpiogrp { - fsl,pins =3D < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ - >; - }; - - pinctrl_enet2_mdio: enet2-mdiogrp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins =3D < - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_gpio_key_back: gpio-key-backgrp { - fsl,pins =3D < - MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059 - >; - }; - - pinctrl_gpio_leds: gpio-ledsgrp { - fsl,pins =3D < - MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ - >; - }; - - pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp { - fsl,pins =3D < - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins =3D < - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins =3D < - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins =3D < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins =3D < - MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins =3D < - MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins =3D < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins =3D < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins =3D < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1-gpiogrp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 - >; - }; -}; - -&pwm4 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_pwm4>; - status =3D "okay"; -}; - -&snvs_pwrkey { - status =3D "disabled"; -}; - -&snvs_rtc { - status =3D "disabled"; -}; - -&tsc { - /* - * Conflics with wdog1 ext-reset-output & SD CD pins, - * so we keep it disabled by default. - */ - status =3D "disabled"; -}; - -/* Console UART */ -&uart1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_uart1>; - status =3D "okay"; -}; - -/* ttymxc4 UART */ -&uart5 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_uart5>; - uart-has-rtscts; - status =3D "okay"; -}; - -&usbotg1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_usb_otg1_id>; - dr_mode =3D "otg"; - disable-over-current; - srp-disable; - hnp-disable; - adp-disable; - status =3D "okay"; -}; - -&usbotg2 { - dr_mode =3D "host"; - disable-over-current; - status =3D "okay"; -}; - -&usdhc1 { - pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; - pinctrl-0 =3D <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; - cd-gpios =3D <&gpio1 0 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status =3D "okay"; -}; - -&wdog1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_wdog>; - /* - * To actually use ext-reset-output - * connect pins J17.3 & J17.8 on the Concerto-Board - */ - fsl,ext-reset-output; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/= arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts new file mode 100644 index 0000000000000..7c601af2657d7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL + * Variscite SoM mounted on it (6ULL CPU variant). + * + * Copyright 2026 Dimonoff + */ + +/dts-v1/; + +#include "imx6ull-var-som.dtsi" +#include "imx6ul-var-som-concerto-common.dtsi" + +/ { + model =3D "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; + compatible =3D "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "= fsl,imx6ull"; +}; --=20 2.47.3