From nobody Tue Mar 3 05:27:01 2026 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB85F3E714C; Mon, 2 Mar 2026 19:11:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.120.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478672; cv=none; b=PnA8vQBDzUlHtpLg87gPuJr/WRG85Tww3aX5dOUCC7mRuUXpPKLyeRpBGxhRsMYTHvx4X/inPBH/mqxNyDTEVSVY6rlyLl+Qa+Qk4F8T4crkgETfNyB1iR879mPV3L42geEiVApUEPbdDoTrvH8P1a4KPMieMUTj1DfZ7qTU3KM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478672; c=relaxed/simple; bh=pNoC7LhNrjxWXAcngz7cuC+o+ltMtibyFKXDuWSFghA=; h=From:To:Cc:Date:Message-ID:In-Reply-To:References:MIME-Version: Subject; b=QSTDRjZqR0PJftJntJAaXrSUnV+135KecWd4bJV08eBkDNIMNpBxjWjMPjnrYJO2xFnpZNLOpK5HYLd2FYkNd2izAkkSzHUlO89W8axXD5jknG93yA8t5mM53sy/SGx+WcoXxRFz+i/itHIxDG2KTSMSTi/1C4DaVk/mcsttfq8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com; spf=pass smtp.mailfrom=hugovil.com; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b=ALUJyLsn; arc=none smtp.client-ip=162.243.120.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=hugovil.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b="ALUJyLsn" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Cc:To :From:subject:date:message-id:reply-to; bh=n+/U1OQdRhUjyjZX2Ky+plYvPnlufBJttc/pgaNi31I=; b=ALUJyLsnnkdVNkrhRzXvcAp41O n5OaymUL6JC2JQSjCnbYCdsyOSexO3YOrWQucRCAU3EIpNtGqCOME96xB1H62NEa6KE/Bs8mlw3dY p6SO0a52DRnRVs1SAaiTvlfEWDX62RW+5HX77+34ZhSupJmeoforrL1X3Yw1QxA1Zsys=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:59962 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1vx8fU-0007Wl-1P; Mon, 02 Mar 2026 14:11:00 -0500 From: Hugo Villeneuve To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, shawnguo@kernel.org, laurent.pinchart+renesas@ideasonboard.com, antonin.godard@bootlin.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, hugo@hugovil.com, Hugo Villeneuve Date: Mon, 2 Mar 2026 14:03:47 -0500 Message-ID: <20260302190953.669325-12-hugo@hugovil.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302190953.669325-1-hugo@hugovil.com> References: <20260302190953.669325-1-hugo@hugovil.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: [PATCH 11/14] ARM: dts: imx6ul-var-som: add support for EC configuration option (ENET1) X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve ENET1 is currently disabled and not supported/working on the concerto EVK. Add support for this optional configuration in a separate DTSI include file, so that it can be selectively enabled/disabled. Signed-off-by: Hugo Villeneuve --- In order for this to work, imx6ul-var-som-enet2.dtsi must be included first, and thus enabled, even if not used. Maybe there is a better way to support both independantly, but I'm not sure how. --- .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 50 ------------------- .../imx/imx6ul-var-som-concerto-common.dtsi | 4 -- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-enet1.dtsi | 44 ++++++++++++++++ .../dts/nxp/imx/imx6ul-var-som-enet2.dtsi | 11 ++++ arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 6 +++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 1 + .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 6 +++ 8 files changed, 69 insertions(+), 54 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/ar= m/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index af9b92f7709b4..70d19eccddb4c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -44,57 +44,7 @@ &clks { assigned-clock-rates =3D <786432000>; }; =20 -&fec1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_md= io>; - phy-mode =3D "rmii"; - phy-handle =3D <ðphy0>; - status =3D "okay"; - - mdio { - #address-cells =3D <1>; - #size-cells =3D <0>; - - ethphy0: ethernet-phy@1 { - compatible =3D "ethernet-phy-ieee802.3-c22"; - reg =3D <1>; - clocks =3D <&rmii_ref_clk>; - clock-names =3D "rmii-ref"; - reset-gpios =3D <&gpio5 0 GPIO_ACTIVE_LOW>; - reset-assert-us =3D <100000>; - micrel,led-mode =3D <1>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - &iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins =3D < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet1_gpio: enet1-gpiogrp { - fsl,pins =3D < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ - >; - }; - - pinctrl_enet1_mdio: enet1-mdiogrp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - >; - }; - pinctrl_i2c1: i2c1grp { fsl,pins =3D < MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi = b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index 53cf801f39fcd..107b1d0fe7827 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -52,10 +52,6 @@ &can1 { status =3D "okay"; }; =20 -&fec1 { - status =3D "disabled"; -}; - &i2c1 { clock-frequency =3D <100000>; pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts index 3905171b47b32..b5e6a3306e1cd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-enet1.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi b/arch/arm= /boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi new file mode 100644 index 0000000000000..6b1e34347bec7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Ethernet ENET1 support for Variscite VAR-SOM-6UL module with + * the EC configuration option ((ethernet PHY assembled on SOM). + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_enet1>, <&pinctrl_enet1_gpio>; + phy-mode =3D "rmii"; + phy-handle =3D <ðphy0>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins =3D < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; +}; + +&mdio_enet2 { + ethphy0: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + clocks =3D <&rmii_ref_clk>; + clock-names =3D "rmii-ref"; + reset-gpios =3D <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <100000>; + micrel,led-mode =3D <1>; + micrel,rmii-reference-clock-select-25-mhz; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi b/arch/arm= /boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi index 334ed3bbe02ce..b29fcdc079e37 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi @@ -26,6 +26,17 @@ mdio_enet2: mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 + ethphy0: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + clocks =3D <&rmii_ref_clk>; + clock-names =3D "rmii-ref"; + reset-gpios =3D <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <100000>; + micrel,led-mode =3D <1>; + micrel,rmii-reference-clock-select-25-mhz; + }; + ethphy1: ethernet-phy@3 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <3>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/= dts/nxp/imx/imx6ul-var-som.dtsi index b4e6a9316dd81..feea24c0e0683 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -29,4 +29,10 @@ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WI= FI_PWR 5G) */ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ >; }; + + pinctrl_enet1_gpio: enet1-gpiogrp { + fsl,pins =3D < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ + >; + }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/= arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts index 89b6032203a28..86f558c76fb3e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-enet1.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot= /dts/nxp/imx/imx6ull-var-som.dtsi index 3067ff6a1bc74..f120b1dca75ce 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi @@ -27,4 +27,10 @@ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (W= IFI_PWR 5G) */ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ >; }; + + pinctrl_enet1_gpio: enet1-gpiogrp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ + >; + }; }; --=20 2.47.3