From nobody Tue Mar 3 03:38:36 2026 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24193359A8A; Mon, 2 Mar 2026 19:11:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.120.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478664; cv=none; b=JiQLPz4qd8wNWC5A4zXqokNDgdmx4O9Nm5Z24gn6eD+79M9aXclRdfcusdAMOmC5WEqcGDHP63Puk2niFCNQ2CWr2Ky1FoL+3A5bLXZ9pecjd7Ttt1F5XSxklyhxqIQzwjahP7WxLIoZqxgHNzxwadIyd/3C3jy63RdVR2K8bIw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478664; c=relaxed/simple; bh=V8u3tYgw2th/H747Fo1Rwb/Zmj5VstI+Lo5MOIYEyoM=; h=From:To:Cc:Date:Message-ID:In-Reply-To:References:MIME-Version: Subject; b=UywRz9z7DcttbJf7bew2g2MzuSMwCimM0jv8PEyCrJkVBK5gCOhFn/H/N3Tt9D/l1vKg8+6oMSf+TmQNzwh8q7jHfj6ustSPrg+aqRASU63F4k0IjJQOpLPzIK7jRLkv8R3C01Y69G6tKI2TONpVK7YgZ0BbPg2f11L/zYAEUnA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com; spf=pass smtp.mailfrom=hugovil.com; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b=ZXHwQFf7; arc=none smtp.client-ip=162.243.120.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=hugovil.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b="ZXHwQFf7" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Cc:To :From:subject:date:message-id:reply-to; bh=IGz99reFYT/+DoaMSCYXt6fgEmntGIKGtzdIEBnIkNk=; b=ZXHwQFf7VaeR0eY/uwhlW0t05u REMVN8NVMJboT/3KKpWhryca+FHMZil27faLxAQjYRm/XixQAvFGf9I6cE/9aQ5YPIlZungfLkcSl DcEFLei7DyqxYCr2uUvkdw1yNhwHkrNfMKnQ+mFz/V193C2mRHJLryn5+Q4Pe2Bdg3VE=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:59962 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1vx8f8-0007Wl-EJ; Mon, 02 Mar 2026 14:10:39 -0500 From: Hugo Villeneuve To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, shawnguo@kernel.org, laurent.pinchart+renesas@ideasonboard.com, antonin.godard@bootlin.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, hugo@hugovil.com, Hugo Villeneuve , stable@kernel.org Date: Mon, 2 Mar 2026 14:03:37 -0500 Message-ID: <20260302190953.669325-2-hugo@hugovil.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302190953.669325-1-hugo@hugovil.com> References: <20260302190953.669325-1-hugo@hugovil.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: [PATCH 01/14] ARM: dts: imx6ul-var-som: fix warning for non-existent dc-supply property X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve The dc-supply property is non-existent in Linux now, nor when this DTS file was created when importing it from Variscite own kernel. Therefore remove it to fix this warning: imx6ul-var-som-concerto.dtb: cpu@0 (arm,cortex-a7): Unevaluated properties are not allowed ('dc-supply' was unexpected) from schema $id: http://devicetree.org/schemas/arm/cpus.yaml Fixes: 9d6a67d9c7a9 ("ARM: dts: imx6ul: Add Variscite VAR-SOM-MX6UL SoM sup= port") Cc: stable@kernel.org Signed-off-by: Hugo Villeneuve --- arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/= dts/nxp/imx/imx6ul-var-som.dtsi index 4e536e0252def..3fb5e2fb68777 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -45,10 +45,6 @@ &clks { assigned-clock-rates =3D <786432000>; }; =20 -&cpu0 { - dc-supply =3D <®_gpio_dvfs>; -}; - &fec1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_md= io>; --=20 2.47.3 From nobody Tue Mar 3 03:38:36 2026 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3D9C369204; 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charset="utf-8" From: Hugo Villeneuve dmesg warning: OF: /soc/bus@2000000/ethernet@20b4000/mdio/ethernet-phy@3: Read of boolean property 'micrel,rmii-reference-clock-select-25-mhz' with a value. Using of_property_read_bool() for non-boolean properties is deprecated and results in a warning during runtime since commit c141ecc3cecd ("of: Warn when of_property_read_bool() is used on non-boolean properties") micrel,rmii-reference-clock-select-25-mhz is a boolean property and should not have a value, so remove it. Signed-off-by: Hugo Villeneuve --- arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/a= rm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 9ff3b374a2b31..085985356668f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -79,7 +79,7 @@ ethphy1: ethernet-phy@3 { reset-gpios =3D <&gpio5 5 GPIO_ACTIVE_LOW>; reset-assert-us =3D <100000>; micrel,led-mode =3D <0>; - micrel,rmii-reference-clock-select-25-mhz =3D <1>; + micrel,rmii-reference-clock-select-25-mhz; }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/= dts/nxp/imx/imx6ul-var-som.dtsi index 3fb5e2fb68777..30032be6fdd50 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -64,7 +64,7 @@ ethphy0: ethernet-phy@1 { reset-gpios =3D <&gpio5 0 GPIO_ACTIVE_LOW>; reset-assert-us =3D <100000>; micrel,led-mode =3D <1>; - micrel,rmii-reference-clock-select-25-mhz =3D <1>; + micrel,rmii-reference-clock-select-25-mhz; }; }; }; --=20 2.47.3 From nobody Tue Mar 3 03:38:36 2026 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB3E636C9CD; Mon, 2 Mar 2026 19:11:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.120.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478666; cv=none; b=lAjV5ylbx5ujZHXK9LJdEtlofB0Jgo5G9A2nKU27X9yp6O2LhBd9XIGQxs6OqecU7swNT23oPtAFZIZlPqwsIM3KTlvYb7+zPaGC04ivaoBKSUNJRQAdtsaZbihHsgW/y4uIt0cCoV6BWOtlCKX7xBC2aYN3UlkIKxALxnaOxko= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478666; c=relaxed/simple; bh=8+ZY4qxWrfTCLugBH7CrOkRoGQL3jwxDNwxkvtQxVUg=; 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charset="utf-8" From: Hugo Villeneuve There is no Variscite module named VAR-SOM-MX6UL. The official name from the manufacturer is VAR-SOM-6UL. Change SOM model name to VAR-SOM-6UL to reduce confusion. Signed-off-by: Hugo Villeneuve --- arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts | 4 ++-- arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/a= rm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 085985356668f..d16e75164fd18 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-MX6UL + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL * Variscite SoM mounted on it * * Copyright 2019 Variscite Ltd. @@ -11,7 +11,7 @@ #include =20 / { - model =3D "Variscite VAR-SOM-MX6UL Concerto Board"; + model =3D "Variscite VAR-SOM-6UL Concerto Board"; compatible =3D "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fs= l,imx6ul"; =20 chosen { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/= dts/nxp/imx/imx6ul-var-som.dtsi index 30032be6fdd50..7259526e2b884 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Support for Variscite VAR-SOM-MX6UL Module + * Support for Variscite VAR-SOM-6UL Module * * Copyright 2019 Variscite Ltd. * Copyright 2025 Bootlin @@ -13,7 +13,7 @@ #include =20 / { - model =3D "Variscite VAR-SOM-MX6UL module"; + model =3D "Variscite VAR-SOM-6UL module"; compatible =3D "variscite,var-som-imx6ul", "fsl,imx6ul"; =20 memory@80000000 { --=20 2.47.3 From nobody Tue Mar 3 03:38:36 2026 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFFCE37104C; Mon, 2 Mar 2026 19:11:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.120.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478666; cv=none; b=R1S4bx54Ged2pVgqU19ye5ExTtFuVG1r8R/9dTxW8OjHKmjSn5dE/eY7/UVE4QYzm7MUtWWAmaLw4gRYTfjb2c/ygtaPwelfDARMfqgMozCw1+b0hg9sqtlNdzUs4zO3pVwLvAOs5h4BBI4FrxVguUjiR6mExx9BfEiEuCqGRxY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478666; c=relaxed/simple; bh=ug8koWtKmBbGcvYvigqXfSmXEMD5IxgDGX6rf7TgjuQ=; h=From:To:Cc:Date:Message-ID:In-Reply-To:References:MIME-Version: Subject; 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charset="utf-8" From: Hugo Villeneuve There is no Variscite module named VAR-SOM-MX6UL. The official name from the manufacturer is VAR-SOM-6UL. Change SOM model name to VAR-SOM-6UL to reduce confusion. Signed-off-by: Hugo Villeneuve --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 5716d701292cf..99dc1b3f1ba92 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -688,7 +688,7 @@ properties: - const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL - const: fsl,imx6ul =20 - - description: i.MX6UL Variscite VAR-SOM-MX6 Boards + - description: i.MX6UL Variscite VAR-SOM-6UL Boards items: - const: variscite,mx6ulconcerto - const: variscite,var-som-imx6ul --=20 2.47.3 From nobody Tue Mar 3 03:38:36 2026 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1EE6366DB7; Mon, 2 Mar 2026 19:11:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.120.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478665; cv=none; b=mtbKZzSyAV5r86oktrpBYxwC9fdm8BnsQoC8loDsuuYCoNT7jPQ1uWGQPrPAkBHX/GVehcjqUj8aqwlJedfqjdUyNtBbk0/r18h1VlQM2vc7vfr6Efx9+7mVVLRu/IeMMcuuTPL47ayHh+4hwV4/F5j9kzVkWoos7zR83u3LPHI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478665; c=relaxed/simple; bh=GFKwW8tRq9+ZKQI6HFvZlyumfI9eovpnWAO8ZCtqErU=; h=From:To:Cc:Date:Message-ID:In-Reply-To:References:MIME-Version: Subject; b=i2kFEGwn779yF18eLwSBM2zJwogLax/gMdB/bMZ5a9xKLAJ+mzOtahanxaBJv+uGBaRkqdGDpndK8uG2/SGCmsy5CXpJq9lZpyIj/BluLq9NS3g3gwBHSoiTroL2R0qQUo6kPEywhR2xTDQF0lfM1m+rlVunehl635UldHjPWNA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com; spf=pass smtp.mailfrom=hugovil.com; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b=i6o2lfbo; arc=none smtp.client-ip=162.243.120.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=hugovil.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b="i6o2lfbo" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Cc:To :From:subject:date:message-id:reply-to; bh=eptGtomLn+jMzHp1bkZ0E5wTEGfhea4HBPM13R/EfB0=; b=i6o2lfbowvWbbUaLtCAJ0C1UHz ieLjxLBuB8x4HiiUrlVOd2zo7FMtXCsOVHG8N2/HWyIFxGiVjJvBuW2FMfIMMEbbCnIh7xKmIJDJy 4P6oXDBuNYbWDjBLl5jV+ym5dTMsnVeXcP+vx83oDsBnbeZouT02wvbdghwmxfqdIboI=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:59962 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1vx8fE-0007Wl-6l; Mon, 02 Mar 2026 14:10:44 -0500 From: Hugo Villeneuve To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, shawnguo@kernel.org, laurent.pinchart+renesas@ideasonboard.com, antonin.godard@bootlin.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, hugo@hugovil.com, Hugo Villeneuve Date: Mon, 2 Mar 2026 14:03:41 -0500 Message-ID: <20260302190953.669325-6-hugo@hugovil.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302190953.669325-1-hugo@hugovil.com> References: <20260302190953.669325-1-hugo@hugovil.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: [PATCH 05/14] dt-bindings: arm: fsl: add variscite,var-som-imx6ull X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Add support for the imx6ull CPU variant of the Variscite concerto board evaluation kit with a VAR-SOM-6UL. Signed-off-by: Hugo Villeneuve --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 99dc1b3f1ba92..61cda40d31873 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -797,6 +797,12 @@ properties: - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL - const: fsl,imx6ull =20 + - description: i.MX6ULL Variscite VAR-SOM-6UL Boards + items: + - const: variscite,mx6ullconcerto # Variscite VAR-SOM-6UL dev k= it board + - const: variscite,var-som-imx6ull # Variscite VAR-SOM-6UL SoM (= 6ULL variant) + - const: fsl,imx6ull + - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules items: - enum: --=20 2.47.3 From nobody Tue Mar 3 03:38:36 2026 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1ECB375AA3; Mon, 2 Mar 2026 19:11:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.120.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478666; cv=none; b=PqmEXeeH0zG+a4WGZUxNtuX17+f/9UBKELv1Iv5/ITmPe17P3CttFMQnAq6zMnWi5SSD7oD7U0LPYy7YOGGdxxkwBm8nqviYOODcuNZ7vLGtpc5kwl7+jt9RGaJX8HMSCJocBagU97dbdmuqFFA72sXcgynuz0OJSaX+Za+bRKY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478666; c=relaxed/simple; bh=KNbyFdp8iCtBuWAZr8TmuaY7Y0W7B9QMy1SPLvEiPJA=; h=From:To:Cc:Date:Message-ID:In-Reply-To:References:MIME-Version: Subject; b=HRXN530kknUfbgLZ7rsPIR1su0pVCv8QH7jWo0Th2IqBPyMIgFSwWyBXC9J1hj5uoJIH1xiFOfV7HUFESPPahtW8xDmwOT18q/11TJNsAMvulKlIw6+S+I8ZEaQafwbMr+b+DhnfwEzALmDhUHjPtyX44vqHewx7uvgzL/b4AUQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com; spf=pass smtp.mailfrom=hugovil.com; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b=A2ZW0cqt; arc=none smtp.client-ip=162.243.120.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=hugovil.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b="A2ZW0cqt" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Cc:To :From:subject:date:message-id:reply-to; bh=UyH7hq1C83dHRYa5rTbJR0RphsXI/QzXCuR+L9DmAns=; b=A2ZW0cqtYwanyq3RgoQ/IHN+1E E6UWNwo9gZPMM0NmTbgw/I0hbIN7n9ngcy5mMkLgxR7PDX/WjAX+3m9s+lnUY7mgZjkOCmXEmfaMI tmtuVnCXVf8Nh6kqvCr3VBB6Xb+awxAzzp/ILOXlDYeKRnqyuRsS2+Y3TSlO8q6VMmno=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:59962 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1vx8fG-0007Wl-0F; Mon, 02 Mar 2026 14:10:46 -0500 From: Hugo Villeneuve To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, shawnguo@kernel.org, laurent.pinchart+renesas@ideasonboard.com, antonin.godard@bootlin.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, hugo@hugovil.com, Hugo Villeneuve Date: Mon, 2 Mar 2026 14:03:42 -0500 Message-ID: <20260302190953.669325-7-hugo@hugovil.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302190953.669325-1-hugo@hugovil.com> References: <20260302190953.669325-1-hugo@hugovil.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: [PATCH 06/14] ARM: dts: imx6ul-var-som: Factor out common parts for all CPU variants X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Factor out the parts on the Variscite VAR-SOM-6UL [1] that are common to all CPU variants (6UL, 6ULL, etc). This will simplify adding future dedicated device tree files for each CPU variant. Link: https://www.variscite.com/product/system-on-module-som/cortex-a7/var-= som-6ul-nxp-imx6ul-6ull-6ulz/ [1] Signed-off-by: Hugo Villeneuve --- ...ar-som.dtsi =3D> imx6ul-var-som-common.dtsi} | 6 +- arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 214 +----------------- .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 15 ++ 3 files changed, 18 insertions(+), 217 deletions(-) copy arch/arm/boot/dts/nxp/imx/{imx6ul-var-som.dtsi =3D> imx6ul-var-som-co= mmon.dtsi} (98%) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/= dts/nxp/imx/imx6ul-var-som-common.dtsi similarity index 98% copy from arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi copy to arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index 7259526e2b884..2072e8ba4d469 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -1,14 +1,12 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Support for Variscite VAR-SOM-6UL Module + * Support for the common parts shared by all the different CPU options on + * Variscite VAR-SOM-6UL Module * * Copyright 2019 Variscite Ltd. * Copyright 2025 Bootlin */ =20 -/dts-v1/; - -#include "imx6ul.dtsi" #include #include =20 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/= dts/nxp/imx/imx6ul-var-som.dtsi index 7259526e2b884..35a0c0b3603fd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -9,221 +9,9 @@ /dts-v1/; =20 #include "imx6ul.dtsi" -#include -#include +#include "imx6ul-var-som-common.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL module"; compatible =3D "variscite,var-som-imx6ul", "fsl,imx6ul"; - - memory@80000000 { - device_type =3D "memory"; - reg =3D <0x80000000 0x20000000>; - }; - - reg_gpio_dvfs: reg-gpio-dvfs { - compatible =3D "regulator-gpio"; - regulator-min-microvolt =3D <1300000>; - regulator-max-microvolt =3D <1400000>; - regulator-name =3D "gpio_dvfs"; - regulator-type =3D "voltage"; - gpios =3D <&gpio4 13 GPIO_ACTIVE_HIGH>; - states =3D <1300000 0x1 - 1400000 0x0>; - }; - - rmii_ref_clk: rmii-ref-clk { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <25000000>; - clock-output-names =3D "rmii-ref"; - }; -}; - -&clks { - assigned-clocks =3D <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates =3D <786432000>; -}; - -&fec1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_md= io>; - phy-mode =3D "rmii"; - phy-handle =3D <ðphy0>; - status =3D "okay"; - - mdio { - #address-cells =3D <1>; - #size-cells =3D <0>; - - ethphy0: ethernet-phy@1 { - compatible =3D "ethernet-phy-ieee802.3-c22"; - reg =3D <1>; - clocks =3D <&rmii_ref_clk>; - clock-names =3D "rmii-ref"; - reset-gpios =3D <&gpio5 0 GPIO_ACTIVE_LOW>; - reset-assert-us =3D <100000>; - micrel,led-mode =3D <1>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - -&iomuxc { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_hog>; - - pinctrl_enet1: enet1grp { - fsl,pins =3D < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet1_gpio: enet1-gpiogrp { - fsl,pins =3D < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ - >; - }; - - pinctrl_enet1_mdio: enet1-mdiogrp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins =3D < - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */ - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */ - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins =3D < - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - >; - }; - - pinctrl_tsc: tscgrp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins =3D < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 - MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins =3D < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins =3D < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins =3D < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 - >; - }; -}; - -&pxp { - status =3D "okay"; -}; - -&sai2 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_sai2>; - assigned-clocks =3D <&clks IMX6UL_CLK_SAI2_SEL>, - <&clks IMX6UL_CLK_SAI2>; - assigned-clock-parents =3D <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates =3D <0>, <12288000>; - fsl,sai-mclk-direction-output; - status =3D "okay"; -}; - -&snvs_poweroff { - status =3D "okay"; -}; - -&tsc { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_tsc>; - xnur-gpios =3D <&gpio1 3 GPIO_ACTIVE_LOW>; - measure-delay-time =3D <0xffff>; - pre-charge-time =3D <0xfff>; - status =3D "okay"; -}; - -&uart2 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_uart2>; - uart-has-rtscts; - status =3D "okay"; -}; - -&usdhc2 { - pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; - pinctrl-0 =3D <&pinctrl_usdhc2>; - pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>; - pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>; - bus-width =3D <8>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - wakeup-source; - status =3D "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot= /dts/nxp/imx/imx6ull-var-som.dtsi new file mode 100644 index 0000000000000..ba482a97623b2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite VAR-SOM-6UL module with imx6ull CPU + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +#include "imx6ull.dtsi" +#include "imx6ul-var-som-common.dtsi" + +/ { + model =3D "Variscite VAR-SOM-6UL module"; + compatible =3D "variscite,var-som-imx6ull", "fsl,imx6ull"; +}; --=20 2.47.3 From nobody Tue Mar 3 03:38:36 2026 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F81E379EC9; Mon, 2 Mar 2026 19:11:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.120.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478670; cv=none; b=G375beU0fZOKXuaQ8q4UsP7KNK/ui8UZ+ATU63hJDo+QNeEyelCN3ybsmulg7HycX+oz48bPG5gP5cOg4G7La8GxKfWWpedp0oSO2kn5KLyLg4iCgJgpP/jd33jO0SJrRyk61g+jG7Nhxub9qk9xTQ7rSpvwVqRxN4uFJb4vIZE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478670; c=relaxed/simple; bh=AJeYnQRs15OIr5dOs2oawchpIH1qHwZ2sibnkoH1KYw=; h=From:To:Cc:Date:Message-ID:In-Reply-To:References:MIME-Version: Subject; b=grYj1PPGmqsvL0pRsHWbbRT8HmwxMa1XwGg5Zms057keJO96HFzLOlQgCURydEsuvUtorT/RqhVOFGAslHQ97PNdfCWVrK3Jw83f16LkUA3YHWSR++hBMJS8ejn6uy61iSzmPqUvO49NpuCTOA9Ok9Sg1yDUi3aArEGgSXzPVQs= ARC-Authentication-Results: i=1; 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Mon, 02 Mar 2026 14:10:49 -0500 From: Hugo Villeneuve To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, shawnguo@kernel.org, laurent.pinchart+renesas@ideasonboard.com, antonin.godard@bootlin.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, hugo@hugovil.com, Hugo Villeneuve Date: Mon, 2 Mar 2026 14:03:43 -0500 Message-ID: <20260302190953.669325-8-hugo@hugovil.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302190953.669325-1-hugo@hugovil.com> References: <20260302190953.669325-1-hugo@hugovil.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: [PATCH 07/14] ARM: dts: imx6ul-var-som-concerto: Factor out common parts for all CPU variants X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Export common parts to the Variscite VAR-SOM-6UL dtsi so that they can be reused on other boards. This will simplify adding future dedicated device tree files for each CPU variant. Add i2c1 pinctrl to var-som dtsi pinmux, so that it can be reused by other boards. Reorder pinctrl_gpio_leds to respect alphabetical order. Signed-off-by: Hugo Villeneuve --- arch/arm/boot/dts/nxp/imx/Makefile | 1 + .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 7 + ...ts =3D> imx6ul-var-som-concerto-common.dtsi} | 17 +- .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 312 +----------------- .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 17 + 5 files changed, 33 insertions(+), 321 deletions(-) copy arch/arm/boot/dts/nxp/imx/{imx6ul-var-som-concerto.dts =3D> imx6ul-va= r-som-concerto-common.dtsi} (95%) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx= /Makefile index de4142e8f3ce8..bc534d0fb1412 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -376,6 +376,7 @@ dtb-$(CONFIG_SOC_IMX6UL) +=3D \ imx6ull-tarragon-slavext.dtb \ imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ull-tqma6ull2l-mba6ulx.dtb \ + imx6ull-var-som-concerto.dtb \ imx6ull-uti260b.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/ar= m/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index 2072e8ba4d469..22b0c4e0725a5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -104,6 +104,13 @@ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Ena= ble */ >; }; =20 + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + pinctrl_sai2: sai2grp { fsl,pins =3D < MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/a= rm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi similarity index 95% copy from arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts copy to arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index d16e75164fd18..10a23ae104359 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -1,19 +1,15 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL - * Variscite SoM mounted on it + * Variscite SoM mounted on it, for all CPU variants. * * Copyright 2019 Variscite Ltd. * Copyright 2025 Bootlin */ =20 -#include "imx6ul-var-som.dtsi" #include =20 / { - model =3D "Variscite VAR-SOM-6UL Concerto Board"; - compatible =3D "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fs= l,imx6ul"; - chosen { stdout-path =3D &uart1; }; @@ -144,22 +140,15 @@ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059 >; }; =20 - pinctrl_gpio_leds: gpio-ledsgrp { - fsl,pins =3D < - MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ - >; - }; - pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp { fsl,pins =3D < MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 >; }; =20 - pinctrl_i2c1: i2c1grp { + pinctrl_gpio_leds: gpio-ledsgrp { fsl,pins =3D < - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ >; }; =20 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/a= rm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index d16e75164fd18..11b45f105b7ad 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -1,320 +1,18 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL - * Variscite SoM mounted on it + * Variscite SoM mounted on it (6UL CPU variant). * * Copyright 2019 Variscite Ltd. * Copyright 2025 Bootlin */ =20 +/dts-v1/; + #include "imx6ul-var-som.dtsi" -#include +#include "imx6ul-var-som-concerto-common.dtsi" =20 / { - model =3D "Variscite VAR-SOM-6UL Concerto Board"; + model =3D "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; compatible =3D "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fs= l,imx6ul"; - - chosen { - stdout-path =3D &uart1; - }; - - gpio-keys { - compatible =3D "gpio-keys"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>; - - key-back { - gpios =3D <&gpio4 14 GPIO_ACTIVE_LOW>; - linux,code =3D ; - }; - - key-wakeup { - gpios =3D <&gpio5 8 GPIO_ACTIVE_LOW>; - linux,code =3D ; - wakeup-source; - }; - }; - - leds { - compatible =3D "gpio-leds"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_gpio_leds>; - - led-0 { - function =3D LED_FUNCTION_STATUS; - color =3D ; - label =3D "gpled2"; - gpios =3D <&gpio1 25 GPIO_ACTIVE_HIGH>; - linux,default-trigger =3D "heartbeat"; - }; - }; -}; - -&can1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_flexcan1>; - status =3D "okay"; -}; - -&fec1 { - status =3D "disabled"; -}; - -&fec2 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_md= io>; - phy-mode =3D "rmii"; - phy-handle =3D <ðphy1>; - status =3D "okay"; - - mdio { - #address-cells =3D <1>; - #size-cells =3D <0>; - - ethphy1: ethernet-phy@3 { - compatible =3D "ethernet-phy-ieee802.3-c22"; - reg =3D <3>; - clocks =3D <&rmii_ref_clk>; - clock-names =3D "rmii-ref"; - reset-gpios =3D <&gpio5 5 GPIO_ACTIVE_LOW>; - reset-assert-us =3D <100000>; - micrel,led-mode =3D <0>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - -&i2c1 { - clock-frequency =3D <100000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_i2c1>; - status =3D "okay"; - - rtc@68 { - /* - * To actually use this interrupt - * connect pins J14.8 & J14.10 on the Concerto-Board. - */ - compatible =3D "dallas,ds1337"; - reg =3D <0x68>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_rtc>; - interrupt-parent =3D <&gpio1>; - interrupts =3D <10 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&iomuxc { - pinctrl_enet2: enet2grp { - fsl,pins =3D < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_enet2_gpio: enet2-gpiogrp { - fsl,pins =3D < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ - >; - }; - - pinctrl_enet2_mdio: enet2-mdiogrp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins =3D < - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_gpio_key_back: gpio-key-backgrp { - fsl,pins =3D < - MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059 - >; - }; - - pinctrl_gpio_leds: gpio-ledsgrp { - fsl,pins =3D < - MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ - >; - }; - - pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp { - fsl,pins =3D < - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins =3D < - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins =3D < - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins =3D < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins =3D < - MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins =3D < - MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins =3D < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins =3D < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins =3D < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1-gpiogrp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 - >; - }; -}; - -&pwm4 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_pwm4>; - status =3D "okay"; -}; - -&snvs_pwrkey { - status =3D "disabled"; -}; - -&snvs_rtc { - status =3D "disabled"; -}; - -&tsc { - /* - * Conflics with wdog1 ext-reset-output & SD CD pins, - * so we keep it disabled by default. - */ - status =3D "disabled"; -}; - -/* Console UART */ -&uart1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_uart1>; - status =3D "okay"; -}; - -/* ttymxc4 UART */ -&uart5 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_uart5>; - uart-has-rtscts; - status =3D "okay"; -}; - -&usbotg1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_usb_otg1_id>; - dr_mode =3D "otg"; - disable-over-current; - srp-disable; - hnp-disable; - adp-disable; - status =3D "okay"; -}; - -&usbotg2 { - dr_mode =3D "host"; - disable-over-current; - status =3D "okay"; -}; - -&usdhc1 { - pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; - pinctrl-0 =3D <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; - cd-gpios =3D <&gpio1 0 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status =3D "okay"; -}; - -&wdog1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_wdog>; - /* - * To actually use ext-reset-output - * connect pins J17.3 & J17.8 on the Concerto-Board - */ - fsl,ext-reset-output; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/= arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts new file mode 100644 index 0000000000000..7c601af2657d7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL + * Variscite SoM mounted on it (6ULL CPU variant). + * + * Copyright 2026 Dimonoff + */ + +/dts-v1/; + +#include "imx6ull-var-som.dtsi" +#include "imx6ul-var-som-concerto-common.dtsi" + +/ { + model =3D "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; + compatible =3D "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "= fsl,imx6ull"; +}; --=20 2.47.3 From nobody Tue Mar 3 03:38:36 2026 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70EDD369206; Mon, 2 Mar 2026 19:11:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.120.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478667; cv=none; b=PsIuY9QOYFKosl2AlBHyejUhbNICm0EkBcDKlCLZ8T+NJPfhEZB5hvW7d2/F/T2A0XcVHa6mGqOIyL79qN/kLFbMmbMfUwvsfGGO7dlnT3+uB1nQ4H+Bj2g5ecXjJGEXFidpqH8SS3JTo/onee1PELjDeDW59QlzicbhEm7Z8iM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Cc:To :From:subject:date:message-id:reply-to; bh=eLBVbmAAAVsEz0x8golWQm+S6FLxF1rb4QI2LLhQark=; b=xVGu5yG9Yir/yRkWz92EHqc15P ImHDqv6NT8OJNNOK3nZNA+oQ8TYVxhnMCIBHmC0Lu4oZbEgSCtuGf6T+HCVkOixc6LH6PoZMPeZHF HUxdphbIOCrCMdSTyHd5EkJthdTD0211BEvz2uK4gR9FczxgeuIDlOgmKrp0SLriqBWQ=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:59962 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1vx8fL-0007Wl-Df; Mon, 02 Mar 2026 14:10:51 -0500 From: Hugo Villeneuve To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, shawnguo@kernel.org, laurent.pinchart+renesas@ideasonboard.com, antonin.godard@bootlin.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, hugo@hugovil.com, Hugo Villeneuve Date: Mon, 2 Mar 2026 14:03:44 -0500 Message-ID: <20260302190953.669325-9-hugo@hugovil.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302190953.669325-1-hugo@hugovil.com> References: <20260302190953.669325-1-hugo@hugovil.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: [PATCH 08/14] ARM: dts: imx6ul-var-som: factor out SD card support X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Move SD support to a separate include, since it cannot be used at the same time as the Wifi/BT module. Signed-off-by: Hugo Villeneuve --- .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 33 ++++++++++++ .../imx/imx6ul-var-som-concerto-common.dtsi | 51 ------------------- .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 1 + .../boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi | 27 ++++++++++ .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 1 + 5 files changed, 62 insertions(+), 51 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/ar= m/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index 22b0c4e0725a5..dd4ecff1eb786 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -139,6 +139,39 @@ MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 >; }; =20 + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins =3D < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi = b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index 10a23ae104359..ea8d9905ce6e7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -186,45 +186,6 @@ MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059 >; }; =20 - pinctrl_usdhc1: usdhc1grp { - fsl,pins =3D < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins =3D < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins =3D < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1-gpiogrp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ - >; - }; - pinctrl_wdog: wdoggrp { fsl,pins =3D < MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 @@ -286,18 +247,6 @@ &usbotg2 { status =3D "okay"; }; =20 -&usdhc1 { - pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; - pinctrl-0 =3D <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; - cd-gpios =3D <&gpio1 0 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status =3D "okay"; -}; - &wdog1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_wdog>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/a= rm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 11b45f105b7ad..85ebac30d7bed 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -11,6 +11,7 @@ =20 #include "imx6ul-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" +#include "imx6ul-var-som-sd.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi b/arch/arm/bo= ot/dts/nxp/imx/imx6ul-var-som-sd.dtsi new file mode 100644 index 0000000000000..0e6d9b945eb4a --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support optional SD card interface on Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +&iomuxc { + pinctrl_usdhc1_gpio: usdhc1-gpiogrp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ + >; + }; +}; + +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + cd-gpios =3D <&gpio1 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/= arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts index 7c601af2657d7..ebf88c3e1addc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -10,6 +10,7 @@ =20 #include "imx6ull-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" +#include "imx6ul-var-som-sd.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; 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Mon, 02 Mar 2026 14:10:55 -0500 From: Hugo Villeneuve To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, shawnguo@kernel.org, laurent.pinchart+renesas@ideasonboard.com, antonin.godard@bootlin.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, hugo@hugovil.com, Hugo Villeneuve Date: Mon, 2 Mar 2026 14:03:45 -0500 Message-ID: <20260302190953.669325-10-hugo@hugovil.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302190953.669325-1-hugo@hugovil.com> References: <20260302190953.669325-1-hugo@hugovil.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: [PATCH 09/14] ARM: dts: imx6ul-var-som: add proper Wifi and Bluetooth support X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve The existing configuration of the optional Wifi/Bluetooth module was copied from the original Variscite kernel tree, and requires custom scripts to properly configure the Wifi/Bluetooth module. Add proper support for the optional Wifi and Bluetooth configuration on VAR-SOM-6UL so that it works out of the box, without any custom scripts. The SD card interface cannot be used if the Wifi/BT module is in use. Signed-off-by: Hugo Villeneuve --- arch/arm/boot/dts/nxp/imx/Makefile | 2 + .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 18 ++--- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 18 +++++ .../boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi | 75 +++++++++++++++++++ arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 15 ++++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 18 +++++ .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 15 ++++ 7 files changed, 151 insertions(+), 10 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.= dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full= .dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx= /Makefile index bc534d0fb1412..c7f24ee63071f 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -339,6 +339,7 @@ dtb-$(CONFIG_SOC_IMX6UL) +=3D \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ imx6ul-var-som-concerto.dtb \ + imx6ul-var-som-concerto-full.dtb \ imx6ull-14x14-evk.dtb \ imx6ull-colibri-aster.dtb \ imx6ull-colibri-emmc-aster.dtb \ @@ -377,6 +378,7 @@ dtb-$(CONFIG_SOC_IMX6UL) +=3D \ imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ull-var-som-concerto.dtb \ + imx6ull-var-som-concerto-full.dtb \ imx6ull-uti260b.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/ar= m/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index dd4ecff1eb786..af8c5d2db53d4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -19,6 +19,14 @@ memory@80000000 { reg =3D <0x80000000 0x20000000>; }; =20 + reg_3p3v: regulator-3p3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "3P3V"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + reg_gpio_dvfs: reg-gpio-dvfs { compatible =3D "regulator-gpio"; regulator-min-microvolt =3D <1300000>; @@ -68,9 +76,6 @@ ethphy0: ethernet-phy@1 { }; =20 &iomuxc { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_hog>; - pinctrl_enet1: enet1grp { fsl,pins =3D < MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 @@ -97,13 +102,6 @@ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 >; }; =20 - pinctrl_hog: hoggrp { - fsl,pins =3D < - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */ - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */ - >; - }; - pinctrl_i2c1: i2c1grp { fsl,pins =3D < MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts new file mode 100644 index 0000000000000..519250b31db24 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL + * Variscite SoM mounted on it (6UL CPU variant). + * + * Copyright 2026 Dimonoff + */ + +/dts-v1/; + +#include "imx6ul-var-som.dtsi" +#include "imx6ul-var-som-concerto-common.dtsi" +#include "imx6ul-var-som-wifi.dtsi" + +/ { + model =3D "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; + compatible =3D "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fs= l,imx6ul"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi b/arch/arm/= boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi new file mode 100644 index 0000000000000..6d16ff7909dab --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support optional Wifi/Bluetooth on Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +/ { + reg_sd1_vmmc: regulator_sd1_vmmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "VMMC1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us =3D <10000>; + }; + + usdhc1_pwrseq: usdhc1-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_brcm_wifi>; + reset-gpios =3D <&gpio5 6 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_32k_clk: 32kclkgrp { + /* + * For TP option, an additional oscillator is assembled on the + * SOM to provide 32 kHz to the WiFi module. Without TP option, + * this pin is configured to provide the 32 KHz clock to the + * WiFi module. + */ + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x03029 + >; + }; +}; + +&tsc { + status =3D "disabled"; +}; + +/* Bluetooth UART */ +&uart2 { + bluetooth { + compatible =3D "brcm,bcm43438-bt"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_brcm_bt>; + shutdown-gpios =3D <&gpio5 4 GPIO_ACTIVE_HIGH>; + vbat-supply =3D <®_3p3v>; + vddio-supply =3D <®_3p3v>; + }; +}; + +&usdhc1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>, <&pinctrl_32k_clk>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>, <&pinctrl_32k_clk>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>, <&pinctrl_32k_clk>; + no-1-8-v; + non-removable; + mmc-pwrseq =3D <&usdhc1_pwrseq>; + vmmc-supply =3D <®_sd1_vmmc>; + status =3D "okay"; + + brcmf: wifi@1 { + compatible =3D "brcm,bcm4329-fmac"; /* LWB option: Sterling LWB5 */ + reg =3D <1>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/= dts/nxp/imx/imx6ul-var-som.dtsi index 35a0c0b3603fd..b4e6a9316dd81 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -15,3 +15,18 @@ / { model =3D "Variscite VAR-SOM-6UL module"; compatible =3D "variscite,var-som-imx6ul", "fsl,imx6ul"; }; + +&iomuxc { + pinctrl_brcm_bt: brcm-bt-grp { + fsl,pins =3D < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON (BT_EN) */ + >; + }; + + pinctrl_brcm_wifi: brcm-wifi-grp { + fsl,pins =3D < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/= arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts new file mode 100644 index 0000000000000..7c0e313603630 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL + * Variscite SoM mounted on it (6ULL CPU variant). + * + * Copyright 2026 Dimonoff + */ + +/dts-v1/; + +#include "imx6ull-var-som.dtsi" +#include "imx6ul-var-som-concerto-common.dtsi" +#include "imx6ul-var-som-wifi.dtsi" + +/ { + model =3D "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; + compatible =3D "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "= fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot= /dts/nxp/imx/imx6ull-var-som.dtsi index ba482a97623b2..3067ff6a1bc74 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi @@ -13,3 +13,18 @@ / { model =3D "Variscite VAR-SOM-6UL module"; compatible =3D "variscite,var-som-imx6ull", "fsl,imx6ull"; }; + +&iomuxc { + pinctrl_brcm_bt: brcm-bt-grp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON (BT_EN) */ + >; + }; + + pinctrl_brcm_wifi: brcm-wifi-grp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */ + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ + >; + }; +}; --=20 2.47.3 From nobody Tue Mar 3 03:38:36 2026 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97E0A3E9F7A; Mon, 2 Mar 2026 19:11:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.120.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478673; cv=none; b=pSv8E5K85PZ4DTsb1sFJF+2OdR8MfcyFWhbLMHTkV9GSPykXra+HQ4ZL6JYS+Mkb91yqGe45w/oWM4sfaxyn5QzgD0W8ci4QDekAlqVpSKOk4TfYv9P9iJEYon4xKNbNSZMmmF3VHUXeV8N/80Y8JWSwEyFpiX7hRIoeg2WgNNA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478673; c=relaxed/simple; bh=ERQv9AQQgkQ3e6Z1hIgg/Z1GjzoihNo28cjh23opDUs=; h=From:To:Cc:Date:Message-ID:In-Reply-To:References:MIME-Version: Subject; b=fr9N+Y+oLwA+FRv9vkxgKllLgC96frEIh0giiL3DjitkDiVgDBztzRbr63GtfJ43pYpw6II7ttzinBLDKQimCkWaHE/+2eXDCQd4IjyJW978xBdDmBYlR9MwYe3wLQ33EUKYCvYaytMQyEXp5yF/XEurxdOFSUpmywHPurfq0gU= ARC-Authentication-Results: i=1; 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Mon, 02 Mar 2026 14:10:57 -0500 From: Hugo Villeneuve To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, shawnguo@kernel.org, laurent.pinchart+renesas@ideasonboard.com, antonin.godard@bootlin.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, hugo@hugovil.com, Hugo Villeneuve Date: Mon, 2 Mar 2026 14:03:46 -0500 Message-ID: <20260302190953.669325-11-hugo@hugovil.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302190953.669325-1-hugo@hugovil.com> References: <20260302190953.669325-1-hugo@hugovil.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: [PATCH 10/14] ARM: dts: imx6ul-var-som: factor out ENET2 ethernet support X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Not all boards use the ethernet ENET2 port, so factor out this functionality to a separate DTSI include file. On the concerto board, this uses the ethernet PHY assembled on it. Signed-off-by: Hugo Villeneuve --- .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 7 -- .../imx/imx6ul-var-som-concerto-common.dtsi | 50 -------------- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-enet2.dtsi | 68 +++++++++++++++++++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 1 + 7 files changed, 72 insertions(+), 57 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/ar= m/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index af8c5d2db53d4..af9b92f7709b4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -37,13 +37,6 @@ reg_gpio_dvfs: reg-gpio-dvfs { states =3D <1300000 0x1 1400000 0x0>; }; - - rmii_ref_clk: rmii-ref-clk { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <25000000>; - clock-output-names =3D "rmii-ref"; - }; }; =20 &clks { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi = b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index ea8d9905ce6e7..53cf801f39fcd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -56,30 +56,6 @@ &fec1 { status =3D "disabled"; }; =20 -&fec2 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_md= io>; - phy-mode =3D "rmii"; - phy-handle =3D <ðphy1>; - status =3D "okay"; - - mdio { - #address-cells =3D <1>; - #size-cells =3D <0>; - - ethphy1: ethernet-phy@3 { - compatible =3D "ethernet-phy-ieee802.3-c22"; - reg =3D <3>; - clocks =3D <&rmii_ref_clk>; - clock-names =3D "rmii-ref"; - reset-gpios =3D <&gpio5 5 GPIO_ACTIVE_LOW>; - reset-assert-us =3D <100000>; - micrel,led-mode =3D <0>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - &i2c1 { clock-frequency =3D <100000>; pinctrl-names =3D "default"; @@ -101,32 +77,6 @@ rtc@68 { }; =20 &iomuxc { - pinctrl_enet2: enet2grp { - fsl,pins =3D < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_enet2_gpio: enet2-gpiogrp { - fsl,pins =3D < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ - >; - }; - - pinctrl_enet2_mdio: enet2-mdiogrp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - >; - }; - pinctrl_flexcan1: flexcan1grp { fsl,pins =3D < MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts index 519250b31db24..3905171b47b32 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -11,6 +11,7 @@ #include "imx6ul-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" +#include "imx6ul-var-som-enet2.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/a= rm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 85ebac30d7bed..d0adcd0e80833 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-sd.dtsi" +#include "imx6ul-var-som-enet2.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi b/arch/arm= /boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi new file mode 100644 index 0000000000000..334ed3bbe02ce --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Ethernet ENET2 support for Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +/ { + rmii_ref_clk: rmii-ref-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + clock-output-names =3D "rmii-ref"; + }; +}; + +&fec2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_md= io>; + phy-mode =3D "rmii"; + phy-handle =3D <ðphy1>; + status =3D "okay"; + + mdio_enet2: mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy1: ethernet-phy@3 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <3>; + clocks =3D <&rmii_ref_clk>; + clock-names =3D "rmii-ref"; + reset-gpios =3D <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <100000>; + micrel,led-mode =3D <0>; + micrel,rmii-reference-clock-select-25-mhz; + }; + }; +}; + +&iomuxc { + pinctrl_enet2: enet2grp { + fsl,pins =3D < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_enet2_gpio: enet2-gpiogrp { + fsl,pins =3D < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ + >; + }; + + pinctrl_enet2_mdio: enet2-mdiogrp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/= arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts index 7c0e313603630..89b6032203a28 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -11,6 +11,7 @@ #include "imx6ull-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" +#include "imx6ul-var-som-enet2.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/= arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts index ebf88c3e1addc..f9bc6a9a5c1be 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -11,6 +11,7 @@ #include "imx6ull-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-sd.dtsi" +#include "imx6ul-var-som-enet2.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; 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Mon, 02 Mar 2026 14:11:00 -0500 From: Hugo Villeneuve To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, shawnguo@kernel.org, laurent.pinchart+renesas@ideasonboard.com, antonin.godard@bootlin.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, hugo@hugovil.com, Hugo Villeneuve Date: Mon, 2 Mar 2026 14:03:47 -0500 Message-ID: <20260302190953.669325-12-hugo@hugovil.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302190953.669325-1-hugo@hugovil.com> References: <20260302190953.669325-1-hugo@hugovil.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: [PATCH 11/14] ARM: dts: imx6ul-var-som: add support for EC configuration option (ENET1) X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve ENET1 is currently disabled and not supported/working on the concerto EVK. Add support for this optional configuration in a separate DTSI include file, so that it can be selectively enabled/disabled. Signed-off-by: Hugo Villeneuve --- In order for this to work, imx6ul-var-som-enet2.dtsi must be included first, and thus enabled, even if not used. Maybe there is a better way to support both independantly, but I'm not sure how. --- .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 50 ------------------- .../imx/imx6ul-var-som-concerto-common.dtsi | 4 -- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-enet1.dtsi | 44 ++++++++++++++++ .../dts/nxp/imx/imx6ul-var-som-enet2.dtsi | 11 ++++ arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 6 +++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 1 + .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 6 +++ 8 files changed, 69 insertions(+), 54 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/ar= m/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index af9b92f7709b4..70d19eccddb4c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -44,57 +44,7 @@ &clks { assigned-clock-rates =3D <786432000>; }; =20 -&fec1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_md= io>; - phy-mode =3D "rmii"; - phy-handle =3D <ðphy0>; - status =3D "okay"; - - mdio { - #address-cells =3D <1>; - #size-cells =3D <0>; - - ethphy0: ethernet-phy@1 { - compatible =3D "ethernet-phy-ieee802.3-c22"; - reg =3D <1>; - clocks =3D <&rmii_ref_clk>; - clock-names =3D "rmii-ref"; - reset-gpios =3D <&gpio5 0 GPIO_ACTIVE_LOW>; - reset-assert-us =3D <100000>; - micrel,led-mode =3D <1>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - &iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins =3D < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet1_gpio: enet1-gpiogrp { - fsl,pins =3D < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ - >; - }; - - pinctrl_enet1_mdio: enet1-mdiogrp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - >; - }; - pinctrl_i2c1: i2c1grp { fsl,pins =3D < MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi = b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index 53cf801f39fcd..107b1d0fe7827 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -52,10 +52,6 @@ &can1 { status =3D "okay"; }; =20 -&fec1 { - status =3D "disabled"; -}; - &i2c1 { clock-frequency =3D <100000>; pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts index 3905171b47b32..b5e6a3306e1cd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-enet1.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi b/arch/arm= /boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi new file mode 100644 index 0000000000000..6b1e34347bec7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Ethernet ENET1 support for Variscite VAR-SOM-6UL module with + * the EC configuration option ((ethernet PHY assembled on SOM). + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_enet1>, <&pinctrl_enet1_gpio>; + phy-mode =3D "rmii"; + phy-handle =3D <ðphy0>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins =3D < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; +}; + +&mdio_enet2 { + ethphy0: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + clocks =3D <&rmii_ref_clk>; + clock-names =3D "rmii-ref"; + reset-gpios =3D <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <100000>; + micrel,led-mode =3D <1>; + micrel,rmii-reference-clock-select-25-mhz; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi b/arch/arm= /boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi index 334ed3bbe02ce..b29fcdc079e37 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi @@ -26,6 +26,17 @@ mdio_enet2: mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 + ethphy0: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + clocks =3D <&rmii_ref_clk>; + clock-names =3D "rmii-ref"; + reset-gpios =3D <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <100000>; + micrel,led-mode =3D <1>; + micrel,rmii-reference-clock-select-25-mhz; + }; + ethphy1: ethernet-phy@3 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <3>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/= dts/nxp/imx/imx6ul-var-som.dtsi index b4e6a9316dd81..feea24c0e0683 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -29,4 +29,10 @@ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WI= FI_PWR 5G) */ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ >; }; + + pinctrl_enet1_gpio: enet1-gpiogrp { + fsl,pins =3D < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ + >; + }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/= arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts index 89b6032203a28..86f558c76fb3e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-enet1.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; 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spf=pass smtp.mailfrom=hugovil.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b="XVsnTCjp" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Cc:To :From:subject:date:message-id:reply-to; bh=CFBFNEMKcnSpTHh9SKoOHLvwoACzQuBcBBrl0aFcyCs=; b=XVsnTCjpC/XreXuKvCVw2tRVDn EV10Jpyt5uOpUenopTW8vNRNDZ+zMEYmmlHleqI4x8l6UZhrzA25eFs5ZHLDfOQXlmthKvvlCXohS oamaIlqt/kU+L0hGD3/XVG7Ez9Yoqm+953rg05+MKRbO1lCrTarH6hm7ySx7rqWURKbE=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:59962 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1vx8fW-0007Wl-Dj; Mon, 02 Mar 2026 14:11:03 -0500 From: Hugo Villeneuve To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, shawnguo@kernel.org, laurent.pinchart+renesas@ideasonboard.com, antonin.godard@bootlin.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, hugo@hugovil.com, Hugo Villeneuve Date: Mon, 2 Mar 2026 14:03:48 -0500 Message-ID: <20260302190953.669325-13-hugo@hugovil.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302190953.669325-1-hugo@hugovil.com> References: <20260302190953.669325-1-hugo@hugovil.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: [PATCH 12/14] ARM: dts: imx6ul-var-som: factor out audio support X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Not all boards use the audio codec, so factor out this functionality to a separate DTSI include file. Signed-off-by: Hugo Villeneuve --- .../dts/nxp/imx/imx6ul-var-som-audio.dtsi | 30 +++++++++++++++++++ .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 21 ------------- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 1 + .../nxp/imx/imx6ull-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 1 + 6 files changed, 34 insertions(+), 21 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi b/arch/arm= /boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi new file mode 100644 index 0000000000000..3c480bc7a6ad8 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Audio support for Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +&iomuxc { + pinctrl_sai2: sai2grp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; +}; + +&sai2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sai2>; + assigned-clocks =3D <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents =3D <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates =3D <0>, <12288000>; + fsl,sai-mclk-direction-output; + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/ar= m/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index 70d19eccddb4c..5600eeaa5854d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -52,16 +52,6 @@ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 >; }; =20 - pinctrl_sai2: sai2grp { - fsl,pins =3D < - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - >; - }; - pinctrl_tsc: tscgrp { fsl,pins =3D < MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 @@ -163,17 +153,6 @@ &pxp { status =3D "okay"; }; =20 -&sai2 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_sai2>; - assigned-clocks =3D <&clks IMX6UL_CLK_SAI2_SEL>, - <&clks IMX6UL_CLK_SAI2>; - assigned-clock-parents =3D <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates =3D <0>, <12288000>; - fsl,sai-mclk-direction-output; - status =3D "okay"; -}; - &snvs_poweroff { status =3D "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts index b5e6a3306e1cd..64a3cbd8b7c38 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -13,6 +13,7 @@ #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-enet1.dtsi" +#include "imx6ul-var-som-audio.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/a= rm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index d0adcd0e80833..f014ee66e18cb 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -13,6 +13,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-sd.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-audio.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/= arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts index 86f558c76fb3e..2e1f75d5f25a6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -13,6 +13,7 @@ #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-enet1.dtsi" +#include "imx6ul-var-som-audio.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/= arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts index f9bc6a9a5c1be..0d0613e3a34f2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-sd.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-audio.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; 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Mon, 02 Mar 2026 14:11:04 -0500 From: Hugo Villeneuve To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, shawnguo@kernel.org, laurent.pinchart+renesas@ideasonboard.com, antonin.godard@bootlin.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, hugo@hugovil.com, Hugo Villeneuve Date: Mon, 2 Mar 2026 14:03:49 -0500 Message-ID: <20260302190953.669325-14-hugo@hugovil.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302190953.669325-1-hugo@hugovil.com> References: <20260302190953.669325-1-hugo@hugovil.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: [PATCH 13/14] dt-bindings: display/lvds-codec: add ti,sn65lvds93 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Add compatible string for TI SN65LVDS93. Similar to SN65LVDS83 but with an industrial temperature range. Signed-off-by: Hugo Villeneuve --- Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-codec.ya= ml b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml index 4f52e35d02537..f2cb74b86cc05 100644 --- a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml @@ -37,6 +37,7 @@ properties: - ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer - ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer - ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter + - ti,sn75lvds93 # For the TI SN75LVDS93 FlatLink transmitter - const: lvds-encoder # Generic LVDS encoder compatible fallback - items: - enum: --=20 2.47.3 From nobody Tue Mar 3 03:38:36 2026 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EF42379ECC; Mon, 2 Mar 2026 19:11:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.120.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478687; cv=none; b=ADv/EKPFgXMqj0YlYlZZJ9VbrrXUigWyY2CEEnc4z5sr0aeQrqPlt95nwxOZe6A3QlHa0Pp6owXtrsKemxp90OoRwENzPgsdW/PS4Nl/lD35qJfrG7ch9kYPTFmGZ1YxiXY+aFNdG1jwESUYtob++lvtj7T8IfQtEz/8WTt4rUI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772478687; c=relaxed/simple; bh=MmIPxr6/HfB3NDzoicCmQyhvewGDjfMdY6unMOqSvdw=; h=From:To:Cc:Date:Message-ID:In-Reply-To:References:MIME-Version: Subject; b=PJwQ2m0cubnL6pLxu5SMtk5I3YQkuOng7IbSf5dWFKeucX6fAUbDOmdDctKU89/Il8/KNt63uWidqOxjkBdta+Pb9tTgVGdjI44t0Fs5CDiIPpl0oZ0+nGn+mN/UXfIdhcxNIpY05t79OiB8KooNwJgHzgBT2oKNyW42dlH9nCc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com; spf=pass smtp.mailfrom=hugovil.com; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b=ZmV7KRJo; arc=none smtp.client-ip=162.243.120.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=hugovil.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=hugovil.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=hugovil.com header.i=@hugovil.com header.b="ZmV7KRJo" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Cc:To :From:subject:date:message-id:reply-to; bh=HOoJmWe2h0lSbumvsX2QPmYQIgLBRq/iMywn4k+tB1U=; b=ZmV7KRJo6W3CvYoZXALdYF4wLM 4tFTyR97yGRLlGllCUOD2ZkYuM+0Kj/38MEtExcmgWC8lmF4CVY+Obnp9AM3YbPdlGJCHwmWXJlXr Bn/aKhlDaUHgrf5qzAcztQ5V9sBPGqoNHiRcFMf4tBe/RZ+cRYKILWdp+kMedq+EJgB8=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:59962 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1vx8fa-0007Wl-HB; Mon, 02 Mar 2026 14:11:07 -0500 From: Hugo Villeneuve To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, Frank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, shawnguo@kernel.org, laurent.pinchart+renesas@ideasonboard.com, antonin.godard@bootlin.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, hugo@hugovil.com, Hugo Villeneuve Date: Mon, 2 Mar 2026 14:03:50 -0500 Message-ID: <20260302190953.669325-15-hugo@hugovil.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302190953.669325-1-hugo@hugovil.com> References: <20260302190953.669325-1-hugo@hugovil.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com X-Spam-Level: X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: [PATCH 14/14] ARM: dts: imx6ul-var-som: add support for LVDS display panel X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Content-Type: text/plain; charset="utf-8" From: Hugo Villeneuve Add support for the LD configuration option (LVDS encoder assembled on SOM) so that the LVDS display panel on the concerto EVK board now works properly. Not all VAR-SOM-6UL SOMs have the LD configuration optionso factor out this functionality to a separate DTSI file. Signed-off-by: Hugo Villeneuve --- .../imx/imx6ul-var-som-concerto-common.dtsi | 35 ++++-- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 1 + .../nxp/imx/imx6ul-var-som-lvds-panel.dtsi | 112 ++++++++++++++++++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 1 + 6 files changed, 139 insertions(+), 12 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi = b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index 107b1d0fe7827..658cec2f4d026 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -44,6 +44,29 @@ led-0 { linux,default-trigger =3D "heartbeat"; }; }; + + lvds_panel: lvds-panel { + compatible =3D "sgd,gktw70sdae4se", "panel-lvds"; + data-mapping =3D "jeida-18"; + width-mm =3D <153>; + height-mm =3D <86>; + + panel-timing { + clock-frequency =3D <35000000>; + hactive =3D <800>; + vactive =3D <480>; + hback-porch =3D <40>; + hfront-porch =3D <40>; + vback-porch =3D <29>; + vfront-porch =3D <13>; + hsync-len =3D <48>; + vsync-len =3D <3>; + hsync-active =3D <0>; + vsync-active =3D <0>; + de-active =3D <1>; + pixelclk-active =3D <0>; + }; + }; }; =20 &can1 { @@ -98,12 +121,6 @@ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ >; }; =20 - pinctrl_pwm4: pwm4grp { - fsl,pins =3D < - MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 - >; - }; - pinctrl_rtc: rtcgrp { fsl,pins =3D < MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */ @@ -139,12 +156,6 @@ MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 }; }; =20 -&pwm4 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_pwm4>; - status =3D "okay"; -}; - &snvs_pwrkey { status =3D "disabled"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts index 64a3cbd8b7c38..725f34d6b7ee9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -14,6 +14,7 @@ #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-enet1.dtsi" #include "imx6ul-var-som-audio.dtsi" +#include "imx6ul-var-som-lvds-panel.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/a= rm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index f014ee66e18cb..e9e4b6882bca8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -14,6 +14,7 @@ #include "imx6ul-var-som-sd.dtsi" #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-audio.dtsi" +#include "imx6ul-var-som-lvds-panel.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi b/arc= h/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi new file mode 100644 index 0000000000000..996b37d35d6e0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * LVDS panel support for Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +/ { + lcd_backlight: lcd-backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&pwm4 0 2000000 0>; + pwm-names =3D "LCD_BKLT_PWM"; + brightness-levels =3D <0 4 8 16 32 64 128 255>; + default-brightness-level =3D <6>; + status =3D "okay"; + }; + + lvds_encoder: lvds-encoder { + compatible =3D "ti,sn75lvds93", "lvds-encoder"; + power-supply =3D <®_3p3v>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + lvds_enc_in: endpoint { + remote-endpoint =3D <&lcdif_out>; + }; + }; + + port@1 { + reg =3D <1>; + + lvds_enc_out: endpoint { + remote-endpoint =3D <&lvds_panel_in>; + }; + }; + }; + }; +}; + +&iomuxc { + pinctrl_lcdif_ctrl: lcdif-ctrl-grp { + fsl,pins =3D < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdif-dat-grp { + fsl,pins =3D < + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_pwm4: pwm4-grp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 /* LCD BACKLIGHT */ + >; + }; +}; + +&lcdif { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + status =3D "okay"; + + port { + lcdif_out: endpoint { + remote-endpoint =3D <&lvds_enc_in>; + }; + }; +}; + +&lvds_panel { + status =3D "okay"; + + port { + lvds_panel_in: endpoint { + remote-endpoint =3D <&lvds_enc_out>; + }; + }; +}; + +/* PWM LCD */ +&pwm4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm4>; + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/= arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts index 2e1f75d5f25a6..1b7c1a3383eec 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -14,6 +14,7 @@ #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-enet1.dtsi" #include "imx6ul-var-som-audio.dtsi" +#include "imx6ul-var-som-lvds-panel.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/= arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts index 0d0613e3a34f2..7d032e17134a7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -13,6 +13,7 @@ #include "imx6ul-var-som-sd.dtsi" #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-audio.dtsi" +#include "imx6ul-var-som-lvds-panel.dtsi" =20 / { model =3D "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; --=20 2.47.3