From nobody Tue Mar 3 03:21:03 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33D7F42EEDF; Mon, 2 Mar 2026 17:52:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772473948; cv=none; b=s4YINt+NDyu62VL8m1+o+y4lPmB2+cwt8d8+uqjpU4om0IS8EHMh9cld/IwZvsNgd1uK2TTvMIzNyQLChM9s2E5YXCFML9vJrDMxIyzH+oUF6jEMhUWXn9j2kKN6oiPnsE/TeT6BoVQegq0DPlEsbJgNl2+CAmr97EVKydqUbPo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772473948; c=relaxed/simple; bh=o6KNAMJkeJ8gWUg6Dn3wv9fLduaTjNYGqRgc1eRuoU0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=H5T43QfnEmxFvNa/1gz2PZ7anVj7zbrLpjUkhgP2lYhBhjBtodLaJEbBLIYvCs6/8wJ/r5/3yDetU/Ry5XT3cwtrlrcAVUg+4OGpZgPgsiUnTeWkkO4YleHcpRb6as55ZYY9VXfDzQhUiSrsEbLLAk2VJHPbBTnbFu8Yf6kQo38= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=fWxihdj5; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="fWxihdj5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772473946; x=1804009946; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o6KNAMJkeJ8gWUg6Dn3wv9fLduaTjNYGqRgc1eRuoU0=; b=fWxihdj5Dij4XrLjWAj+PJFRAAstO4d3Lg9/vzSqcqsktTyH2oYAGp8w 3XOhDBBYYXoRJ1v2U5b77t7A7PZ2HthNgC+wye3xzQedyOs4WrX/441xi tBVIpow2TpAmvPH0Cou49HDQnD/+zfAmlT+QwdaqSU/PosGrGpVxFRQXL 0N3gPfFzojQXJ+wx8qLeapGqTMEziYCi7hXenHXr+kmiO94pVgldVIigL xesJtYvvUS327kXpYYHJ1eZWmmRLwXLIVr6dsM4Qg/oT59wPIEPPV+lZH zScNB7BnYxboQQFyyMTmUf27DOzs+qq4itKFU8k1e9hCVHQkaIjOHQ6kR w==; X-CSE-ConnectionGUID: wO1pv2HNSs2qKS2Pvp2+tw== X-CSE-MsgGUID: ZAG+MItLRnqi3bgOxRLHZQ== X-IronPort-AV: E=McAfee;i="6800,10657,11717"; a="77356715" X-IronPort-AV: E=Sophos;i="6.21,320,1763452800"; d="scan'208";a="77356715" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2026 09:52:25 -0800 X-CSE-ConnectionGUID: 4qu+ZdbvT7W8nfs6sbcKWw== X-CSE-MsgGUID: oEIiBwmmQ9uOSxeM1mUmrQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,320,1763452800"; d="scan'208";a="248238379" Received: from intel-nuc8i7beh.iind.intel.com ([10.223.163.35]) by orviesa002.jf.intel.com with ESMTP; 02 Mar 2026 09:52:21 -0800 From: Arun T To: arun.t@intel.com Cc: sakari.ailus@iki.fi, sakari.ailus@intel.com, sakari.ailus@linux.intel.com, arec.kao@intel.com, ilpo.jarvinen@linux.intel.com, dan.scally@ideasonboard.com, platform-driver-x86@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, mehdi.djait@intel.com Subject: [PATCH v3 1/2] platform/x86: int3472: Add TPS68470 board data for Intel nvl Date: Mon, 2 Mar 2026 23:16:43 +0530 Message-ID: <20260302174644.1258718-2-arun.t@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260302174644.1258718-1-arun.t@intel.com> References: <20260130092431.2335363-2-arun.t@intel.com> <20260302174644.1258718-1-arun.t@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Intel NVL platform uses IPU8 is powered by a TPS68470 PMIC,requiring bo= ard data to configure the GPIOs and regulators for proper camera sensor operati= on. Signed-off-by: Arun T --- .../x86/intel/int3472/tps68470_board_data.c | 150 ++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/drivers/platform/x86/intel/int3472/tps68470_board_data.c b/dri= vers/platform/x86/intel/int3472/tps68470_board_data.c index 71357a036292..1efc0f8e9ba8 100644 --- a/drivers/platform/x86/intel/int3472/tps68470_board_data.c +++ b/drivers/platform/x86/intel/int3472/tps68470_board_data.c @@ -143,6 +143,34 @@ static struct regulator_consumer_supply int3479_aux2_c= onsumer_supplies[] =3D { REGULATOR_SUPPLY("dovdd", "i2c-INT3479:00"), }; =20 +/* Settings for Intel NVL platform */ + +static struct regulator_consumer_supply int3472_core_consumer_supplies[] = =3D { + REGULATOR_SUPPLY("dvdd", "i2c-OVTI13B1:00"), +}; + +static struct regulator_consumer_supply int3472_ana_consumer_supplies[] = =3D { + REGULATOR_SUPPLY("ana", "i2c-OVTI13B1:00"), +}; + +static struct regulator_consumer_supply int3472_vcm_consumer_supplies[] = =3D { + REGULATOR_SUPPLY("vdd", "i2c-OVTI13B1:00"), +}; + +static struct regulator_consumer_supply int3472_vsio_consumer_supplies[] = =3D { + REGULATOR_SUPPLY("dovdd", "i2c-OVTI13B1:00"), + REGULATOR_SUPPLY("vsio", "i2c-OVTI13B1:00"), + REGULATOR_SUPPLY("vddd", "i2c-OVTI13B1:00"), +}; + +static struct regulator_consumer_supply int3472_aux1_consumer_supplies[] = =3D { + REGULATOR_SUPPLY("vdda", "i2c-OVTI13B1:00"), +}; + +static struct regulator_consumer_supply int3472_aux2_consumer_supplies[] = =3D { + REGULATOR_SUPPLY("vdddo", "i2c-OVTI13B1:00"), +}; + static const struct regulator_init_data dell_7212_tps68470_core_reg_init_d= ata =3D { .constraints =3D { .min_uV =3D 1200000, @@ -220,6 +248,82 @@ static const struct regulator_init_data dell_7212_tps6= 8470_aux2_reg_init_data =3D .consumer_supplies =3D int3479_aux2_consumer_supplies, }; =20 +static const struct regulator_init_data intel_nvl_tps68470_core_reg_init_d= ata =3D { + .constraints =3D { + .min_uV =3D 1200000, + .max_uV =3D 1200000, + .apply_uV =3D true, + .always_on =3D true, + }, + .num_consumer_supplies =3D ARRAY_SIZE(int3472_core_consumer_supplies), + .consumer_supplies =3D int3472_core_consumer_supplies, +}; + +static const struct regulator_init_data intel_nvl_tps68470_ana_reg_init_da= ta =3D { + .constraints =3D { + .min_uV =3D 2815200, + .max_uV =3D 2815200, + .apply_uV =3D true, + .always_on =3D true, + }, + .num_consumer_supplies =3D ARRAY_SIZE(int3472_ana_consumer_supplies), + .consumer_supplies =3D int3472_ana_consumer_supplies, +}; + +static const struct regulator_init_data intel_nvl_tps68470_vcm_reg_init_da= ta =3D { + .constraints =3D { + .min_uV =3D 2815200, + .max_uV =3D 2815200, + .apply_uV =3D true, + .always_on =3D true, + }, + .num_consumer_supplies =3D ARRAY_SIZE(int3472_vcm_consumer_supplies), + .consumer_supplies =3D int3472_vcm_consumer_supplies, +}; + +/* Ensure the always-on VIO regulator has the same voltage as VSIO */ +static const struct regulator_init_data intel_nvl_tps68470_vio_reg_init_da= ta =3D { + .constraints =3D { + .min_uV =3D 1800600, + .max_uV =3D 1800600, + .apply_uV =3D true, + .always_on =3D true, + }, +}; + +static const struct regulator_init_data intel_nvl_tps68470_vsio_reg_init_d= ata =3D { + .constraints =3D { + .min_uV =3D 1800600, + .max_uV =3D 1800600, + .apply_uV =3D true, + .always_on =3D true, + }, + .num_consumer_supplies =3D ARRAY_SIZE(int3472_vsio_consumer_supplies), + .consumer_supplies =3D int3472_vsio_consumer_supplies, +}; + +static const struct regulator_init_data intel_nvl_tps68470_aux1_reg_init_d= ata =3D { + .constraints =3D { + .min_uV =3D 2815200, + .max_uV =3D 2815200, + .apply_uV =3D 1, + .valid_ops_mask =3D REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies =3D ARRAY_SIZE(int3472_aux1_consumer_supplies), + .consumer_supplies =3D int3472_aux1_consumer_supplies, +}; + +static const struct regulator_init_data intel_nvl_tps68470_aux2_reg_init_d= ata =3D { + .constraints =3D { + .min_uV =3D 1800600, + .max_uV =3D 1800600, + .apply_uV =3D 1, + .valid_ops_mask =3D REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies =3D ARRAY_SIZE(int3472_aux2_consumer_supplies), + .consumer_supplies =3D int3472_aux2_consumer_supplies, +}; + static const struct tps68470_regulator_platform_data dell_7212_tps68470_pd= ata =3D { .reg_init_data =3D { [TPS68470_CORE] =3D &dell_7212_tps68470_core_reg_init_data, @@ -232,6 +336,18 @@ static const struct tps68470_regulator_platform_data d= ell_7212_tps68470_pdata =3D }, }; =20 +static const struct tps68470_regulator_platform_data intel_nvl_tps68470_pd= ata =3D { + .reg_init_data =3D { + [TPS68470_CORE] =3D &intel_nvl_tps68470_core_reg_init_data, + [TPS68470_ANA] =3D &intel_nvl_tps68470_ana_reg_init_data, + [TPS68470_VCM] =3D &intel_nvl_tps68470_vcm_reg_init_data, + [TPS68470_VIO] =3D &intel_nvl_tps68470_vio_reg_init_data, + [TPS68470_VSIO] =3D &intel_nvl_tps68470_vsio_reg_init_data, + [TPS68470_AUX1] =3D &intel_nvl_tps68470_aux1_reg_init_data, + [TPS68470_AUX2] =3D &intel_nvl_tps68470_aux2_reg_init_data, + }, +}; + static struct gpiod_lookup_table surface_go_int347a_gpios =3D { .dev_id =3D "i2c-INT347A:00", .table =3D { @@ -258,6 +374,23 @@ static struct gpiod_lookup_table dell_7212_int3479_gpi= os =3D { } }; =20 +static struct gpiod_lookup_table intel_nvl_int347a_gpios =3D { + .dev_id =3D "i2c-OVTI13B1:01", + .table =3D { + GPIO_LOOKUP("tps68470-gpio", 9, "reset", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("tps68470-gpio", 8, "s_idle", GPIO_ACTIVE_LOW), + { } + } +}; + +static struct gpiod_lookup_table intel_nvl_int347e_gpios =3D { + .dev_id =3D "i2c-OVTI13B1:01", + .table =3D { + GPIO_LOOKUP("tps68470-gpio", 7, "s_enable", GPIO_ACTIVE_LOW), + { } + } +}; + static const struct int3472_tps68470_board_data surface_go_tps68470_board_= data =3D { .dev_name =3D "i2c-INT3472:05", .tps68470_regulator_pdata =3D &surface_go_tps68470_pdata, @@ -287,6 +420,16 @@ static const struct int3472_tps68470_board_data dell_7= 212_tps68470_board_data =3D }, }; =20 +static const struct int3472_tps68470_board_data intel_nvl_tps68470_board_d= ata =3D { + .dev_name =3D "i2c-INT3472:04", + .tps68470_regulator_pdata =3D &intel_nvl_tps68470_pdata, + .n_gpiod_lookups =3D 2, + .tps68470_gpio_lookup_tables =3D { + &intel_nvl_int347a_gpios, + &intel_nvl_int347e_gpios, + }, +}; + static const struct dmi_system_id int3472_tps68470_board_data_table[] =3D { { .matches =3D { @@ -316,6 +459,13 @@ static const struct dmi_system_id int3472_tps68470_boa= rd_data_table[] =3D { }, .driver_data =3D (void *)&dell_7212_tps68470_board_data, }, + { + .matches =3D { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Intel Corporation"), + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Nova Lake Client Platform"), + }, + .driver_data =3D (void *)&intel_nvl_tps68470_board_data, + }, { } }; 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X-CSE-ConnectionGUID: aGSxkvpRQn+oHQUZz2XhCA== X-CSE-MsgGUID: rZzKkmgCRwSoUbNpLIObKg== X-IronPort-AV: E=McAfee;i="6800,10657,11717"; a="77356740" X-IronPort-AV: E=Sophos;i="6.21,320,1763452800"; d="scan'208";a="77356740" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2026 09:52:30 -0800 X-CSE-ConnectionGUID: NSUtNXDPR1WvG1W5D1Q4ag== X-CSE-MsgGUID: jp2UtXLmTlqomU+W79njyQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,320,1763452800"; d="scan'208";a="248238385" Received: from intel-nuc8i7beh.iind.intel.com ([10.223.163.35]) by orviesa002.jf.intel.com with ESMTP; 02 Mar 2026 09:52:27 -0800 From: Arun T To: arun.t@intel.com Cc: sakari.ailus@iki.fi, sakari.ailus@intel.com, sakari.ailus@linux.intel.com, arec.kao@intel.com, ilpo.jarvinen@linux.intel.com, dan.scally@ideasonboard.com, platform-driver-x86@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, mehdi.djait@intel.com Subject: [PATCH v3 2/2] media: i2c: ov13b10: support tps68470 regulator and gpio Date: Mon, 2 Mar 2026 23:16:44 +0530 Message-ID: <20260302174644.1258718-3-arun.t@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260302174644.1258718-1-arun.t@intel.com> References: <20260130092431.2335363-2-arun.t@intel.com> <20260302174644.1258718-1-arun.t@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The OV13B10 sensor obtains clock and regulators from the TPS68470 PMIC. Add TPS68470 regulator and GPIO names to the sensor power on Signed-off-by: Arun T --- drivers/media/i2c/ov13b10.c | 48 +++++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/drivers/media/i2c/ov13b10.c b/drivers/media/i2c/ov13b10.c index 5421874732bc..d678d0d49266 100644 --- a/drivers/media/i2c/ov13b10.c +++ b/drivers/media/i2c/ov13b10.c @@ -3,6 +3,7 @@ =20 #include #include +#include #include #include #include @@ -699,6 +700,13 @@ static const struct ov13b10_mode supported_2_lanes_mod= es[] =3D { }, }; =20 +static const char * const ov13b10_supply_names[] =3D { + "dovdd", /* Digital I/O power */ + "avdd", /* Analog power */ + "dvdd", /* Digital core power */ + "vdd", /* Vcm power */ +}; + struct ov13b10 { struct device *dev; =20 @@ -708,7 +716,7 @@ struct ov13b10 { struct v4l2_ctrl_handler ctrl_handler; =20 struct clk *img_clk; - struct regulator *avdd; + struct regulator_bulk_data supplies[ARRAY_SIZE(ov13b10_supply_names)]; struct gpio_desc *reset; =20 /* V4L2 Controls */ @@ -1194,9 +1202,8 @@ static int ov13b10_power_off(struct device *dev) struct ov13b10 *ov13b10 =3D to_ov13b10(sd); =20 gpiod_set_value_cansleep(ov13b10->reset, 1); - - if (ov13b10->avdd) - regulator_disable(ov13b10->avdd); + regulator_bulk_disable(ARRAY_SIZE(ov13b10_supply_names), + ov13b10->supplies); =20 clk_disable_unprepare(ov13b10->img_clk); =20 @@ -1214,14 +1221,12 @@ static int ov13b10_power_on(struct device *dev) dev_err(dev, "failed to enable imaging clock: %d", ret); return ret; } - - if (ov13b10->avdd) { - ret =3D regulator_enable(ov13b10->avdd); - if (ret < 0) { - dev_err(dev, "failed to enable avdd: %d", ret); - clk_disable_unprepare(ov13b10->img_clk); - return ret; - } + ret =3D regulator_bulk_enable(ARRAY_SIZE(ov13b10_supply_names), + ov13b10->supplies); + if (ret < 0) { + dev_err(dev, "failed to enable regulators\n"); + clk_disable_unprepare(ov13b10->img_clk); + return ret; } =20 gpiod_set_value_cansleep(ov13b10->reset, 0); @@ -1475,7 +1480,8 @@ static int ov13b10_get_pm_resources(struct ov13b10 *o= v13b) unsigned long freq; int ret; =20 - ov13b->reset =3D devm_gpiod_get_optional(ov13b->dev, "reset", GPIOD_OUT_L= OW); + ov13b->reset =3D devm_gpiod_get_optional(ov13b->dev, "reset", + GPIOD_OUT_LOW); if (IS_ERR(ov13b->reset)) return dev_err_probe(ov13b->dev, PTR_ERR(ov13b->reset), "failed to get reset gpio\n"); @@ -1491,15 +1497,15 @@ static int ov13b10_get_pm_resources(struct ov13b10 = *ov13b) "external clock %lu is not supported\n", freq); =20 - ov13b->avdd =3D devm_regulator_get_optional(ov13b->dev, "avdd"); - if (IS_ERR(ov13b->avdd)) { - ret =3D PTR_ERR(ov13b->avdd); - ov13b->avdd =3D NULL; - if (ret !=3D -ENODEV) - return dev_err_probe(ov13b->dev, ret, - "failed to get avdd regulator\n"); - } + for (unsigned int i =3D 0; i < ARRAY_SIZE(ov13b10_supply_names); i++) + ov13b->supplies[i].supply =3D ov13b10_supply_names[i]; =20 + ret =3D devm_regulator_bulk_get(ov13b->dev, + ARRAY_SIZE(ov13b10_supply_names), + ov13b->supplies); + if (ret) + return dev_err_probe(ov13b->dev, ret, + "failed to get regulators\n"); return 0; } =20 --=20 2.43.0