From nobody Thu Apr 9 15:03:44 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B206D426ED8; Mon, 2 Mar 2026 16:55:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772470520; cv=none; b=O5o6OxwTPKoHHmFoBIzxArx91+GgTECCieRPYYzyNQuz+6P8K5co7LKbT75qJ9ajWNXsSrOJypDUbJyZO/CDHm5WrQAffm0LFmQau3rtVSyAueWNdVDPoeQOw4a61ydpFdLT0nCnO1DECVS0jm0TksVARNGAnNL3zQ/WWaa+Pkk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772470520; c=relaxed/simple; bh=2DzucrKG4zpsK64G4zyQD5GDxLL1K1SQgMCNfYELczA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rp6tsNyYt/SD0ffyC0SM48xRRdpmfE7dJm0jnXUeRjK79l9gOrMgZqjHq5b6l1WAMsBEBm/E9GcU9exRguQoGsfBG0Lnrgzm6JNv0KFtxTK7t1pFBJRoMEo8RpRzjdjaFknWOQnH17pogAuP1wDCcg/Gaz1xOVr9qCJxs5bS5N0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: wIcKGcpETrWLYpPyNcX5gA== X-CSE-MsgGUID: hHhSlcrvTd2bpaA7jF3w2w== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 03 Mar 2026 01:55:15 +0900 Received: from vm01.adwin.renesas.com (unknown [10.226.92.15]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 8C1AA401C226; Tue, 3 Mar 2026 01:55:11 +0900 (JST) From: Ovidiu Panait To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, biju.das.jz@bp.renesas.com, fabrizio.castro.jz@renesas.com Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 6/7] clk: versaclock3: Add freerunning 32.768kHz clock support Date: Mon, 2 Mar 2026 16:54:40 +0000 Message-ID: <20260302165441.4457-7-ovidiu.panait.rb@renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260302165441.4457-1-ovidiu.panait.rb@renesas.com> References: <20260302165441.4457-1-ovidiu.panait.rb@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Versa 3 clock generator has an internal 32.768kHz oscillator that can be routed to the SE1, SE2 and SE3 outputs. This patch exposes it as a fixed-rate clock and makes it available as a parent for the SE1/SE2/SE3 muxes. The 32.768kHz clock is only intended to be used when explicitly requested (i.e. when a rate of exactly 32768Hz is set). Selecting it as a fallback for other rates can cause issues, for example in audio configurations. To enforce this, introduce a new helper function, _vc3_clk_mux_determine_rate() which rejects configurations where the 32.768kHz parent would otherwise be chosen implicitly. One new field is added to struct vc3_clk_data - clk_32k_bitmsk, which is the bit mask used for selecting the 32.768kHz oscillator as output. It is used by clk_mux callbacks to select the appropriate parent clock. Signed-off-by: Ovidiu Panait --- v4 changes: - Used the I2C device name instead of device tree node name to make the 32k clk name globally unique. v3 changes: - Rebased the patch to match the new clock registration logic and dropped the 32k clock parent index number (clk_32k_index). drivers/clk/clk-versaclock3.c | 96 +++++++++++++++++++++++++++++++---- 1 file changed, 86 insertions(+), 10 deletions(-) diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c index eb25100bb0aa..d8abb665e642 100644 --- a/drivers/clk/clk-versaclock3.c +++ b/drivers/clk/clk-versaclock3.c @@ -69,8 +69,10 @@ #define VC3_OUTPUT_CTR_DIV4_SRC_SEL BIT(3) =20 #define VC3_SE2_CTRL_REG0 0x1f +#define VC3_SE2_CTRL_REG0_SE2_FREERUN_32K BIT(7) =20 #define VC3_SE3_DIFF1_CTRL_REG 0x21 +#define VC3_SE3_DIFF1_CTRL_REG_SE3_FREERUN_32K BIT(7) #define VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL BIT(6) =20 #define VC3_DIFF1_CTRL_REG 0x22 @@ -80,6 +82,7 @@ #define VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL BIT(7) =20 #define VC3_SE1_DIV4_CTRL 0x24 +#define VC3_SE1_DIV4_CTRL_SE1_FREERUN_32K BIT(4) #define VC3_SE1_DIV4_CTRL_SE1_CLK_SEL BIT(3) =20 #define VC3_PLL1_VCO_MIN 300000000UL @@ -91,6 +94,8 @@ #define VC3_2_POW_16 (U16_MAX + 1) #define VC3_DIV_MASK(width) ((1 << (width)) - 1) =20 +#define VC3_CLK_32K_FREQ 32768 + #define VC3_CLK_PARENT(t, i) { .type =3D VC3_CLK_##t, .idx =3D (i) } =20 enum vc3_pfd_mux { @@ -149,6 +154,7 @@ enum vc3_clk_type { VC3_CLK_DIV_MUX, VC3_CLK_DIV, VC3_CLK_CLK_MUX, + VC3_CLK_32K, }; =20 struct vc3_clk_parent { @@ -164,6 +170,7 @@ struct vc3_parent_info { struct vc3_clk_data { u8 offs; u8 bitmsk; + u8 clk_32k_bitmsk; }; =20 struct vc3_pfd_data { @@ -217,6 +224,7 @@ struct vc3_device_data { struct vc3_hw_data clk_div_mux[VC3_DIV_MUX_NUM]; struct vc3_hw_data clk_div[VC3_DIV_NUM]; struct vc3_hw_data clk_mux[VC3_CLK_MUX_NUM]; + struct clk_hw *clk_32k; struct clk_hw *clk_out[VC3_CLK_OUT_NUM]; }; =20 @@ -587,19 +595,52 @@ static const struct clk_ops vc3_div_ops =3D { .set_rate =3D vc3_div_set_rate, }; =20 +static int vc3_get_32k_parent_index(const struct vc3_hw_data *hw_data) +{ + const struct vc3_parent_info *pinfo =3D hw_data->parent_info; + + for (int i =3D 0; i < pinfo->num_parents; i++) { + if (pinfo->parents[i].type =3D=3D VC3_CLK_32K) + return i; + } + + return -1; +} + +static int _vc3_clk_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + bool is_32k_req =3D (req->rate =3D=3D VC3_CLK_32K_FREQ); + struct clk_rate_request tmp_req; + int ret; + + clk_hw_init_rate_request(hw, &tmp_req, req->rate); + + ret =3D clk_mux_determine_rate_flags(hw, &tmp_req, CLK_SET_RATE_PARENT); + if (ret) + return ret; + + /* Select the 32.768 kHz parent only when explicitly requested. */ + if ((tmp_req.best_parent_rate =3D=3D VC3_CLK_32K_FREQ) && !is_32k_req) + return -EINVAL; + + memcpy(req, &tmp_req, sizeof(*req)); + + return 0; +} + static int vc3_clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { int frc; =20 - if (clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT)) { + if (_vc3_clk_mux_determine_rate(hw, req)) { /* The below check is equivalent to (best_parent_rate/rate) */ if (req->best_parent_rate >=3D req->rate) { frc =3D DIV_ROUND_CLOSEST_ULL(req->best_parent_rate, req->rate); req->rate *=3D frc; - return clk_mux_determine_rate_flags(hw, req, - CLK_SET_RATE_PARENT); + return _vc3_clk_mux_determine_rate(hw, req); } } =20 @@ -610,10 +651,15 @@ static u8 vc3_clk_mux_get_parent(struct clk_hw *hw) { struct vc3_hw_data *vc3 =3D container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *clk_mux =3D vc3->data; + int clk_32k_index; u32 val; =20 regmap_read(vc3->regmap, clk_mux->offs, &val); =20 + clk_32k_index =3D vc3_get_32k_parent_index(vc3); + if (clk_32k_index >=3D 0 && !(val & clk_mux->clk_32k_bitmsk)) + return clk_32k_index; + return !!(val & clk_mux->bitmsk); } =20 @@ -621,9 +667,17 @@ static int vc3_clk_mux_set_parent(struct clk_hw *hw, u= 8 index) { struct vc3_hw_data *vc3 =3D container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *clk_mux =3D vc3->data; + unsigned int bitmsk =3D clk_mux->clk_32k_bitmsk; + unsigned int val =3D 0; + int clk_32k_index; + + clk_32k_index =3D vc3_get_32k_parent_index(vc3); + if (index !=3D clk_32k_index) { + bitmsk |=3D clk_mux->bitmsk; + val =3D clk_mux->clk_32k_bitmsk | (index ? clk_mux->bitmsk : 0); + } =20 - return regmap_update_bits(vc3->regmap, clk_mux->offs, clk_mux->bitmsk, - index ? clk_mux->bitmsk : 0); + return regmap_update_bits(vc3->regmap, clk_mux->offs, bitmsk, val); } =20 static const struct clk_ops vc3_clk_mux_ops =3D { @@ -990,22 +1044,25 @@ static const struct vc3_parent_info clk_mux_parents[= ] =3D { .parents =3D (const struct vc3_clk_parent[]) { VC3_CLK_PARENT(DIV, VC3_DIV5), VC3_CLK_PARENT(DIV, VC3_DIV4), + VC3_CLK_PARENT(32K, 0), }, - .num_parents =3D 2, + .num_parents =3D 3, }, [VC3_SE2_MUX] =3D { .parents =3D (const struct vc3_clk_parent[]) { VC3_CLK_PARENT(DIV, VC3_DIV5), VC3_CLK_PARENT(DIV, VC3_DIV4), + VC3_CLK_PARENT(32K, 0), }, - .num_parents =3D 2, + .num_parents =3D 3, }, [VC3_SE3_MUX] =3D { .parents =3D (const struct vc3_clk_parent[]) { VC3_CLK_PARENT(DIV, VC3_DIV2), VC3_CLK_PARENT(DIV, VC3_DIV4), + VC3_CLK_PARENT(32K, 0), }, - .num_parents =3D 2, + .num_parents =3D 3, }, [VC3_DIFF1_MUX] =3D { .parents =3D (const struct vc3_clk_parent[]) { @@ -1027,7 +1084,8 @@ static struct vc3_hw_data clk_mux[] =3D { [VC3_SE1_MUX] =3D { .data =3D &(struct vc3_clk_data) { .offs =3D VC3_SE1_DIV4_CTRL, - .bitmsk =3D VC3_SE1_DIV4_CTRL_SE1_CLK_SEL + .bitmsk =3D VC3_SE1_DIV4_CTRL_SE1_CLK_SEL, + .clk_32k_bitmsk =3D VC3_SE1_DIV4_CTRL_SE1_FREERUN_32K, }, .hw.init =3D &(struct clk_init_data) { .name =3D "se1_mux", @@ -1039,6 +1097,7 @@ static struct vc3_hw_data clk_mux[] =3D { [VC3_SE2_MUX] =3D { .data =3D &(struct vc3_clk_data) { .offs =3D VC3_SE2_CTRL_REG0, + .clk_32k_bitmsk =3D VC3_SE2_CTRL_REG0_SE2_FREERUN_32K, }, .hw.init =3D &(struct clk_init_data) { .name =3D "se2_mux", @@ -1050,7 +1109,8 @@ static struct vc3_hw_data clk_mux[] =3D { [VC3_SE3_MUX] =3D { .data =3D &(struct vc3_clk_data) { .offs =3D VC3_SE3_DIFF1_CTRL_REG, - .bitmsk =3D VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL + .bitmsk =3D VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL, + .clk_32k_bitmsk =3D VC3_SE3_DIFF1_CTRL_REG_SE3_FREERUN_32K, }, .hw.init =3D &(struct clk_init_data) { .name =3D "se3_mux", @@ -1103,6 +1163,8 @@ static struct clk_hw *vc3_clk_get_hw(struct vc3_devic= e_data *vc3, return &vc3->clk_div[parent->idx].hw; case VC3_CLK_CLK_MUX: return &vc3->clk_mux[parent->idx].hw; + case VC3_CLK_32K: + return vc3->clk_32k; } =20 return NULL; @@ -1224,6 +1286,20 @@ static int vc3_probe(struct i2c_client *client) return ret; } =20 + /* Register internal 32.768kHz oscillator */ + name =3D kasprintf(GFP_KERNEL, "%s.clk_32k", dev_name(dev)); + if (!name) + return -ENOMEM; + + vc3->clk_32k =3D devm_clk_hw_register_fixed_rate(dev, name, NULL, 0, + VC3_CLK_32K_FREQ); + kfree(name); + + if (IS_ERR(vc3->clk_32k)) + return dev_err_probe(dev, PTR_ERR(vc3->clk_32k), + "Failed to register %dHz fixed clock\n", + VC3_CLK_32K_FREQ); + /* Register pfd muxes */ for (i =3D 0; i < ARRAY_SIZE(clk_pfd_mux); i++) { name =3D clk_pfd_mux[i].hw.init->name; --=20 2.51.0