From nobody Thu Apr 9 13:22:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F002411619; Mon, 2 Mar 2026 15:36:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772465764; cv=none; b=Dia82no5lE0KfWAqlQJcI56lJYbHboMnW2TDYJ+z92nEAdAyqXBcFAXeKAytx4vAd1Oad6XNVkEoSolnUSkV/oII+tG1lSVjcDnF2vEA9bE6hekrLeon5EbJxlR7KzNjP4BhvGS6jQUvS05cEtsJYIKgxy+REKRrVntpH/oxen8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772465764; c=relaxed/simple; bh=CYDoAqYz0+vG1YQhjmnYaSQHBJESLZPbzW7By0gNSOo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=k64Sm2M9uxe5agLMcsBfSa715f7D+51nxugOrhMUdCKlymiN0e2kajy0/HAUGTO//oBX6lETf50pSQSIHcfLrjMCVpvMaAmdpesSn2yFT6V+DzDUld1Xy9wEG9OCy/yUT4LlPPOv9dOgSvrQ4lKxjc/LoaYqcAPriYTdY2Psavg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Egeu3r5u; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Egeu3r5u" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06CB4C19423; Mon, 2 Mar 2026 15:36:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772465764; bh=CYDoAqYz0+vG1YQhjmnYaSQHBJESLZPbzW7By0gNSOo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Egeu3r5uSdNJbTroxXrYZTsIzdwvS/kLOLoawApPgryLcShe9eV0nus7z5+cCpzz2 YUhZS6tmboo/GQMxAN3a2dU+LY5yuUf2mfzTfoic39T7q9MgvHS6nG0P3Ms+y+uW8C DgDwO0bvQZGN+Gk3sru6L8Z/5w4NblvhElu/C1LBCSBiOP+zAPbZITv91Romuyi4W0 8Pw90etuB6iEYCHEhHH3VxQw8jzAtDua/feEeeQbynK21dN4piIT0tL52DnHxaVG89 Dob2x/UKFCXAu79eu3UbsJ+6P081awMfZMXJclpgQdVaY6XWP0x2EEoYgKMzvnP79L LTZzxts9cSWUQ== Received: by wens.tw (Postfix, from userid 1000) id 188D35F95F; Mon, 02 Mar 2026 23:36:02 +0800 (CST) From: Chen-Yu Tsai To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Mark Brown Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 1/3] spi: dt-bindings: sun6i: Allow Dual SPI and Quad SPI for newer SoCs Date: Mon, 2 Mar 2026 23:35:56 +0800 Message-ID: <20260302153559.3199783-2-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302153559.3199783-1-wens@kernel.org> References: <20260302153559.3199783-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support for Dual SPI and Quad SPI was added to the Linux driver in commit 0605d9fb411f ("spi: sun6i: add quirk for dual and quad SPI modes support") and commit 25453d797d7a ("spi: sun6i: add dual and quad SPI modes support for R329/D1/R528/T113s"). However the binding was never updated to allow these modes. Allow them by adding 2 and 4 to the allowed bus widths for the newer variants. While at it, also add 0 to the allowed bus widths. This signals that RX or TX is not available, i.e. the MISO or MOSI pin is disconnected. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Moved "allOf:" block after "required:" block - Dropped "type:" from child node in conditional block --- .../bindings/spi/allwinner,sun6i-a31-spi.yaml | 29 +++++++++++++++---- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.= yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index a6067030c5ed..6af4ff233158 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Allwinner A31 SPI Controller =20 -allOf: - - $ref: spi-controller.yaml - maintainers: - Chen-Yu Tsai - Maxime Ripard @@ -82,11 +79,11 @@ patternProperties: =20 spi-rx-bus-width: items: - - const: 1 + enum: [0, 1, 2, 4] =20 spi-tx-bus-width: items: - - const: 1 + enum: [0, 1, 2, 4] =20 required: - compatible @@ -95,6 +92,28 @@ required: - clocks - clock-names =20 +allOf: + - $ref: spi-controller.yaml + - if: + not: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-r329-spi + - allwinner,sun55i-a523-spi + then: + patternProperties: + "^.*@[0-9a-f]+": + properties: + spi-rx-bus-width: + items: + enum: [0, 1] + + spi-tx-bus-width: + items: + enum: [0, 1] + unevaluatedProperties: false =20 examples: --=20 2.47.3 From nobody Thu Apr 9 13:22:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCA5041322B; Mon, 2 Mar 2026 15:36:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772465764; cv=none; b=tsSi+udY5/BfPvgPRu8iNtUxn2dEXsz6jVinj6zmbHEPrAjpVD4KdC3eZy29MJA04eB5l93bd599LTYLcTH/2WjmcbU1J2+HXL/Jgs930zqMQcsJmX6LCfRcWxnPyP4KWHxxyxnXtyKfeF7xK/LmsgnT7Oeyl64Mxi8pmYLpgAE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772465764; c=relaxed/simple; bh=ZFP8AgDDMVfbo9xqlz0itL+nVBZ/DmygRhjGTRlxnaY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VCFEYEei0ulbSPdAW3r44kI7pWyyuUWp+Lw1f5xKFNotzoe9gifEfdNy8DaG8SWmdvwumxkO9LTOUVGErTMdgQFnSuuhM5g1xRV10uy0HmLQYj31Jb386IObRJBBg7GCfTMvHl+Gr/MQHb+7BKRMHqSe1fqKS0zuGw0garH8kbk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TUKUPOKS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TUKUPOKS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52E77C2BCB8; Mon, 2 Mar 2026 15:36:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772465764; bh=ZFP8AgDDMVfbo9xqlz0itL+nVBZ/DmygRhjGTRlxnaY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TUKUPOKSEw2QrjbLIUX5PdGoJl6Zt1RtTXw7ts9d3g/Q4ztW1uVASry/JZs+9lrn8 pQLFpsH3zBYKShW98dRSGnO/LxiOjMfmeJGp7T/IdWo31nDEIvKHYeUHpVblXQlWtW OlwAcqJPgV8N1yQu1bbB9fc8fcxq6npDvA8FMJEt+KFyyayk9m5rK8dtQHfG83zl+7 DjMAYir0Ib2AENMNigw7POnXcKvQA2yJMxQ92tzGppUp67Z007auvaMqGetfhyAiFi Bq6v3VNnaEjtc8WfRX3VnenZyvhKpRHnjVvl75hXzsrVN9VKsiDaaAHXyp20ei7gAb 0Q/d9sW1TOxTQ== Received: by wens.tw (Postfix, from userid 1000) id 210375FF08; Mon, 02 Mar 2026 23:36:02 +0800 (CST) From: Chen-Yu Tsai To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Mark Brown Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH v2 2/3] arm64: dts: allwinner: sun55i-a523: Add pinmux for spi0 on PJ pins Date: Mon, 2 Mar 2026 23:35:57 +0800 Message-ID: <20260302153559.3199783-3-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302153559.3199783-1-wens@kernel.org> References: <20260302153559.3199783-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Avaota A1 board uses spi0 on the PJ pins to connect a SPI NAND chip. Add the full set of pins. Even though this board doesn't use CS1, other boards may do so in the future. Reviewed-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 92aecb90d4e1..da85cecb66c0 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -228,6 +228,13 @@ spi0_pc_pins: spi0-pc-pins { allwinner,pinmux =3D <4>; }; =20 + /omit-if-no-ref/ + spi0_pj_pins: spi0-pj-pins { + pins =3D "PJ21", "PJ22", "PJ23"; + function =3D "spi0"; + allwinner,pinmux =3D <5>; + }; + /omit-if-no-ref/ spi0_cs0_pc_pin: spi0-cs0-pc-pin { pins =3D "PC3"; @@ -235,6 +242,13 @@ spi0_cs0_pc_pin: spi0-cs0-pc-pin { allwinner,pinmux =3D <4>; }; =20 + /omit-if-no-ref/ + spi0_cs0_pj_pin: spi0-cs0-pj-pin { + pins =3D "PJ20"; + function =3D "spi0"; + allwinner,pinmux =3D <5>; + }; + /omit-if-no-ref/ spi0_cs1_pc_pin: spi0-cs1-pc-pin { pins =3D "PC7"; @@ -242,6 +256,13 @@ spi0_cs1_pc_pin: spi0-cs1-pc-pin { allwinner,pinmux =3D <4>; }; =20 + /omit-if-no-ref/ + spi0_cs1_pj_pin: spi0-cs1-pj-pin { + pins =3D "PJ24"; + function =3D "spi0"; + allwinner,pinmux =3D <5>; + }; + /omit-if-no-ref/ spi0_hold_pc_pin: spi0-hold-pc-pin { /* conflicts with eMMC D7 */ @@ -250,6 +271,13 @@ spi0_hold_pc_pin: spi0-hold-pc-pin { allwinner,pinmux =3D <4>; }; =20 + /omit-if-no-ref/ + spi0_hold_pj_pin: spi0-hold-pj-pin { + pins =3D "PJ26"; + function =3D "spi0"; + allwinner,pinmux =3D <5>; + }; + /omit-if-no-ref/ spi0_wp_pc_pin: spi0-wp-pc-pin { /* conflicts with eMMC D2 */ @@ -258,6 +286,13 @@ spi0_wp_pc_pin: spi0-wp-pc-pin { allwinner,pinmux =3D <4>; }; =20 + /omit-if-no-ref/ + spi0_wp_pj_pin: spi0-wp-pj-pin { + pins =3D "PJ25"; + function =3D "spi0"; + allwinner,pinmux =3D <5>; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; allwinner,pinmux =3D <2>; --=20 2.47.3 From nobody Thu Apr 9 13:22:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B465841161B; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YHiUS7wS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4C3EAC4AF0D; Mon, 2 Mar 2026 15:36:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772465764; bh=z/p2kAng0Y5oRilaQCks0dh5WQLuleduc50nf40KO6Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YHiUS7wSLoHxSX4GSlEChP6haEzq9nrYlDDDbes9RRgMy5jutsaPJtocJ6m+CWOo5 S7L3lvsxEvz/ViMWRTKOIhA9gh9Uj5r4SIeYGlT+mx9iNYHH6t7qY5D5Y6SAWtaa2v 05NdAK/svFGTUNNMuESEwtVmC3kLJ5P6W/RuL+uah8Jfw3O3YH30idKxOJZjmXUqU9 cXE4IJlOUGXHL/o9VnFQIeTWe09k8peXTPiF2bO+IAyexKh98WHNTfqF9S+iCIJY1R GOaAB//+NGnpu3qFl9EoPILdYCMsk3E17vCVlHdrXvB0naQMwK0STkUvwHt7GbMv+s D14RAcLsZTX9A== Received: by wens.tw (Postfix, from userid 1000) id 320EB60003; Mon, 02 Mar 2026 23:36:02 +0800 (CST) From: Chen-Yu Tsai To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Mark Brown Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH v2 3/3] arm64: dts: allwinner: sun55i-t527: avaota-a1: Add SPI NAND Date: Mon, 2 Mar 2026 23:35:58 +0800 Message-ID: <20260302153559.3199783-4-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302153559.3199783-1-wens@kernel.org> References: <20260302153559.3199783-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Avaota A1 board has a SPI NAND chip connected to spi0 on the PJ pins with support for QSPI. Enable spi0 and add a device node for the SPI NAND chip. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- .../boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index 7c24121de88f..474354fbfcec 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -403,6 +403,21 @@ &rtc { assigned-clock-rates =3D <32768>; }; =20 +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pj_pins>, <&spi0_cs0_pj_pin>, + <&spi0_hold_pj_pin>, <&spi0_wp_pj_pin>; + status =3D "okay"; + + nand@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + spi-max-frequency =3D <100000000>; + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + }; +}; + &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0_pb_pins>; --=20 2.47.3