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Mon, 2 Mar 2026 04:33:58 -0800 From: Akhil R To: Vinod Koul , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , "Jonathan Hunter" , Laxman Dewangan , Philipp Zabel , , , , CC: Akhil R Subject: [PATCH v2 1/9] dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map property Date: Mon, 2 Mar 2026 18:02:31 +0530 Message-ID: <20260302123239.68441-2-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260302123239.68441-1-akhilrajeev@nvidia.com> References: <20260302123239.68441-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A1:EE_|IA0PR12MB8981:EE_ X-MS-Office365-Filtering-Correlation-Id: 8ee150cf-7da2-41d6-37c7-08de785806ab X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014|7416014|921020; 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charset="utf-8" Add iommu-map property to specify separate stream IDs for each DMA channel. This enables each channel to be in its own IOMMU domain, keeping memory isolated from other devices sharing the same DMA controller. Signed-off-by: Akhil R --- .../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.= yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml index 0dabe9bbb219..1e7b5ddd4658 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -14,6 +14,7 @@ description: | maintainers: - Jon Hunter - Rajesh Gumasta + - Akhil R =20 allOf: - $ref: dma-controller.yaml# @@ -51,6 +52,10 @@ properties: iommus: maxItems: 1 =20 + iommu-map: + minItems: 1 + maxItems: 32 + dma-coherent: true =20 dma-channel-mask: --=20 2.50.1 From nobody Thu Apr 9 12:06:24 2026 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012010.outbound.protection.outlook.com [40.107.209.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99F6C36D9E5; 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charset="utf-8" In Tegra264, GPCDMA reset control is not exposed to Linux and is handled by the boot firmware. Although reset was not exposed in Tegra234 as well, the firmware supported a dummy reset which just returns success on reset without doing an actual reset. This is also not supported in Tegra264 BPMP. Therefore mark 'reset' and 'reset-names' properties as required only for devices prior to Tegra264. This also necessitates that the Tegra264 compatible to be standalone and cannot have the fallback compatible of Tegra186. Since there is no functional impact, we keep reset as required for Tegra234 to avoid breaking the ABI. Signed-off-by: Akhil R --- .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 22 ++++++++++++++----- 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.= yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml index 1e7b5ddd4658..34c9b41aecfc 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -16,16 +16,13 @@ maintainers: - Rajesh Gumasta - Akhil R =20 -allOf: - - $ref: dma-controller.yaml# - properties: compatible: oneOf: + - const: nvidia,tegra264-gpcdma - const: nvidia,tegra186-gpcdma - items: - enum: - - nvidia,tegra264-gpcdma - nvidia,tegra234-gpcdma - nvidia,tegra194-gpcdma - const: nvidia,tegra186-gpcdma @@ -65,12 +62,25 @@ required: - compatible - reg - interrupts - - resets - - reset-names - "#dma-cells" - iommus - dma-channel-mask =20 +allOf: + - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-gpcdma + - nvidia,tegra194-gpcdma + - nvidia,tegra234-gpcdma + then: + required: + - resets + - reset-names + additionalProperties: false =20 examples: --=20 2.50.1 From nobody Thu Apr 9 12:06:24 2026 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010010.outbound.protection.outlook.com [52.101.201.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 404F236E469; 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charset="utf-8" In Tegra264, reset is not available for the driver to control as this is handled by the boot firmware. Hence make the reset control optional and update the error message to reflect the correct error. Signed-off-by: Akhil R Reviewed-by: Frank Li --- drivers/dma/tegra186-gpc-dma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index 4d6fe0efa76e..09a1717aa808 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -1382,10 +1382,10 @@ static int tegra_dma_probe(struct platform_device *= pdev) if (IS_ERR(tdma->base_addr)) return PTR_ERR(tdma->base_addr); =20 - tdma->rst =3D devm_reset_control_get_exclusive(&pdev->dev, "gpcdma"); + tdma->rst =3D devm_reset_control_get_optional_exclusive(&pdev->dev, "gpcd= ma"); if (IS_ERR(tdma->rst)) { return dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst), - "Missing controller reset\n"); + "Failed to get controller reset\n"); } reset_control_reset(tdma->rst); =20 --=20 2.50.1 From nobody Thu Apr 9 12:06:24 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013069.outbound.protection.outlook.com [40.93.201.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B30936C9D6; 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charset="utf-8" Repurpose the struct tegra_dma_channel_regs to define offsets for all the channel registers. Previously, the struct only held the register values for each transfer and was wrapped within tegra_dma_sg_req. Move the values directly into tegra_dma_sg_req and use channel_regs for storing the register offsets. Update all register reads/writes to use the struct channel_regs. This prepares for the register offset change in Tegra264. Signed-off-by: Akhil R Reviewed-by: Frank Li --- drivers/dma/tegra186-gpc-dma.c | 281 +++++++++++++++++---------------- 1 file changed, 146 insertions(+), 135 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index 09a1717aa808..09ba2755c06d 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -22,7 +22,6 @@ #include "virt-dma.h" =20 /* CSR register */ -#define TEGRA_GPCDMA_CHAN_CSR 0x00 #define TEGRA_GPCDMA_CSR_ENB BIT(31) #define TEGRA_GPCDMA_CSR_IE_EOC BIT(30) #define TEGRA_GPCDMA_CSR_ONCE BIT(27) @@ -58,7 +57,6 @@ #define TEGRA_GPCDMA_CSR_WEIGHT GENMASK(13, 10) =20 /* STATUS register */ -#define TEGRA_GPCDMA_CHAN_STATUS 0x004 #define TEGRA_GPCDMA_STATUS_BUSY BIT(31) #define TEGRA_GPCDMA_STATUS_ISE_EOC BIT(30) #define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28) @@ -70,22 +68,13 @@ #define TEGRA_GPCDMA_STATUS_IRQ_STA BIT(21) #define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20) =20 -#define TEGRA_GPCDMA_CHAN_CSRE 0x008 #define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31) =20 -/* Source address */ -#define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C - -/* Destination address */ -#define TEGRA_GPCDMA_CHAN_DST_PTR 0x010 - /* High address pointer */ -#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR 0x014 #define TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR GENMASK(7, 0) #define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR GENMASK(23, 16) =20 /* MC sequence register */ -#define TEGRA_GPCDMA_CHAN_MCSEQ 0x18 #define TEGRA_GPCDMA_MCSEQ_DATA_SWAP BIT(31) #define TEGRA_GPCDMA_MCSEQ_REQ_COUNT GENMASK(30, 25) #define TEGRA_GPCDMA_MCSEQ_BURST GENMASK(24, 23) @@ -101,7 +90,6 @@ #define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK GENMASK(6, 0) =20 /* MMIO sequence register */ -#define TEGRA_GPCDMA_CHAN_MMIOSEQ 0x01c #define TEGRA_GPCDMA_MMIOSEQ_DBL_BUF BIT(31) #define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH GENMASK(30, 28) #define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8 \ @@ -120,17 +108,7 @@ #define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD GENMASK(18, 16) #define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT GENMASK(8, 7) =20 -/* Channel WCOUNT */ -#define TEGRA_GPCDMA_CHAN_WCOUNT 0x20 - -/* Transfer count */ -#define TEGRA_GPCDMA_CHAN_XFER_COUNT 0x24 - -/* DMA byte count status */ -#define TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS 0x28 - /* Error Status Register */ -#define TEGRA_GPCDMA_CHAN_ERR_STATUS 0x30 #define TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT 8 #define TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK 0xF #define TEGRA_GPCDMA_CHAN_ERR_TYPE(err) ( \ @@ -143,14 +121,9 @@ #define TEGRA_DMA_MC_SLAVE_ERR 0xB #define TEGRA_DMA_MMIO_SLAVE_ERR 0xA =20 -/* Fixed Pattern */ -#define TEGRA_GPCDMA_CHAN_FIXED_PATTERN 0x34 - -#define TEGRA_GPCDMA_CHAN_TZ 0x38 #define TEGRA_GPCDMA_CHAN_TZ_MMIO_PROT_1 BIT(0) #define TEGRA_GPCDMA_CHAN_TZ_MC_PROT_1 BIT(1) =20 -#define TEGRA_GPCDMA_CHAN_SPARE 0x3c #define TEGRA_GPCDMA_CHAN_SPARE_EN_LEGACY_FC BIT(16) =20 /* @@ -181,19 +154,27 @@ struct tegra_dma_chip_data { unsigned int nr_channels; unsigned int channel_reg_size; unsigned int max_dma_count; + const struct tegra_dma_channel_regs *channel_regs; int (*terminate)(struct tegra_dma_channel *tdc); }; =20 /* DMA channel registers */ struct tegra_dma_channel_regs { u32 csr; - u32 src_ptr; - u32 dst_ptr; - u32 high_addr_ptr; + u32 status; + u32 csre; + u32 src; + u32 dst; + u32 high_addr; u32 mc_seq; u32 mmio_seq; u32 wcount; + u32 wxfer; + u32 wstatus; + u32 err_status; u32 fixed_pattern; + u32 tz; + u32 spare; }; =20 /* @@ -205,7 +186,14 @@ struct tegra_dma_channel_regs { */ struct tegra_dma_sg_req { unsigned int len; - struct tegra_dma_channel_regs ch_regs; + u32 csr; + u32 src; + u32 dst; + u32 high_addr; + u32 mc_seq; + u32 mmio_seq; + u32 wcount; + u32 fixed_pattern; }; =20 /* @@ -228,19 +216,20 @@ struct tegra_dma_desc { * tegra_dma_channel: Channel specific information */ struct tegra_dma_channel { - bool config_init; - char name[30]; - enum dma_transfer_direction sid_dir; - enum dma_status status; - int id; - int irq; - int slave_id; + const struct tegra_dma_channel_regs *regs; struct tegra_dma *tdma; struct virt_dma_chan vc; struct tegra_dma_desc *dma_desc; struct dma_slave_config dma_sconfig; + enum dma_transfer_direction sid_dir; + enum dma_status status; unsigned int stream_id; unsigned long chan_base_offset; + bool config_init; + char name[30]; + int id; + int irq; + int slave_id; }; =20 /* @@ -288,22 +277,22 @@ static void tegra_dma_dump_chan_regs(struct tegra_dma= _channel *tdc) { dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n", tdc->id, tdc->name); - dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n", - tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR) - ); - dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n", - tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS) - ); + dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x\n", + tdc_read(tdc, tdc->regs->csr), + tdc_read(tdc, tdc->regs->status), + tdc_read(tdc, tdc->regs->csre)); + dev_dbg(tdc2dev(tdc), "SRC %x DST %x HI ADDR %x\n", + tdc_read(tdc, tdc->regs->src), + tdc_read(tdc, tdc->regs->dst), + tdc_read(tdc, tdc->regs->high_addr)); + dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x WSTA %x\n", + tdc_read(tdc, tdc->regs->mc_seq), + tdc_read(tdc, tdc->regs->mmio_seq), + tdc_read(tdc, tdc->regs->wcount), + tdc_read(tdc, tdc->regs->wxfer), + tdc_read(tdc, tdc->regs->wstatus)); dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n", - tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS)); + tdc_read(tdc, tdc->regs->err_status)); } =20 static int tegra_dma_sid_reserve(struct tegra_dma_channel *tdc, @@ -377,13 +366,13 @@ static int tegra_dma_pause(struct tegra_dma_channel *= tdc) int ret; u32 val; =20 - val =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); + val =3D tdc_read(tdc, tdc->regs->csre); val |=3D TEGRA_GPCDMA_CHAN_CSRE_PAUSE; - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); + tdc_write(tdc, tdc->regs->csre, val); =20 /* Wait until busy bit is de-asserted */ ret =3D readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + - tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, + tdc->chan_base_offset + tdc->regs->status, val, !(val & TEGRA_GPCDMA_STATUS_BUSY), TEGRA_GPCDMA_BURST_COMPLETE_TIME, @@ -419,9 +408,9 @@ static void tegra_dma_resume(struct tegra_dma_channel *= tdc) { u32 val; =20 - val =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); + val =3D tdc_read(tdc, tdc->regs->csre); val &=3D ~TEGRA_GPCDMA_CHAN_CSRE_PAUSE; - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); + tdc_write(tdc, tdc->regs->csre, val); =20 tdc->status =3D DMA_IN_PROGRESS; } @@ -456,27 +445,27 @@ static void tegra_dma_disable(struct tegra_dma_channe= l *tdc) { u32 csr, status; =20 - csr =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR); + csr =3D tdc_read(tdc, tdc->regs->csr); =20 /* Disable interrupts */ csr &=3D ~TEGRA_GPCDMA_CSR_IE_EOC; =20 /* Disable DMA */ csr &=3D ~TEGRA_GPCDMA_CSR_ENB; - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr); + tdc_write(tdc, tdc->regs->csr, csr); =20 /* Clear interrupt status if it is there */ - status =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); + status =3D tdc_read(tdc, tdc->regs->status); if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) { dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status); + tdc_write(tdc, tdc->regs->status, status); } } =20 static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc) { struct tegra_dma_desc *dma_desc =3D tdc->dma_desc; - struct tegra_dma_channel_regs *ch_regs; + struct tegra_dma_sg_req *sg_req; int ret; u32 val; =20 @@ -488,29 +477,29 @@ static void tegra_dma_configure_next_sg(struct tegra_= dma_channel *tdc) =20 /* Configure next transfer immediately after DMA is busy */ ret =3D readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + - tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, + tdc->chan_base_offset + tdc->regs->status, val, (val & TEGRA_GPCDMA_STATUS_BUSY), 0, TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT); if (ret) return; =20 - ch_regs =3D &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; + sg_req =3D &dma_desc->sg_req[dma_desc->sg_idx]; =20 - tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); + tdc_write(tdc, tdc->regs->wcount, sg_req->wcount); + tdc_write(tdc, tdc->regs->src, sg_req->src); + tdc_write(tdc, tdc->regs->dst, sg_req->dst); + tdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr); =20 /* Start DMA */ - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, - ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); + tdc_write(tdc, tdc->regs->csr, + sg_req->csr | TEGRA_GPCDMA_CSR_ENB); } =20 static void tegra_dma_start(struct tegra_dma_channel *tdc) { struct tegra_dma_desc *dma_desc =3D tdc->dma_desc; - struct tegra_dma_channel_regs *ch_regs; + struct tegra_dma_sg_req *sg_req; struct virt_dma_desc *vdesc; =20 if (!dma_desc) { @@ -526,21 +515,21 @@ static void tegra_dma_start(struct tegra_dma_channel = *tdc) tegra_dma_resume(tdc); } =20 - ch_regs =3D &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; + sg_req =3D &dma_desc->sg_req[dma_desc->sg_idx]; =20 - tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr); + tdc_write(tdc, tdc->regs->wcount, sg_req->wcount); + tdc_write(tdc, tdc->regs->csr, 0); + tdc_write(tdc, tdc->regs->src, sg_req->src); + tdc_write(tdc, tdc->regs->dst, sg_req->dst); + tdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr); + tdc_write(tdc, tdc->regs->fixed_pattern, sg_req->fixed_pattern); + tdc_write(tdc, tdc->regs->mmio_seq, sg_req->mmio_seq); + tdc_write(tdc, tdc->regs->mc_seq, sg_req->mc_seq); + tdc_write(tdc, tdc->regs->csr, sg_req->csr); =20 /* Start DMA */ - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, - ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); + tdc_write(tdc, tdc->regs->csr, + sg_req->csr | TEGRA_GPCDMA_CSR_ENB); } =20 static void tegra_dma_xfer_complete(struct tegra_dma_channel *tdc) @@ -601,19 +590,19 @@ static irqreturn_t tegra_dma_isr(int irq, void *dev_i= d) u32 status; =20 /* Check channel error status register */ - status =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS); + status =3D tdc_read(tdc, tdc->regs->err_status); if (status) { tegra_dma_chan_decode_error(tdc, status); tegra_dma_dump_chan_regs(tdc); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF); + tdc_write(tdc, tdc->regs->err_status, 0xFFFFFFFF); } =20 spin_lock(&tdc->vc.lock); - status =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); + status =3D tdc_read(tdc, tdc->regs->status); if (!(status & TEGRA_GPCDMA_STATUS_ISE_EOC)) goto irq_done; =20 - tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, + tdc_write(tdc, tdc->regs->status, TEGRA_GPCDMA_STATUS_ISE_EOC); =20 if (!dma_desc) @@ -673,10 +662,10 @@ static int tegra_dma_stop_client(struct tegra_dma_cha= nnel *tdc) * to stop DMA engine from starting any more bursts for * the given client and wait for in flight bursts to complete */ - csr =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR); + csr =3D tdc_read(tdc, tdc->regs->csr); csr &=3D ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK); csr |=3D TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED; - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr); + tdc_write(tdc, tdc->regs->csr, csr); =20 /* Wait for in flight data transfer to finish */ udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME); @@ -687,7 +676,7 @@ static int tegra_dma_stop_client(struct tegra_dma_chann= el *tdc) =20 ret =3D readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + tdc->chan_base_offset + - TEGRA_GPCDMA_CHAN_STATUS, + tdc->regs->status, status, !(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX | TEGRA_GPCDMA_STATUS_CHANNEL_RX)), @@ -739,14 +728,14 @@ static int tegra_dma_get_residual(struct tegra_dma_ch= annel *tdc) unsigned int bytes_xfer, residual; u32 wcount =3D 0, status; =20 - wcount =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT); + wcount =3D tdc_read(tdc, tdc->regs->wxfer); =20 /* * Set wcount =3D 0 if EOC bit is set. The transfer would have * already completed and the CHAN_XFER_COUNT could have updated * for the next transfer, specifically in case of cyclic transfers. */ - status =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); + status =3D tdc_read(tdc, tdc->regs->status); if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) wcount =3D 0; =20 @@ -893,7 +882,7 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr= _t dest, int value, /* Configure default priority weight for the channel */ csr |=3D FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1); =20 - mc_seq =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + mc_seq =3D tdc_read(tdc, tdc->regs->mc_seq); /* retain stream-id and clean rest */ mc_seq &=3D TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK; =20 @@ -916,16 +905,16 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_ad= dr_t dest, int value, dma_desc->sg_count =3D 1; sg_req =3D dma_desc->sg_req; =20 - sg_req[0].ch_regs.src_ptr =3D 0; - sg_req[0].ch_regs.dst_ptr =3D dest; - sg_req[0].ch_regs.high_addr_ptr =3D + sg_req[0].src =3D 0; + sg_req[0].dst =3D dest; + sg_req[0].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32)); - sg_req[0].ch_regs.fixed_pattern =3D value; + sg_req[0].fixed_pattern =3D value; /* Word count reg takes value as (N +1) words */ - sg_req[0].ch_regs.wcount =3D ((len - 4) >> 2); - sg_req[0].ch_regs.csr =3D csr; - sg_req[0].ch_regs.mmio_seq =3D 0; - sg_req[0].ch_regs.mc_seq =3D mc_seq; + sg_req[0].wcount =3D ((len - 4) >> 2); + sg_req[0].csr =3D csr; + sg_req[0].mmio_seq =3D 0; + sg_req[0].mc_seq =3D mc_seq; sg_req[0].len =3D len; =20 dma_desc->cyclic =3D false; @@ -961,7 +950,7 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr= _t dest, /* Configure default priority weight for the channel */ csr |=3D FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1); =20 - mc_seq =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + mc_seq =3D tdc_read(tdc, tdc->regs->mc_seq); /* retain stream-id and clean rest */ mc_seq &=3D (TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK) | (TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK); @@ -985,17 +974,17 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_ad= dr_t dest, dma_desc->sg_count =3D 1; sg_req =3D dma_desc->sg_req; =20 - sg_req[0].ch_regs.src_ptr =3D src; - sg_req[0].ch_regs.dst_ptr =3D dest; - sg_req[0].ch_regs.high_addr_ptr =3D + sg_req[0].src =3D src; + sg_req[0].dst =3D dest; + sg_req[0].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32)); - sg_req[0].ch_regs.high_addr_ptr |=3D + sg_req[0].high_addr |=3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32)); /* Word count reg takes value as (N +1) words */ - sg_req[0].ch_regs.wcount =3D ((len - 4) >> 2); - sg_req[0].ch_regs.csr =3D csr; - sg_req[0].ch_regs.mmio_seq =3D 0; - sg_req[0].ch_regs.mc_seq =3D mc_seq; + sg_req[0].wcount =3D ((len - 4) >> 2); + sg_req[0].csr =3D csr; + sg_req[0].mmio_seq =3D 0; + sg_req[0].mc_seq =3D mc_seq; sg_req[0].len =3D len; =20 dma_desc->cyclic =3D false; @@ -1049,7 +1038,7 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct s= catterlist *sgl, if (flags & DMA_PREP_INTERRUPT) csr |=3D TEGRA_GPCDMA_CSR_IE_EOC; =20 - mc_seq =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + mc_seq =3D tdc_read(tdc, tdc->regs->mc_seq); /* retain stream-id and clean rest */ mc_seq &=3D TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK; =20 @@ -1096,14 +1085,14 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct= scatterlist *sgl, dma_desc->bytes_req +=3D len; =20 if (direction =3D=3D DMA_MEM_TO_DEV) { - sg_req[i].ch_regs.src_ptr =3D mem; - sg_req[i].ch_regs.dst_ptr =3D apb_ptr; - sg_req[i].ch_regs.high_addr_ptr =3D + sg_req[i].src =3D mem; + sg_req[i].dst =3D apb_ptr; + sg_req[i].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32)); } else if (direction =3D=3D DMA_DEV_TO_MEM) { - sg_req[i].ch_regs.src_ptr =3D apb_ptr; - sg_req[i].ch_regs.dst_ptr =3D mem; - sg_req[i].ch_regs.high_addr_ptr =3D + sg_req[i].src =3D apb_ptr; + sg_req[i].dst =3D mem; + sg_req[i].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32)); } =20 @@ -1111,10 +1100,10 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct= scatterlist *sgl, * Word count register takes input in words. Writing a value * of N into word count register means a req of (N+1) words. */ - sg_req[i].ch_regs.wcount =3D ((len - 4) >> 2); - sg_req[i].ch_regs.csr =3D csr; - sg_req[i].ch_regs.mmio_seq =3D mmio_seq; - sg_req[i].ch_regs.mc_seq =3D mc_seq; + sg_req[i].wcount =3D ((len - 4) >> 2); + sg_req[i].csr =3D csr; + sg_req[i].mmio_seq =3D mmio_seq; + sg_req[i].mc_seq =3D mc_seq; sg_req[i].len =3D len; } =20 @@ -1186,7 +1175,7 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_ad= dr_t buf_addr, size_t buf_l =20 mmio_seq |=3D FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1); =20 - mc_seq =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + mc_seq =3D tdc_read(tdc, tdc->regs->mc_seq); /* retain stream-id and clean rest */ mc_seq &=3D TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK; =20 @@ -1218,24 +1207,24 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_= addr_t buf_addr, size_t buf_l for (i =3D 0; i < period_count; i++) { mmio_seq |=3D get_burst_size(tdc, burst_size, slave_bw, len); if (direction =3D=3D DMA_MEM_TO_DEV) { - sg_req[i].ch_regs.src_ptr =3D mem; - sg_req[i].ch_regs.dst_ptr =3D apb_ptr; - sg_req[i].ch_regs.high_addr_ptr =3D + sg_req[i].src =3D mem; + sg_req[i].dst =3D apb_ptr; + sg_req[i].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32)); } else if (direction =3D=3D DMA_DEV_TO_MEM) { - sg_req[i].ch_regs.src_ptr =3D apb_ptr; - sg_req[i].ch_regs.dst_ptr =3D mem; - sg_req[i].ch_regs.high_addr_ptr =3D + sg_req[i].src =3D apb_ptr; + sg_req[i].dst =3D mem; + sg_req[i].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32)); } /* * Word count register takes input in words. Writing a value * of N into word count register means a req of (N+1) words. */ - sg_req[i].ch_regs.wcount =3D ((len - 4) >> 2); - sg_req[i].ch_regs.csr =3D csr; - sg_req[i].ch_regs.mmio_seq =3D mmio_seq; - sg_req[i].ch_regs.mc_seq =3D mc_seq; + sg_req[i].wcount =3D ((len - 4) >> 2); + sg_req[i].csr =3D csr; + sg_req[i].mmio_seq =3D mmio_seq; + sg_req[i].mc_seq =3D mc_seq; sg_req[i].len =3D len; =20 mem +=3D len; @@ -1305,11 +1294,30 @@ static struct dma_chan *tegra_dma_of_xlate(struct o= f_phandle_args *dma_spec, return chan; } =20 +static const struct tegra_dma_channel_regs tegra186_reg_offsets =3D { + .csr =3D 0x0, + .status =3D 0x4, + .csre =3D 0x8, + .src =3D 0xc, + .dst =3D 0x10, + .high_addr =3D 0x14, + .mc_seq =3D 0x18, + .mmio_seq =3D 0x1c, + .wcount =3D 0x20, + .wxfer =3D 0x24, + .wstatus =3D 0x28, + .err_status =3D 0x30, + .fixed_pattern =3D 0x34, + .tz =3D 0x38, + .spare =3D 0x40, +}; + static const struct tegra_dma_chip_data tegra186_dma_chip_data =3D { .nr_channels =3D 32, .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D false, + .channel_regs =3D &tegra186_reg_offsets, .terminate =3D tegra_dma_stop_client, }; =20 @@ -1318,6 +1326,7 @@ static const struct tegra_dma_chip_data tegra194_dma_= chip_data =3D { .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D true, + .channel_regs =3D &tegra186_reg_offsets, .terminate =3D tegra_dma_pause, }; =20 @@ -1326,6 +1335,7 @@ static const struct tegra_dma_chip_data tegra234_dma_= chip_data =3D { .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D true, + .channel_regs =3D &tegra186_reg_offsets, .terminate =3D tegra_dma_pause_noerr, }; =20 @@ -1346,7 +1356,7 @@ MODULE_DEVICE_TABLE(of, tegra_dma_of_match); =20 static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream= _id) { - unsigned int reg_val =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + unsigned int reg_val =3D tdc_read(tdc, tdc->regs->mc_seq); =20 reg_val &=3D ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK); reg_val &=3D ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK); @@ -1354,7 +1364,7 @@ static int tegra_dma_program_sid(struct tegra_dma_cha= nnel *tdc, int stream_id) reg_val |=3D FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id); 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charset="utf-8" Tegra264 supports address width of 41 bits. Unlike older SoCs which use a common high_addr register for upper address bits, Tegra264 has separate src_high and dst_high registers to accommodate this wider address space. Add an addr_bits property to the device data structure to specify the number of address bits supported on each device and use that to program the appropriate registers. Update the sg_req struct to remove the high_addr field and use dma_addr_t for src and dst to store the complete addresses. Extract the high address bits only when programming the registers. Signed-off-by: Akhil R Reviewed-by: Frank Li --- drivers/dma/tegra186-gpc-dma.c | 87 ++++++++++++++++++++++------------ 1 file changed, 56 insertions(+), 31 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index 09ba2755c06d..753e86d05a02 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -151,6 +151,7 @@ struct tegra_dma_channel; */ struct tegra_dma_chip_data { bool hw_support_pause; + unsigned int addr_bits; unsigned int nr_channels; unsigned int channel_reg_size; unsigned int max_dma_count; @@ -166,6 +167,8 @@ struct tegra_dma_channel_regs { u32 src; u32 dst; u32 high_addr; + u32 src_high; + u32 dst_high; u32 mc_seq; u32 mmio_seq; u32 wcount; @@ -186,10 +189,9 @@ struct tegra_dma_channel_regs { */ struct tegra_dma_sg_req { unsigned int len; + dma_addr_t src; + dma_addr_t dst; u32 csr; - u32 src; - u32 dst; - u32 high_addr; u32 mc_seq; u32 mmio_seq; u32 wcount; @@ -273,6 +275,25 @@ static inline struct device *tdc2dev(struct tegra_dma_= channel *tdc) return tdc->vc.chan.device->dev; } =20 +static void tegra_dma_program_addr(struct tegra_dma_channel *tdc, + struct tegra_dma_sg_req *sg_req) +{ + tdc_write(tdc, tdc->regs->src, lower_32_bits(sg_req->src)); + tdc_write(tdc, tdc->regs->dst, lower_32_bits(sg_req->dst)); + + if (tdc->tdma->chip_data->addr_bits > 39) { + tdc_write(tdc, tdc->regs->src_high, upper_32_bits(sg_req->src)); + tdc_write(tdc, tdc->regs->dst_high, upper_32_bits(sg_req->dst)); + } else { + u32 src_high =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, + upper_32_bits(sg_req->src)); + u32 dst_high =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, + upper_32_bits(sg_req->dst)); + + tdc_write(tdc, tdc->regs->high_addr, src_high | dst_high); + } +} + static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc) { dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n", @@ -281,10 +302,20 @@ static void tegra_dma_dump_chan_regs(struct tegra_dma= _channel *tdc) tdc_read(tdc, tdc->regs->csr), tdc_read(tdc, tdc->regs->status), tdc_read(tdc, tdc->regs->csre)); - dev_dbg(tdc2dev(tdc), "SRC %x DST %x HI ADDR %x\n", - tdc_read(tdc, tdc->regs->src), - tdc_read(tdc, tdc->regs->dst), - tdc_read(tdc, tdc->regs->high_addr)); + + if (tdc->tdma->chip_data->addr_bits > 39) { + dev_dbg(tdc2dev(tdc), "SRC %x SRC HI %x DST %x DST HI %x\n", + tdc_read(tdc, tdc->regs->src), + tdc_read(tdc, tdc->regs->src_high), + tdc_read(tdc, tdc->regs->dst), + tdc_read(tdc, tdc->regs->dst_high)); + } else { + dev_dbg(tdc2dev(tdc), "SRC %x DST %x HI ADDR %x\n", + tdc_read(tdc, tdc->regs->src), + tdc_read(tdc, tdc->regs->dst), + tdc_read(tdc, tdc->regs->high_addr)); + } + dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x WSTA %x\n", tdc_read(tdc, tdc->regs->mc_seq), tdc_read(tdc, tdc->regs->mmio_seq), @@ -487,9 +518,7 @@ static void tegra_dma_configure_next_sg(struct tegra_dm= a_channel *tdc) sg_req =3D &dma_desc->sg_req[dma_desc->sg_idx]; =20 tdc_write(tdc, tdc->regs->wcount, sg_req->wcount); - tdc_write(tdc, tdc->regs->src, sg_req->src); - tdc_write(tdc, tdc->regs->dst, sg_req->dst); - tdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr); + tegra_dma_program_addr(tdc, sg_req); =20 /* Start DMA */ tdc_write(tdc, tdc->regs->csr, @@ -517,11 +546,9 @@ static void tegra_dma_start(struct tegra_dma_channel *= tdc) =20 sg_req =3D &dma_desc->sg_req[dma_desc->sg_idx]; =20 + tegra_dma_program_addr(tdc, sg_req); tdc_write(tdc, tdc->regs->wcount, sg_req->wcount); tdc_write(tdc, tdc->regs->csr, 0); - tdc_write(tdc, tdc->regs->src, sg_req->src); - tdc_write(tdc, tdc->regs->dst, sg_req->dst); - tdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr); tdc_write(tdc, tdc->regs->fixed_pattern, sg_req->fixed_pattern); tdc_write(tdc, tdc->regs->mmio_seq, sg_req->mmio_seq); tdc_write(tdc, tdc->regs->mc_seq, sg_req->mc_seq); @@ -826,7 +853,7 @@ static unsigned int get_burst_size(struct tegra_dma_cha= nnel *tdc, =20 static int get_transfer_param(struct tegra_dma_channel *tdc, enum dma_transfer_direction direction, - u32 *apb_addr, + dma_addr_t *apb_addr, u32 *mmio_seq, u32 *csr, unsigned int *burst_size, @@ -904,11 +931,9 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_add= r_t dest, int value, dma_desc->bytes_req =3D len; dma_desc->sg_count =3D 1; sg_req =3D dma_desc->sg_req; - sg_req[0].src =3D 0; sg_req[0].dst =3D dest; - sg_req[0].high_addr =3D - FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32)); + sg_req[0].fixed_pattern =3D value; /* Word count reg takes value as (N +1) words */ sg_req[0].wcount =3D ((len - 4) >> 2); @@ -976,10 +1001,7 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_ad= dr_t dest, =20 sg_req[0].src =3D src; sg_req[0].dst =3D dest; - sg_req[0].high_addr =3D - FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32)); - sg_req[0].high_addr |=3D - FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32)); + /* Word count reg takes value as (N +1) words */ sg_req[0].wcount =3D ((len - 4) >> 2); sg_req[0].csr =3D csr; @@ -999,7 +1021,8 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct sc= atterlist *sgl, struct tegra_dma_channel *tdc =3D to_tegra_dma_chan(dc); unsigned int max_dma_count =3D tdc->tdma->chip_data->max_dma_count; enum dma_slave_buswidth slave_bw =3D DMA_SLAVE_BUSWIDTH_UNDEFINED; - u32 csr, mc_seq, apb_ptr =3D 0, mmio_seq =3D 0; + u32 csr, mc_seq, mmio_seq =3D 0; + dma_addr_t apb_ptr =3D 0; struct tegra_dma_sg_req *sg_req; struct tegra_dma_desc *dma_desc; struct scatterlist *sg; @@ -1087,13 +1110,9 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct = scatterlist *sgl, if (direction =3D=3D DMA_MEM_TO_DEV) { sg_req[i].src =3D mem; sg_req[i].dst =3D apb_ptr; - sg_req[i].high_addr =3D - FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32)); } else if (direction =3D=3D DMA_DEV_TO_MEM) { sg_req[i].src =3D apb_ptr; sg_req[i].dst =3D mem; - sg_req[i].high_addr =3D - FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32)); } =20 /* @@ -1117,7 +1136,8 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_ad= dr_t buf_addr, size_t buf_l unsigned long flags) { enum dma_slave_buswidth slave_bw =3D DMA_SLAVE_BUSWIDTH_UNDEFINED; - u32 csr, mc_seq, apb_ptr =3D 0, mmio_seq =3D 0, burst_size; + u32 csr, mc_seq, mmio_seq =3D 0, burst_size; + dma_addr_t apb_ptr =3D 0; unsigned int max_dma_count, len, period_count, i; struct tegra_dma_channel *tdc =3D to_tegra_dma_chan(dc); struct tegra_dma_desc *dma_desc; @@ -1209,13 +1229,9 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_a= ddr_t buf_addr, size_t buf_l if (direction =3D=3D DMA_MEM_TO_DEV) { sg_req[i].src =3D mem; sg_req[i].dst =3D apb_ptr; - sg_req[i].high_addr =3D - FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32)); } else if (direction =3D=3D DMA_DEV_TO_MEM) { sg_req[i].src =3D apb_ptr; sg_req[i].dst =3D mem; - sg_req[i].high_addr =3D - FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32)); } /* * Word count register takes input in words. Writing a value @@ -1314,6 +1330,7 @@ static const struct tegra_dma_channel_regs tegra186_r= eg_offsets =3D { =20 static const struct tegra_dma_chip_data tegra186_dma_chip_data =3D { .nr_channels =3D 32, + .addr_bits =3D 39, .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D false, @@ -1323,6 +1340,7 @@ static const struct tegra_dma_chip_data tegra186_dma_= chip_data =3D { =20 static const struct tegra_dma_chip_data tegra194_dma_chip_data =3D { .nr_channels =3D 32, + .addr_bits =3D 39, .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D true, @@ -1332,6 +1350,7 @@ static const struct tegra_dma_chip_data tegra194_dma_= chip_data =3D { =20 static const struct tegra_dma_chip_data tegra234_dma_chip_data =3D { .nr_channels =3D 32, + .addr_bits =3D 39, .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D true, @@ -1443,6 +1462,12 @@ static int tegra_dma_probe(struct platform_device *p= dev) tdc->stream_id =3D stream_id; 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charset="utf-8" Switch to dmaenginem_async_device_register() for managed registration and to simplify the error path in the probe. Signed-off-by: Akhil R Suggested-by: Frank Li --- drivers/dma/tegra186-gpc-dma.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index 753e86d05a02..5997edaba28e 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -1497,7 +1497,7 @@ static int tegra_dma_probe(struct platform_device *pd= ev) tdma->dma_dev.device_synchronize =3D tegra_dma_chan_synchronize; tdma->dma_dev.residue_granularity =3D DMA_RESIDUE_GRANULARITY_BURST; =20 - ret =3D dma_async_device_register(&tdma->dma_dev); + ret =3D dmaenginem_async_device_register(&tdma->dma_dev); if (ret < 0) { dev_err_probe(&pdev->dev, ret, "GPC DMA driver registration failed\n"); @@ -1509,12 +1509,10 @@ static int tegra_dma_probe(struct platform_device *= pdev) if (ret < 0) { dev_err_probe(&pdev->dev, ret, "GPC DMA OF registration failed\n"); - - dma_async_device_unregister(&tdma->dma_dev); return ret; } =20 - dev_info(&pdev->dev, "GPC DMA driver register %lu channels\n", + dev_info(&pdev->dev, "GPC DMA driver registered %lu channels\n", hweight_long(tdma->chan_mask)); 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charset="utf-8" Use 'iommu-map', when provided, to get the stream ID to be programmed for each channel. Iterate over the channels registered and configure each channel device separately using of_dma_configure_id() to allow it to use a separate IOMMU domain for the transfer. But do this in a second loop since the first loop populates the dma device channels list and async_device_register() registers the channels. Both are prerequisite for using the channel device in the next loop. Channels will continue to use the same global stream ID if the 'iommu-map' property is not present in the device tree. Signed-off-by: Akhil R --- drivers/dma/tegra186-gpc-dma.c | 64 +++++++++++++++++++++++++++++----- 1 file changed, 55 insertions(+), 9 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index 5997edaba28e..9af509ecf495 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1390,9 +1391,13 @@ static int tegra_dma_program_sid(struct tegra_dma_ch= annel *tdc, int stream_id) static int tegra_dma_probe(struct platform_device *pdev) { const struct tegra_dma_chip_data *cdata =3D NULL; + struct tegra_dma_channel *tdc; + struct tegra_dma *tdma; + struct dma_chan *chan; + struct device *chdev; + bool use_iommu_map =3D false; unsigned int i; u32 stream_id; - struct tegra_dma *tdma; int ret; =20 cdata =3D of_device_get_match_data(&pdev->dev); @@ -1420,9 +1425,12 @@ static int tegra_dma_probe(struct platform_device *p= dev) =20 tdma->dma_dev.dev =3D &pdev->dev; =20 - if (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) { - dev_err(&pdev->dev, "Missing iommu stream-id\n"); - return -EINVAL; + use_iommu_map =3D of_property_present(pdev->dev.of_node, "iommu-map"); + if (!use_iommu_map) { + if (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) { + dev_err(&pdev->dev, "Missing iommu stream-id\n"); + return -EINVAL; + } } =20 ret =3D device_property_read_u32(&pdev->dev, "dma-channel-mask", @@ -1434,9 +1442,10 @@ static int tegra_dma_probe(struct platform_device *p= dev) tdma->chan_mask =3D TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK; } =20 + /* Initialize vchan for each channel and populate the channels list */ INIT_LIST_HEAD(&tdma->dma_dev.channels); for (i =3D 0; i < cdata->nr_channels; i++) { - struct tegra_dma_channel *tdc =3D &tdma->channels[i]; + tdc =3D &tdma->channels[i]; =20 /* Check for channel mask */ if (!(tdma->chan_mask & BIT(i))) @@ -1456,10 +1465,6 @@ static int tegra_dma_probe(struct platform_device *p= dev) =20 vchan_init(&tdc->vc, &tdma->dma_dev); tdc->vc.desc_free =3D tegra_dma_desc_free; - - /* program stream-id for this channel */ - tegra_dma_program_sid(tdc, stream_id); - tdc->stream_id =3D stream_id; } =20 ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(cdata->addr_bi= ts)); @@ -1497,6 +1502,7 @@ static int tegra_dma_probe(struct platform_device *pd= ev) tdma->dma_dev.device_synchronize =3D tegra_dma_chan_synchronize; tdma->dma_dev.residue_granularity =3D DMA_RESIDUE_GRANULARITY_BURST; =20 + /* Register the DMA device and the channels */ ret =3D dmaenginem_async_device_register(&tdma->dma_dev); if (ret < 0) { dev_err_probe(&pdev->dev, ret, @@ -1504,6 +1510,46 @@ static int tegra_dma_probe(struct platform_device *p= dev) return ret; } =20 + /* + * Configure stream ID for each channel from the channels registered + * above. This is done in a separate iteration to ensure that only + * the channels available and registered for the DMA device are used. + */ + list_for_each_entry(chan, &tdma->dma_dev.channels, device_node) { + chdev =3D &chan->dev->device; + tdc =3D to_tegra_dma_chan(chan); + + if (use_iommu_map) { + chdev->bus =3D pdev->dev.bus; + ret =3D dma_coerce_mask_and_coherent(chdev, DMA_BIT_MASK(cdata->addr_bi= ts)); + if (ret) { + dev_err(chdev, "Failed to set DMA mask for channel %d: %d\n", + tdc->id, ret); + return ret; + } + + ret =3D of_dma_configure_id(chdev, pdev->dev.of_node, + true, &tdc->id); + if (ret) { + dev_err(chdev, "Failed to configure IOMMU for channel %d: %d\n", + tdc->id, ret); + return ret; + } + + if (!tegra_dev_iommu_get_stream_id(chdev, &stream_id)) { + dev_err(chdev, "Failed to get stream ID for channel %d\n", + tdc->id); + return -EINVAL; + } + + chan->dev->chan_dma_dev =3D true; + } + + /* program stream-id for this channel */ + tegra_dma_program_sid(tdc, stream_id); + tdc->stream_id =3D stream_id; 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charset="utf-8" Add compatible and chip data to support GPCDMA in Tegra264, which has differences in register layout and address bits compared to previous versions. Signed-off-by: Akhil R Reviewed-by: Frank Li --- drivers/dma/tegra186-gpc-dma.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index 9af509ecf495..d6e0dbc19e8a 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -1329,6 +1329,25 @@ static const struct tegra_dma_channel_regs tegra186_= reg_offsets =3D { .spare =3D 0x40, }; =20 +static const struct tegra_dma_channel_regs tegra264_reg_offsets =3D { + .csr =3D 0x0, + .status =3D 0x4, + .csre =3D 0x8, + .src =3D 0xc, + .dst =3D 0x10, + .src_high =3D 0x14, + .dst_high =3D 0x18, + .mc_seq =3D 0x1c, + .mmio_seq =3D 0x20, + .wcount =3D 0x24, + .wxfer =3D 0x28, + .wstatus =3D 0x2c, + .err_status =3D 0x34, + .fixed_pattern =3D 0x38, + .tz =3D 0x3c, + .spare =3D 0x44, +}; + static const struct tegra_dma_chip_data tegra186_dma_chip_data =3D { .nr_channels =3D 32, .addr_bits =3D 39, @@ -1359,6 +1378,16 @@ static const struct tegra_dma_chip_data tegra234_dma= _chip_data =3D { .terminate =3D tegra_dma_pause_noerr, }; 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charset="utf-8" Add iommu-map the GPCDMA controller node so that each channel uses a separate stream ID and gets its own IOMMU domain for memory. Enable GCPDMA as well. Also remove the fallback compatible string "nvidia,tegra186-gpcdma". Tegra186 compatible cannot work on Tegra264 because of the register offset changes and absence of reset property. Signed-off-by: Akhil R --- arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 4 ++++ arch/arm64/boot/dts/nvidia/tegra264.dtsi | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/bo= ot/dts/nvidia/tegra264-p3834.dtsi index 7e2c3e66c2ab..c8beb616964a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi @@ -16,6 +16,10 @@ serial@c4e0000 { serial@c5a0000 { status =3D "okay"; }; + + dma-controller@8400000 { + status =3D "okay"; + }; }; =20 bus@8100000000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index 7644a41d5f72..9821d085c766 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3208,7 +3208,7 @@ agic_page5: interrupt-controller@99b0000 { }; =20 gpcdma: dma-controller@8400000 { - compatible =3D "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma"; + compatible =3D "nvidia,tegra264-gpcdma"; reg =3D <0x0 0x08400000 0x0 0x210000>; interrupts =3D , , @@ -3244,6 +3244,7 @@ gpcdma: dma-controller@8400000 { ; #dma-cells =3D <1>; iommus =3D <&smmu1 0x00000800>; + iommu-map =3D <1 &smmu1 0x801 31>; dma-coherent; dma-channel-mask =3D <0xfffffffe>; status =3D "disabled"; --=20 2.50.1