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([103.218.174.23]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c70fa848471sm11454177a12.30.2026.03.02.04.12.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2026 04:12:15 -0800 (PST) From: Sudarshan Shetty To: andersson@kernel.org, konradybcio@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sudarshan Shetty , Krzysztof Kozlowski Subject: [PATCH v15 1/3] dt-bindings: arm: qcom: talos-evk: Add QCS615 Talos EVK SMARC platform Date: Mon, 2 Mar 2026 17:41:57 +0530 Message-Id: <20260302121159.1938694-2-tessolveupstream@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260302121159.1938694-1-tessolveupstream@gmail.com> References: <20260302121159.1938694-1-tessolveupstream@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add binding support for the Qualcomm Technologies, Inc. Talos EVK SMARC platform based on the QCS615 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Sudarshan Shetty --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index d48c625d3fc4..9732a32a5f59 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -883,6 +883,7 @@ properties: - items: - enum: - qcom,qcs615-ride + - qcom,talos-evk - const: qcom,qcs615 - const: qcom,sm6150 =20 --=20 2.34.1 From nobody Thu Apr 9 12:06:26 2026 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B9BC363C47 for ; Mon, 2 Mar 2026 12:12:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772453545; cv=none; b=D4vz1ihVEYG9026WXUuQJlkAqF6tT46/XqszGu5xfZt79JgNkfIHNHyS2e1fb71e2uhTmjxxCK8GnsiO2sXGE1gbHU6TnZmq2h8n5VQqufNBVZF8JvQZNbOt7T4tYKLNSvzCbh9eqfItGHNa5nFFhK+L1Jt2B6u531AGCHe6Fl4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772453545; c=relaxed/simple; bh=W81JHwo98DtnUdaW8I4ravA3RNHN4XNWcIrZGDKOXHg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bgACSnsn6kX8C9Si01oo+210x0/0yOKNZKaThdG0hjbESyj55qF5n7E5eNcb+cP71Lw8gpcRE/mT8rTeZ4F2kcGgDri6DQ442yWzlsFJV9IzIaRp5RKAooFOqTw0ktkIbyN8CLbWK0xa44PhktvthPOwWH9tKcRMXneNEvduu7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=WMhExMgU; arc=none smtp.client-ip=209.85.210.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WMhExMgU" Received: by mail-pf1-f180.google.com with SMTP id d2e1a72fcca58-8273eb7798eso1860441b3a.1 for ; Mon, 02 Mar 2026 04:12:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772453544; x=1773058344; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PfF4tOiVLItjb1gfwcr8m37Aukq7zsbax8v7AQsNoAw=; b=WMhExMgUBwwdjH2XtpPrVTKBDFrz9JR2FjtzyLebDs6uN2Bw+WDjkGgdgtW87RqaIo K6MvIQsujv2ylEb4BVOJQ6xc1NmU3rfQ6+bMlzlToCaHRA8l8JcOFuZ9etQ1BXbMhLcr qKCCm4VSqcvqHkvid8J7LK/ZbyNpxG9qcCeLQuy19mV37Hhb7NBSpcCUx4jIpEwnm6Ro FOynA1YDfeDVqAriyy56D5dOmRvATIMK9rM9B6JUY+ER4ykE0bU4vIb/3qC2TfaKcxOI /ga+hu+b9saev2INh1oTQpEzNbwNXS4qyp3ngzPDuKdEKuC5Z1LqLWbEi8mZhqKuUNbn jXmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772453544; x=1773058344; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=PfF4tOiVLItjb1gfwcr8m37Aukq7zsbax8v7AQsNoAw=; b=rTE/tOQm+bYi8ccLsEBrq3iwoZ38JxuBFrYItrtdrQndNO3i9/e0XDuPwRQGhmKf3O Xf3u9UCJ8y6itDDCT4m0SZ7b3+sAil18WBVFhaBg19GaxzrULUGOVGPiOEXbmvjcIrcQ w0XiIxLLPasw5BHWmzDbFEL+CGezmroBIEdDW0F3qK8iE1Ird4u8W39DoZsueWj2tQOR VsVVjuykELVc9nqU5IMRwrEs1ku2RD2pgNtEq50oi0q+N1dzF1d3ZjgbIhqqLGq1J2X/ k+ypUaE2nCjj6l3lyy4W1JhLQdpgq1wnvr44yrOUaKbHarE0iQbguFpPXcmxwFhERwYi TUbA== X-Forwarded-Encrypted: i=1; AJvYcCViFvjiageOc7lJFHTRDYcrc4Zry7vVdWqn+J12FVYmbcFAbCM4rE4t8yWuRECacP3w0UNpJ6mXEoDI9G4=@vger.kernel.org X-Gm-Message-State: AOJu0Yy0KsLosAjzQMmPieITkdiixRArUNq0RVJVqUfV/7uJ7b0h/mZD 31F+emKOV/y6P/gnW+y2kjyVV/ON9WuXA4KDneoxC9PEhhiVjkiNnXMJ X-Gm-Gg: ATEYQzwA6pGR8lP6kRD8ezQXZ07uHSp9O/K+21sEse38YaxsgeJEgHjxn4VPmO72T7k +3TxWfslJAh07jHqkk75Jm+K5ZvNmM/CQp4+AmgsWCNGMFKXhnr1BFudJreTL6DJY0S5oVE9qSl q6dmdvXxTJb4MrLbqfwqinHd4RisqwItFTrb4QczsVtndH9DbZXm2ZfcW5wIOsjKR4MIt25skCt u1IW/CIfeWncWc56iR/FBfmEkggrXoUqDGFaVsZuAdeT4953mibEiefDKlXjHpXpYgsLcBNsgwr LacZqOeEP34Z9U0czT0Dr/MceDTpAQaVM3TAbm/zSKiYJRfKEgRYtka34DpA2jRSUQERnB1SMFg J73evhXnXDuFv27Dxt0pe3jI04eoIWz3ZR86iRlucNX/2KzRCDyvBF+ORXkmLGGT/IJx/Tg2AOu yOkmCRXFl8IjtWBj3adZ6IdUurr7r2k5bfyI+bKzhDtv9DI6yt X-Received: by 2002:a05:6a21:6f0a:b0:38d:ebdc:3555 with SMTP id adf61e73a8af0-395c3b3deadmr10834753637.66.1772453543562; Mon, 02 Mar 2026 04:12:23 -0800 (PST) Received: from test-HP-Desktop-Pro-G3.. ([103.218.174.23]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c70fa848471sm11454177a12.30.2026.03.02.04.12.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2026 04:12:22 -0800 (PST) From: Sudarshan Shetty To: andersson@kernel.org, konradybcio@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sudarshan Shetty , Dmitry Baryshkov Subject: [PATCH v15 2/3] arm64: dts: qcom: talos/qcs615-ride: Fix inconsistent USB PHY node naming Date: Mon, 2 Mar 2026 17:41:58 +0530 Message-Id: <20260302121159.1938694-3-tessolveupstream@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260302121159.1938694-1-tessolveupstream@gmail.com> References: <20260302121159.1938694-1-tessolveupstream@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The USB PHY nodes has inconsistent labels as 'usb_1_hsphy' and 'usb_hsphy_2' across talos.dtsi and qcs615-ride.dts. This patch renames them to follow a consistent naming scheme. No functional changes, only label renaming. Reviewed-by: Dmitry Baryshkov Signed-off-by: Sudarshan Shetty --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 2 +- arch/arm64/boot/dts/qcom/talos.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts index 5a24c19c415e..6a052667f096 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -662,7 +662,7 @@ &usb_1_dwc3 { dr_mode =3D "peripheral"; }; =20 -&usb_hsphy_2 { +&usb_2_hsphy { vdd-supply =3D <&vreg_l5a>; vdda-pll-supply =3D <&vreg_l12a>; vdda-phy-dpdm-supply =3D <&vreg_l13a>; diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom= /talos.dtsi index 75716b4a58d6..f69a40fb8e28 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -4417,7 +4417,7 @@ usb_1_hsphy: phy@88e2000 { status =3D "disabled"; }; =20 - usb_hsphy_2: phy@88e3000 { + usb_2_hsphy: phy@88e3000 { compatible =3D "qcom,qcs615-qusb2-phy"; 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([103.218.174.23]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c70fa848471sm11454177a12.30.2026.03.02.04.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2026 04:12:29 -0800 (PST) From: Sudarshan Shetty To: andersson@kernel.org, konradybcio@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sudarshan Shetty , Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v15 3/3] arm64: dts: qcom: talos-evk: Add support for QCS615 talos evk board Date: Mon, 2 Mar 2026 17:41:59 +0530 Message-Id: <20260302121159.1938694-4-tessolveupstream@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260302121159.1938694-1-tessolveupstream@gmail.com> References: <20260302121159.1938694-1-tessolveupstream@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add the device tree for the QCS615-based Talos EVK platform. The platform is composed of a System-on-Module following the SMARC standard, and a Carrier Board. The Carrier Board supports several display configurations, HDMI and LVDS. Both configurations use the same base hardware, with the display selection controlled by a DIP switch. Use a DTBO file, talos-evk-lvds-auo,g133han01.dtso, which defines an overlay that disables HDMI and adds LVDS. The DTs file talos-evk can describe the HDMI display configurations. According to the hardware design and vendor guidance, the WiFi PA supplies VDD_PA_A and VDD_PA_B only need to be enabled at the same time as asserting WLAN_EN. On this platform, WiFi enablement is controlled via the WLAN_EN GPIO (GPIO84), which also drives the VDD_PA_A and VDD_PA_B power enables. Remove the VDD_PA_A and VDD_PA_B regulator nodes from the device tree and rely on WLAN_EN to enable WiFi functionality. Add talos-evk-usb1-peripheral.dtso overlay to enable USB0 peripheral (EDL) mode. The base DTS will keep USB0 host-only due to hardware routing through the EDL DIP switch, and the overlay switches the configuration for device-mode operation. The LVDS backlight hardware has been updated to use a simplified design. The backlight enable signal is now permanently pulled up to 3.3V and is no longer controlled via GPIO59. Remove the GPIO59 based backlight configuration from the device tree, as it is no longer routed to the LVDS interface. The initial device tree includes support for: - CPU and memory - UART - GPIOs - Regulators - PMIC - Early console - AT24MAC602 EEPROM - MCP2515 SPI to CAN - ADV7535 DSI-to-HDMI bridge - DisplayPort interface - SN65DSI84ZXHR DSI-to-LVDS bridge - Wi-Fi/BT Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Sudarshan Shetty --- arch/arm64/boot/dts/qcom/Makefile | 6 + .../qcom/talos-evk-lvds-auo,g133han01.dtso | 127 ++++ arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 614 ++++++++++++++++++ .../dts/qcom/talos-evk-usb1-peripheral.dtso | 10 + arch/arm64/boot/dts/qcom/talos-evk.dts | 139 ++++ 5 files changed, 896 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.d= tso create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-som.dtsi create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso create mode 100644 arch/arm64/boot/dts/qcom/talos-evk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index f80b5d9cf1e8..4dd34a36dcf5 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -348,6 +348,12 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8750-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8750-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D talos-evk.dtb +talos-evk-usb1-peripheral-dtbs :=3D talos-evk.dtb talos-evk-usb1-periphera= l.dtbo +dtb-$(CONFIG_ARCH_QCOM) +=3D talos-evk-usb1-peripheral.dtb +talos-evk-lvds-auo,g133han01-dtbs :=3D \ + talos-evk.dtb talos-evk-lvds-auo,g133han01.dtbo +dtb-$(CONFIG_ARCH_QCOM) +=3D talos-evk-lvds-auo,g133han01.dtb x1e001de-devkit-el2-dtbs :=3D x1e001de-devkit.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D x1e001de-devkit.dtb x1e001de-devkit-el2.dtb x1e78100-lenovo-thinkpad-t14s-el2-dtbs :=3D x1e78100-lenovo-thinkpad-t14s.= dtb x1-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso b/a= rch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso new file mode 100644 index 000000000000..77a061f36292 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; +/plugin/; + +#include + +&{/} { + backlight: backlight { + compatible =3D "gpio-backlight"; + gpios =3D <&tlmm 115 GPIO_ACTIVE_HIGH>; + default-on; + }; + + panel-lvds { + compatible =3D "auo,g133han01"; + power-supply =3D <&vreg_v3p3>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* LVDS A (Odd pixels) */ + port@0 { + reg =3D <0>; + dual-lvds-odd-pixels; + + lvds_panel_out_a: endpoint { + remote-endpoint =3D <&sn65dsi84_out_a>; + }; + }; + + /* LVDS B (Even pixels) */ + port@1 { + reg =3D <1>; + dual-lvds-even-pixels; + + lvds_panel_out_b: endpoint { + remote-endpoint =3D <&sn65dsi84_out_b>; + }; + }; + }; + }; + + vreg_v3p3: regulator-v3p3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd-3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; +}; + +&hdmi_connector { + status =3D "disabled"; +}; + +&i2c1 { + clock-frequency =3D <400000>; + status =3D "okay"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + hdmi_bridge: bridge@3d { + reg =3D <0x3d>; + status =3D "disabled"; + }; + + lvds_bridge: bridge@2c { + compatible =3D "ti,sn65dsi84"; + reg =3D <0x2c>; + enable-gpios =3D <&tlmm 42 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + sn65dsi84_in: endpoint { + data-lanes =3D <1 2 3 4>; + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg =3D <2>; + + sn65dsi84_out_a: endpoint { + data-lanes =3D <1 2 3 4>; + remote-endpoint =3D <&lvds_panel_out_a>; + }; + }; + + port@3 { + reg =3D <3>; + + sn65dsi84_out_b: endpoint { + data-lanes =3D <1 2 3 4>; + remote-endpoint =3D <&lvds_panel_out_b>; + }; + }; + }; + }; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l11a>; + + status =3D "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&sn65dsi84_in>; + data-lanes =3D <0 1 2 3>; +}; + +&tlmm { + lcd_bklt_en: lcd-bklt-en-state { + pins =3D "gpio115"; + function =3D "gpio"; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/= dts/qcom/talos-evk-som.dtsi new file mode 100644 index 000000000000..e57dc370c4e4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -0,0 +1,614 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include +#include +#include "talos.dtsi" +#include "pm8150.dtsi" +/ { + aliases { + i2c1 =3D &i2c1; + i2c5 =3D &i2c5; + mmc0 =3D &sdhc_1; + serial0 =3D &uart0; + serial1 =3D &uart7; + spi6 =3D &spi6; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + can_osc: can-oscillator { + compatible =3D "fixed-clock"; + clock-frequency =3D <20000000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32764>; + #clock-cells =3D <0>; + }; + + xo_board_clk: xo-board-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + }; + + regulator-usb2-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "USB2_VBUS"; + gpio =3D <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&usb2_en>; + pinctrl-names =3D "default"; + enable-active-high; + regulator-always-on; + }; + + vreg_conn_1p8: regulator-conn-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_conn_1p8"; + startup-delay-us =3D <4000>; + enable-active-high; + gpio =3D <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + }; + + vreg_conn_pa: regulator-conn-pa { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_conn_pa"; + startup-delay-us =3D <4000>; + enable-active-high; + gpio =3D <&pm8150_gpios 6 GPIO_ACTIVE_HIGH>; + }; + + vreg_v3p3_can: regulator-v3p3-can { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg-v3p3-can"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_v5p0_can: regulator-v5p0-can { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg-v5p0-can"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + wcn6855-pmu { + compatible =3D "qcom,wcn6855-pmu"; + + pinctrl-0 =3D <&bt_en_state>, <&wlan_en_state>; + pinctrl-names =3D "default"; + + bt-enable-gpios =3D <&tlmm 85 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios =3D <&tlmm 84 GPIO_ACTIVE_HIGH>; + + vddio-supply =3D <&vreg_conn_pa>; + vddaon-supply =3D <&vreg_s5a>; + vddpmu-supply =3D <&vreg_conn_1p8>; + vddpmumx-supply =3D <&vreg_conn_1p8>; + vddpmucx-supply =3D <&vreg_conn_pa>; + vddrfa0p95-supply =3D <&vreg_s5a>; + vddrfa1p3-supply =3D <&vreg_s6a>; + vddrfa1p9-supply =3D <&vreg_l15a>; + vddpcie1p3-supply =3D <&vreg_s6a>; + vddpcie1p9-supply =3D <&vreg_l15a>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name =3D "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name =3D "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vreg_s3a: smps3 { + regulator-name =3D "vreg_s3a"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <650000>; + regulator-initial-mode =3D ; + }; + + vreg_s4a: smps4 { + regulator-name =3D "vreg_s4a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1829000>; + regulator-initial-mode =3D ; + }; + + vreg_s5a: smps5 { + regulator-name =3D "vreg_s5a"; + regulator-min-microvolt =3D <1896000>; + regulator-max-microvolt =3D <2040000>; + regulator-initial-mode =3D ; + }; + + vreg_s6a: smps6 { + regulator-name =3D "vreg_s6a"; + regulator-min-microvolt =3D <1304000>; + regulator-max-microvolt =3D <1404000>; + regulator-initial-mode =3D ; + }; + + vreg_l1a: ldo1 { + regulator-name =3D "vreg_l1a"; + regulator-min-microvolt =3D <488000>; + regulator-max-microvolt =3D <852000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2a: ldo2 { + regulator-name =3D "vreg_l2a"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <3100000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3a: ldo3 { + regulator-name =3D "vreg_l3a"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1248000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5a: ldo5 { + regulator-name =3D "vreg_l5a"; + regulator-min-microvolt =3D <875000>; + regulator-max-microvolt =3D <975000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7a: ldo7 { + regulator-name =3D "vreg_l7a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1900000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8a: ldo8 { + regulator-name =3D "vreg_l8a"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1350000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l10a: ldo10 { + regulator-name =3D "vreg_l10a"; + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l11a: ldo11 { + regulator-name =3D "vreg_l11a"; + regulator-min-microvolt =3D <1232000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l12a: ldo12 { + regulator-name =3D "vreg_l12a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1890000>; + regulator-initial-mode =3D ; + }; + + vreg_l13a: ldo13 { + regulator-name =3D "vreg_l13a"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3230000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15a: ldo15 { + regulator-name =3D "vreg_l15a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1904000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l16a: ldo16 { + regulator-name =3D "vreg_l16a"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l17a: ldo17 { + regulator-name =3D "vreg_l17a"; + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&gpi_dma0 { + status =3D "okay"; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&i2c5 { + clock-frequency =3D <400000>; + status =3D "okay"; + + eeprom@57 { + compatible =3D "atmel,24c02"; + reg =3D <0x57>; + pagesize =3D <16>; + }; + + eeprom@5f { + compatible =3D "atmel,24mac602"; + reg =3D <0x5f>; + pagesize =3D <16>; + }; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000>; + remote-endpoint =3D <&dp0_connector_in>; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l11a>; + status =3D "okay"; +}; + +&mdss_dsi0_phy { + vcca-supply =3D <&vreg_l5a>; + status =3D "okay"; +}; + +&pcie { + perst-gpios =3D <&tlmm 89 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 100 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&pcie_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie_phy { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + + status =3D "okay"; +}; + +&pcie_port0 { + wifi@0 { + compatible =3D "pci17cb,1103"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + qcom,calibration-variant =3D "QC_QCS615_Ride"; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p7>; + vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + }; +}; + +&pm8150_gpios { + usb2_en: usb2-en-state { + pins =3D "gpio10"; + function =3D "normal"; + output-enable; + power-source =3D <0>; + }; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/qcs615/adsp.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/qcs615/cdsp.mbn"; + + status =3D "okay"; +}; + +&sdhc_1 { + pinctrl-0 =3D <&sdc1_state_on>; + pinctrl-1 =3D <&sdc1_state_off>; + pinctrl-names =3D "default", "sleep"; + + bus-width =3D <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + vmmc-supply =3D <&vreg_l17a>; + vqmmc-supply =3D <&vreg_s4a>; + + non-removable; + no-sd; + no-sdio; + + status =3D "okay"; +}; + +&spi6 { + status =3D "okay"; + + can@0 { + compatible =3D "microchip,mcp2515"; + reg =3D <0>; + clocks =3D <&can_osc>; + interrupts-extended =3D <&tlmm 87 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency =3D <10000000>; + vdd-supply =3D <&vreg_v3p3_can>; + xceiver-supply =3D <&vreg_v5p0_can>; + }; +}; + +&tlmm { + bt_en_state: bt-en-state { + pins =3D "gpio85"; + function =3D "gpio"; + bias-pull-down; + }; + + pcie_default_state: pcie-default-state { + clkreq-pins { + pins =3D "gpio90"; + function =3D "pcie_clk_req"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-pins { + pins =3D "gpio89"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + wake-pins { + pins =3D "gpio100"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + wifi_reg_en_pins_state: wifi-reg-en-pins-state { + pins =3D "gpio91"; + function =3D "gpio"; + drive-strength =3D <8>; + output-high; + bias-pull-up; + }; + + wlan_en_state: wlan-en-state { + pins =3D "gpio84"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-pull-up; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart7 { + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn6855-bt"; + firmware-name =3D "QCA6698/hpnv21", "QCA6698/hpbtfw21.tlv"; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddbtcmx-supply =3D <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p7>; + }; +}; + +/* + * USB0 routing and EDL mode: + * + * The USB0 controller=E2=80=99s HS differential pair is switched (manuall= y) + * between the Micro-USB port for EDL/ADB and the on-board USB 3.0 hub. + * + * During EDL (Emergency Download) mode, the HS lines are explicitly + * routed to the Micro-USB port to allow the SoC to enter device mode + * for flashing. + * + * After EDL the switch is normally toggled so the HS lines stay + * connected to the hub=E2=80=99s Type-A downstream ports, leaving no elec= trical + * path to the Micro-USB connector =E2=80=94 therefore USB0 runs host-only= in + * normal runtime and device mode must not be advertised. + * + * USB0 is configured host-only in the base device tree; a separate + * device-tree overlay enables the Micro-USB peripheral configuration for + * ADB. For ADB to work during normal runtime the DIP switch SW1 must be + * manually toggled to the off position (reconnecting the HS pair to the + * Micro-USB port). + */ + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "host"; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + vdda-phy-dpdm-supply =3D <&vreg_l13a>; + + status =3D "okay"; +}; + +&usb_2 { + status =3D "okay"; +}; + +&usb_2_dwc3 { + dr_mode =3D "host"; +}; + +&usb_2_hsphy { + vdd-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + vdda-phy-dpdm-supply =3D <&vreg_l13a>; + + status =3D "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + + status =3D "okay"; +}; + +&usb_qmpphy_2 { + vdda-phy-supply =3D <&vreg_l11a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 123 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&vreg_l17a>; + vcc-max-microamp =3D <600000>; + vccq2-supply =3D <&vreg_s4a>; + vccq2-max-microamp =3D <600000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + + status =3D "okay"; +}; + +&venus { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso b/arch= /arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso new file mode 100644 index 000000000000..2f4630a6ba66 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; +/plugin/; + +&usb_1_dwc3 { + dr_mode =3D "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-evk.dts b/arch/arm64/boot/dts/q= com/talos-evk.dts new file mode 100644 index 000000000000..af100e22beee --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include "talos-evk-som.dtsi" + +/ { + model =3D "Qualcomm QCS615 IQ 615 EVK"; + compatible =3D "qcom,talos-evk", "qcom,qcs615", "qcom,sm6150"; + chassis-type =3D "embedded"; + + aliases { + mmc1 =3D &sdhc_2; + }; + + dp0-connector { + compatible =3D "dp-connector"; + label =3D "DP0"; + type =3D "full-size"; + + hpd-gpios =3D <&tlmm 104 GPIO_ACTIVE_HIGH>; + + port { + dp0_connector_in: endpoint { + remote-endpoint =3D <&mdss_dp0_out>; + }; + }; + }; + + hdmi_connector: hdmi-out { + compatible =3D "hdmi-connector"; + type =3D "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint =3D <&adv7535_out>; + }; + }; + }; + + vreg_v1p8_out: regulator-v1p8-out { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg-v1p8-out"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vreg_v5p0_out>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_v3p3_out: regulator-v3p3-out { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg-v3p3-out"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vreg_v5p0_out>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_v5p0_out: regulator-v5p0-out { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg-v5p0-out"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-boot-on; + regulator-always-on; + /* Powered by system 20V rail (USBC_VBUS_IN) */ + }; +}; + +&i2c1 { + clock-frequency =3D <400000>; + status =3D "okay"; + + hdmi_bridge: bridge@3d { + compatible =3D "adi,adv7535"; + reg =3D <0x3d>; + avdd-supply =3D <&vreg_v1p8_out>; + dvdd-supply =3D <&vreg_v1p8_out>; + pvdd-supply =3D <&vreg_v1p8_out>; + a2vdd-supply =3D <&vreg_v1p8_out>; + v3p3-supply =3D <&vreg_v3p3_out>; + interrupts-extended =3D <&tlmm 26 IRQ_TYPE_LEVEL_LOW>; + adi,dsi-lanes =3D <4>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + adv7535_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + adv7535_out: endpoint { + remote-endpoint =3D <&hdmi_con_out>; + }; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&adv7535_in>; + data-lanes =3D <0 1 2 3>; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&sdhc_2 { + pinctrl-0 =3D <&sdc2_state_on>; + pinctrl-1 =3D <&sdc2_state_off>; + pinctrl-names =3D "default", "sleep"; + + bus-width =3D <4>; + cd-gpios =3D <&tlmm 99 GPIO_ACTIVE_LOW>; + + vmmc-supply =3D <&vreg_l10a>; + vqmmc-supply =3D <&vreg_s4a>; + + status =3D "okay"; +}; --=20 2.34.1