From nobody Thu Apr 9 12:06:44 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E48803624A5; Mon, 2 Mar 2026 11:33:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772451229; cv=none; b=FSxDeBT3c2AvnhUErrzlNd7fVK+/JEsBL3GRCOWMwpT3QGC1i73U+F3qATVQeNTZTDvkxLVWZcNC+WNa1qBpNRV45FwRNIUVwzpL0J+LKRku4RNNFTLvCAlSssPY7jMgeGYe1T7xflK6Jphh9QDVBVcIR/f3L5r7WNKrtMHr0Cg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772451229; c=relaxed/simple; bh=Qi6mDeLUYAi34DWMvp/7dxXLg8jcp1nz+M4Ea+q5TZo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NtvT76SNMNQ/DjV6qu+Np5uevKjDw8hIuBcUFUn1wKvxm2FVyvCObGWfdx0/LvZMEE9ENkr/We6EGmR0pvEXfLy5dgSBTo6ri5xKc18hM/dC7mvHN6nKLs3sxMruTYrE8jDa/sTnb38eqiaEeUikchMRAZ6n8TSQphA0YIV3x7o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=HjlmunFN; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="HjlmunFN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1772451227; x=1803987227; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Qi6mDeLUYAi34DWMvp/7dxXLg8jcp1nz+M4Ea+q5TZo=; b=HjlmunFNoNCh+AoVK5AGRet6e3Bkr+z+mmw8eaCS67Ed5jKSR3OVDPAy DvsSphLm1MoZSQ2ovBhp1NXomlGDdfE++0Y9GNwEfOv3mJFDXfepUKf2s EtSgjpm3F0lh7kiMa/3ExkkxEX31waR/LQZBYPwEFmJfQXxa0HmSpdVJC rmOpSgtrYTEWC6NX1pvDrV+Z5QDzseODprU0QZ5kP6cZL3mr/dRmDR6U5 KJ+wH1fpex2i/LvYevwETp/SlOhzDwRykMlTu1V9/ClAV9xuCz13LTo9R i3dJv9uYruXeIVY2Tq/9PC7q6i1ITPA/nC/fhWk3+xje4xdzsRenzUpio Q==; X-CSE-ConnectionGUID: R6kAG1m/QI27bcgiSIY67w== X-CSE-MsgGUID: fBBBJlpLRx+h9sHU7QGuEw== X-IronPort-AV: E=Sophos;i="6.21,319,1763449200"; d="scan'208";a="61522905" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Mar 2026 04:33:46 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 2 Mar 2026 04:33:19 -0700 Received: from che-ll-i71840.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 2 Mar 2026 04:33:15 -0700 From: Balakrishnan Sambath To: CC: , , , , , , Nicolas Ferre , Claudiu Beznea , Mathieu Othacehe Subject: [PATCH 1/2] watchdog: sama5d4_wdt: Fix WDDIS detection on SAM9X60 and SAMA7G5 Date: Mon, 2 Mar 2026 17:03:09 +0530 Message-ID: <20260302113310.133989-2-balakrishnan.s@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260302113310.133989-1-balakrishnan.s@microchip.com> References: <20260302113310.133989-1-balakrishnan.s@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The driver hardcoded AT91_WDT_WDDIS (bit 15) in wdt_enabled and the probe initial state readout. SAM9X60 and SAMA7G5 use bit 12 (AT91_SAM9X60_WDDIS), causing incorrect WDDIS detection. Introduce a per-device wddis_mask field to select the correct WDDIS bit based on the compatible string. Fixes: 266da53c35fc ("watchdog: sama5d4: readout initial state") Co-developed-by: Andrei Simion Signed-off-by: Andrei Simion Signed-off-by: Balakrishnan Sambath Reviewed-by: Alexandre Belloni --- drivers/watchdog/sama5d4_wdt.c | 48 +++++++++++++++------------------- 1 file changed, 21 insertions(+), 27 deletions(-) diff --git a/drivers/watchdog/sama5d4_wdt.c b/drivers/watchdog/sama5d4_wdt.c index 13e72918338a..704b786cc2ec 100644 --- a/drivers/watchdog/sama5d4_wdt.c +++ b/drivers/watchdog/sama5d4_wdt.c @@ -24,37 +24,41 @@ #define WDT_DEFAULT_TIMEOUT MAX_WDT_TIMEOUT =20 #define WDT_SEC2TICKS(s) ((s) ? (((s) << 8) - 1) : 0) =20 struct sama5d4_wdt { struct watchdog_device wdd; void __iomem *reg_base; u32 mr; u32 ir; + u32 wddis_mask; unsigned long last_ping; bool need_irq; bool sam9x60_support; }; =20 static int wdt_timeout; static bool nowayout =3D WATCHDOG_NOWAYOUT; =20 module_param(wdt_timeout, int, 0); MODULE_PARM_DESC(wdt_timeout, "Watchdog timeout in seconds. (default =3D " __MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")"); =20 module_param(nowayout, bool, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=3D" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); =20 -#define wdt_enabled (!(wdt->mr & AT91_WDT_WDDIS)) +static inline bool wdt_enabled(struct sama5d4_wdt *wdt) +{ + return !(wdt->mr & wdt->wddis_mask); +} =20 #define wdt_read(wdt, field) \ readl_relaxed((wdt)->reg_base + (field)) =20 /* 4 slow clock periods is 4/32768 =3D 122.07=C2=B5s*/ #define WDT_DELAY usecs_to_jiffies(123) =20 static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val) { @@ -75,55 +79,49 @@ static void wdt_write_nosleep(struct sama5d4_wdt *wdt, = u32 field, u32 val) udelay(123); writel_relaxed(val, wdt->reg_base + field); wdt->last_ping =3D jiffies; } =20 static int sama5d4_wdt_start(struct watchdog_device *wdd) { struct sama5d4_wdt *wdt =3D watchdog_get_drvdata(wdd); =20 - if (wdt->sam9x60_support) { + if (wdt->sam9x60_support) writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IER); - wdt->mr &=3D ~AT91_SAM9X60_WDDIS; - } else { - wdt->mr &=3D ~AT91_WDT_WDDIS; - } + wdt->mr &=3D ~wdt->wddis_mask; wdt_write(wdt, AT91_WDT_MR, wdt->mr); =20 return 0; } =20 static int sama5d4_wdt_stop(struct watchdog_device *wdd) { struct sama5d4_wdt *wdt =3D watchdog_get_drvdata(wdd); =20 - if (wdt->sam9x60_support) { + if (wdt->sam9x60_support) writel_relaxed(wdt->ir, wdt->reg_base + AT91_SAM9X60_IDR); - wdt->mr |=3D AT91_SAM9X60_WDDIS; - } else { - wdt->mr |=3D AT91_WDT_WDDIS; - } + wdt->mr |=3D wdt->wddis_mask; wdt_write(wdt, AT91_WDT_MR, wdt->mr); =20 return 0; } =20 static int sama5d4_wdt_ping(struct watchdog_device *wdd) { struct sama5d4_wdt *wdt =3D watchdog_get_drvdata(wdd); =20 wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT); =20 return 0; } =20 static int sama5d4_wdt_set_timeout(struct watchdog_device *wdd, - unsigned int timeout) + unsigned int timeout) { struct sama5d4_wdt *wdt =3D watchdog_get_drvdata(wdd); u32 value =3D WDT_SEC2TICKS(timeout); =20 if (wdt->sam9x60_support) { wdt_write(wdt, AT91_SAM9X60_WLR, AT91_SAM9X60_SET_COUNTER(value)); =20 wdd->timeout =3D timeout; @@ -134,20 +132,20 @@ static int sama5d4_wdt_set_timeout(struct watchdog_de= vice *wdd, wdt->mr |=3D AT91_WDT_SET_WDV(value); =20 /* * WDDIS has to be 0 when updating WDD/WDV. The datasheet states: When * setting the WDDIS bit, and while it is set, the fields WDV and WDD * must not be modified. * If the watchdog is enabled, then the timeout can be updated. Else, * wait that the user enables it. */ - if (wdt_enabled) - wdt_write(wdt, AT91_WDT_MR, wdt->mr & ~AT91_WDT_WDDIS); + if (wdt_enabled(wdt)) + wdt_write(wdt, AT91_WDT_MR, wdt->mr & ~wdt->wddis_mask); =20 wdd->timeout =3D timeout; =20 return 0; } =20 static const struct watchdog_info sama5d4_wdt_info =3D { .options =3D WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, .identity =3D "Atmel SAMA5D4 Watchdog", @@ -178,22 +176,19 @@ static irqreturn_t sama5d4_wdt_irq_handler(int irq, v= oid *dev_id) } =20 return IRQ_HANDLED; } =20 static int of_sama5d4_wdt_init(struct device_node *np, struct sama5d4_wdt = *wdt) { const char *tmp; =20 - if (wdt->sam9x60_support) - wdt->mr =3D AT91_SAM9X60_WDDIS; - else - wdt->mr =3D AT91_WDT_WDDIS; + wdt->mr =3D wdt->wddis_mask; =20 if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) && !strcmp(tmp, "software")) wdt->need_irq =3D true; =20 if (of_property_read_bool(np, "atmel,idle-halt")) wdt->mr |=3D AT91_WDT_WDIDLEHLT; =20 if (of_property_read_bool(np, "atmel,dbg-halt")) @@ -207,27 +202,23 @@ static int sama5d4_wdt_init(struct sama5d4_wdt *wdt) u32 reg, val; =20 val =3D WDT_SEC2TICKS(WDT_DEFAULT_TIMEOUT); /* * When booting and resuming, the bootloader may have changed the * watchdog configuration. * If the watchdog is already running, we can safely update it. * Else, we have to disable it properly. */ - if (!wdt_enabled) { + if (!wdt_enabled(wdt)) { reg =3D wdt_read(wdt, AT91_WDT_MR); - if (wdt->sam9x60_support && (!(reg & AT91_SAM9X60_WDDIS))) - wdt_write_nosleep(wdt, AT91_WDT_MR, - reg | AT91_SAM9X60_WDDIS); - else if (!wdt->sam9x60_support && - (!(reg & AT91_WDT_WDDIS))) + if (!(reg & wdt->wddis_mask)) wdt_write_nosleep(wdt, AT91_WDT_MR, - reg | AT91_WDT_WDDIS); + reg | wdt->wddis_mask); } =20 if (wdt->sam9x60_support) { if (wdt->need_irq) wdt->ir =3D AT91_SAM9X60_PERINT; else wdt->mr |=3D AT91_SAM9X60_PERIODRST; =20 wdt_write(wdt, AT91_SAM9X60_IER, wdt->ir); @@ -267,18 +258,21 @@ static int sama5d4_wdt_probe(struct platform_device *= pdev) wdd->ops =3D &sama5d4_wdt_ops; wdd->min_timeout =3D MIN_WDT_TIMEOUT; wdd->max_timeout =3D MAX_WDT_TIMEOUT; wdt->last_ping =3D jiffies; =20 if (of_device_is_compatible(dev->of_node, "microchip,sam9x60-wdt") || of_device_is_compatible(dev->of_node, "microchip,sama7g5-wdt")) wdt->sam9x60_support =3D true; =20 + wdt->wddis_mask =3D wdt->sam9x60_support ? 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Update comments to reflect this and add SAMA7G5 and SAM9X75 datasheet references to the file header. Signed-off-by: Balakrishnan Sambath Reviewed-by: Alexandre Belloni --- drivers/watchdog/at91sam9_wdt.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/at91sam9_wdt.h b/drivers/watchdog/at91sam9_wd= t.h index 298d545df1a1..2020694f8f6f 100644 --- a/drivers/watchdog/at91sam9_wdt.h +++ b/drivers/watchdog/at91sam9_wdt.h @@ -3,40 +3,42 @@ * drivers/watchdog/at91sam9_wdt.h * * Copyright (C) 2007 Andrew Victor * Copyright (C) 2007 Atmel Corporation. * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries * * Watchdog Timer (WDT) - System peripherals regsters. * Based on AT91SAM9261 datasheet revision D. * Based on SAM9X60 datasheet. + * Based on SAMA7G5 datasheet. + * Based on SAM9X75 datasheet. * */ =20 #ifndef AT91_WDT_H #define AT91_WDT_H =20 #include =20 #define AT91_WDT_CR 0x00 /* Watchdog Control Register */ #define AT91_WDT_WDRSTT BIT(0) /* Restart */ #define AT91_WDT_KEY (0xa5UL << 24) /* KEY Password */ =20 #define AT91_WDT_MR 0x04 /* Watchdog Mode Register */ #define AT91_WDT_WDV (0xfffUL << 0) /* Counter Value */ #define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV) #define AT91_SAM9X60_PERIODRST BIT(4) /* Period Reset */ #define AT91_SAM9X60_RPTHRST BIT(5) /* Minimum Restart Period */ #define AT91_WDT_WDFIEN BIT(12) /* Fault Interrupt Enable */ -#define AT91_SAM9X60_WDDIS BIT(12) /* Watchdog Disable */ +#define AT91_SAM9X60_WDDIS BIT(12) /* Watchdog Disable (SAM9X60, SAMA7G5= , SAM9X75) */ #define AT91_WDT_WDRSTEN BIT(13) /* Reset Processor */ #define AT91_WDT_WDRPROC BIT(14) /* Timer Restart */ -#define AT91_WDT_WDDIS BIT(15) /* Watchdog Disable */ +#define AT91_WDT_WDDIS BIT(15) /* Watchdog Disable (SAMA5, AT91SAM9261)= */ #define AT91_WDT_WDD (0xfffUL << 16) /* Delta Value */ #define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD) #define AT91_WDT_WDDBGHLT BIT(28) /* Debug Halt */ #define AT91_WDT_WDIDLEHLT BIT(29) /* Idle Halt */ =20 #define AT91_WDT_SR 0x08 /* Watchdog Status Register */ #define AT91_WDT_WDUNF BIT(0) /* Watchdog Underflow */ #define AT91_WDT_WDERR BIT(1) /* Watchdog Error */ =20 --=20 2.34.1