From nobody Thu Apr 9 16:20:00 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 809B61FC0EA for ; Mon, 2 Mar 2026 10:29:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772447382; cv=none; b=uP3i5eJBKQbsJrmxRLCNCYMq/RYKu4i2RJvC5AXAkX175WgJb3PFp7XwAaL69de+RaLoQVXN6SGEcswPURct/0f1nf9NiGiz/8VdVwvhPKDuCIh85N0m7PSUNmE3TZbWyToSvLbQsbmX+dXpeiA5Eko9qXheRVgJxvp6I/8QHn4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772447382; c=relaxed/simple; bh=GPhoEjDGFx9BVoj9SRTvn0iSRPYFTMcD7bFsJRUCGDU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V/r2csTA2U+r2x7py2GK9Rr5T/LvzylEBUWlyaeEisn//PqUhSDuGhKDkYVbSjdLtGIa2veTCgxGXxaUhQPPNxlWvaF/AfANPDuzeV9VY6s/kiCXLSsOUcT4iq84Ia3l9OPup++Ktrhl40XCW+opH/EVPhRCIZ1gnjKrcBv9h00= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l3F6z/jW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l3F6z/jW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 54995C19425; Mon, 2 Mar 2026 10:29:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772447382; bh=GPhoEjDGFx9BVoj9SRTvn0iSRPYFTMcD7bFsJRUCGDU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l3F6z/jW+A8z82YaP3zHsuVBHvexBrIhfRhZQReaN3Ddt5SN5vWEXVJ/2GUjL048o 1uflU0jYNMkDevvjmG5NyWmq4mIiWZJoHuExXQTX4vsSXyy9vHtiuL348I7bi7Ofio h67goqcaNFInfjTXFqPncylnCJ2DSN1emIouJLLG5HILQgyIRt6olz7PldklOTFsAI 61n9Y/NQIIpkAhLqHZ6HdHLmKBO0ADaTZeEhgF1AeDId7jKCTKTNOF8cS8xl47uMx1 E9wkcyUVh+NaorWUDioYMF+nUqFQv3WjroJYCWCJ2l2BxEZ3UiJ4AjLp3j1OFrnSUo E/2idZuqoBPAA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vx0Wy-0000000FBCc-0jt2; Mon, 02 Mar 2026 10:29:40 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH 1/5] clocksource/drivers/arm_arch_timer: Add a static key indicating the need for a runtime workaround Date: Mon, 2 Mar 2026 10:29:33 +0000 Message-ID: <20260302102937.1516059-2-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302102937.1516059-1-maz@kernel.org> References: <20260302102937.1516059-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" In order to decide whether we can read the architected counter without disabling preemption to look up a workaround, introduce a static key that denotes whether a workaround is required at all. The behaviour of this new static key is a bit unusual: - it starts as 'true', indicating that workarounds are required - each time a new CPU boots, it is added to a cpumask - when all possible CPUs have booted at least once, and that it has been established that none of them require a workaround, the key flips to 'false' Of course, as long as not all the CPUs have booted once, you may end-up with slow accessors, but that's what you get for not sharing your toys. Things are made a bit complicated because static keys cannot be flipped from a CPUHP callback. Instead, schedule a deferred work from there. Yes, this is fun. Nothing is making use of this stuff yet, but watch this space. Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm= _arch_timer.c index 90aeff44a2764..c5b42001c9282 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -90,6 +90,8 @@ static int arch_counter_get_width(void) /* * Architected system timer support. */ +static inline bool arch_counter_broken_accessors(void); + static noinstr u64 raw_counter_get_cntpct_stable(void) { return __arch_counter_get_cntpct_stable(); @@ -555,10 +557,40 @@ static bool arch_timer_counter_has_wa(void) { return atomic_read(&timer_unstable_counter_workaround_in_use); } + +static DEFINE_STATIC_KEY_TRUE(broken_cnt_accessors); + +static inline bool arch_counter_broken_accessors(void) +{ + return static_branch_unlikely(&broken_cnt_accessors); +} + +static void enable_direct_accessors(struct work_struct *wk) +{ + pr_info("Enabling direct accessors\n"); + static_branch_disable(&broken_cnt_accessors); +} + +static int arch_timer_set_direct_accessors(unsigned int cpu) +{ + static DECLARE_WORK(enable_accessors_wk, enable_direct_accessors); + static cpumask_t seen_cpus; + + cpumask_set_cpu(cpu, &seen_cpus); + + if (arch_counter_broken_accessors() && + !arch_timer_counter_has_wa() && + cpumask_equal(&seen_cpus, cpu_possible_mask)) + schedule_work(&enable_accessors_wk); + + return 0; +} #else #define arch_timer_check_ool_workaround(t,a) do { } while(0) #define arch_timer_this_cpu_has_cntvct_wa() ({false;}) #define arch_timer_counter_has_wa() ({false;}) +static inline bool arch_counter_broken_accessors(void) { return false ; } +#define arch_timer_set_direct_accessors(c) do { } while(0) #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */ =20 static __always_inline irqreturn_t timer_handler(const int access, @@ -840,6 +872,7 @@ static int arch_timer_starting_cpu(unsigned int cpu) } =20 arch_counter_set_user_access(); + arch_timer_set_direct_accessors(cpu); =20 return 0; } --=20 2.47.3