From nobody Thu Apr 9 14:53:28 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 809B61FC0EA for ; Mon, 2 Mar 2026 10:29:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772447382; cv=none; b=uP3i5eJBKQbsJrmxRLCNCYMq/RYKu4i2RJvC5AXAkX175WgJb3PFp7XwAaL69de+RaLoQVXN6SGEcswPURct/0f1nf9NiGiz/8VdVwvhPKDuCIh85N0m7PSUNmE3TZbWyToSvLbQsbmX+dXpeiA5Eko9qXheRVgJxvp6I/8QHn4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772447382; c=relaxed/simple; bh=GPhoEjDGFx9BVoj9SRTvn0iSRPYFTMcD7bFsJRUCGDU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V/r2csTA2U+r2x7py2GK9Rr5T/LvzylEBUWlyaeEisn//PqUhSDuGhKDkYVbSjdLtGIa2veTCgxGXxaUhQPPNxlWvaF/AfANPDuzeV9VY6s/kiCXLSsOUcT4iq84Ia3l9OPup++Ktrhl40XCW+opH/EVPhRCIZ1gnjKrcBv9h00= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l3F6z/jW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l3F6z/jW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 54995C19425; Mon, 2 Mar 2026 10:29:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772447382; bh=GPhoEjDGFx9BVoj9SRTvn0iSRPYFTMcD7bFsJRUCGDU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l3F6z/jW+A8z82YaP3zHsuVBHvexBrIhfRhZQReaN3Ddt5SN5vWEXVJ/2GUjL048o 1uflU0jYNMkDevvjmG5NyWmq4mIiWZJoHuExXQTX4vsSXyy9vHtiuL348I7bi7Ofio h67goqcaNFInfjTXFqPncylnCJ2DSN1emIouJLLG5HILQgyIRt6olz7PldklOTFsAI 61n9Y/NQIIpkAhLqHZ6HdHLmKBO0ADaTZeEhgF1AeDId7jKCTKTNOF8cS8xl47uMx1 E9wkcyUVh+NaorWUDioYMF+nUqFQv3WjroJYCWCJ2l2BxEZ3UiJ4AjLp3j1OFrnSUo E/2idZuqoBPAA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vx0Wy-0000000FBCc-0jt2; Mon, 02 Mar 2026 10:29:40 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH 1/5] clocksource/drivers/arm_arch_timer: Add a static key indicating the need for a runtime workaround Date: Mon, 2 Mar 2026 10:29:33 +0000 Message-ID: <20260302102937.1516059-2-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302102937.1516059-1-maz@kernel.org> References: <20260302102937.1516059-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" In order to decide whether we can read the architected counter without disabling preemption to look up a workaround, introduce a static key that denotes whether a workaround is required at all. The behaviour of this new static key is a bit unusual: - it starts as 'true', indicating that workarounds are required - each time a new CPU boots, it is added to a cpumask - when all possible CPUs have booted at least once, and that it has been established that none of them require a workaround, the key flips to 'false' Of course, as long as not all the CPUs have booted once, you may end-up with slow accessors, but that's what you get for not sharing your toys. Things are made a bit complicated because static keys cannot be flipped from a CPUHP callback. Instead, schedule a deferred work from there. Yes, this is fun. Nothing is making use of this stuff yet, but watch this space. Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm= _arch_timer.c index 90aeff44a2764..c5b42001c9282 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -90,6 +90,8 @@ static int arch_counter_get_width(void) /* * Architected system timer support. */ +static inline bool arch_counter_broken_accessors(void); + static noinstr u64 raw_counter_get_cntpct_stable(void) { return __arch_counter_get_cntpct_stable(); @@ -555,10 +557,40 @@ static bool arch_timer_counter_has_wa(void) { return atomic_read(&timer_unstable_counter_workaround_in_use); } + +static DEFINE_STATIC_KEY_TRUE(broken_cnt_accessors); + +static inline bool arch_counter_broken_accessors(void) +{ + return static_branch_unlikely(&broken_cnt_accessors); +} + +static void enable_direct_accessors(struct work_struct *wk) +{ + pr_info("Enabling direct accessors\n"); + static_branch_disable(&broken_cnt_accessors); +} + +static int arch_timer_set_direct_accessors(unsigned int cpu) +{ + static DECLARE_WORK(enable_accessors_wk, enable_direct_accessors); + static cpumask_t seen_cpus; + + cpumask_set_cpu(cpu, &seen_cpus); + + if (arch_counter_broken_accessors() && + !arch_timer_counter_has_wa() && + cpumask_equal(&seen_cpus, cpu_possible_mask)) + schedule_work(&enable_accessors_wk); + + return 0; +} #else #define arch_timer_check_ool_workaround(t,a) do { } while(0) #define arch_timer_this_cpu_has_cntvct_wa() ({false;}) #define arch_timer_counter_has_wa() ({false;}) +static inline bool arch_counter_broken_accessors(void) { return false ; } +#define arch_timer_set_direct_accessors(c) do { } while(0) #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */ =20 static __always_inline irqreturn_t timer_handler(const int access, @@ -840,6 +872,7 @@ static int arch_timer_starting_cpu(unsigned int cpu) } =20 arch_counter_set_user_access(); + arch_timer_set_direct_accessors(cpu); =20 return 0; } --=20 2.47.3 From nobody Thu Apr 9 14:53:28 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6AE539B97D for ; Mon, 2 Mar 2026 10:29:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772447382; cv=none; b=XKgYqXNYw28GAtNzBrhJlG7S/jTczzINuPG3GjCa2kQkNaHg0gq5Kdar+Mto2guAaGEfhxnQZqLj3MpHB+LClE9kRNMD8Z74l0/M8X1HWudH8c20Dc8QfGuaWSVzLwoodRr+0mu+8v1w8QPZaziKu0dmncVNImiX/x4VZ5ezauc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772447382; c=relaxed/simple; bh=PlhXgFp9jn4wn5ui/B/bv4QBDAuir3YiMvnBhoH2GEI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Bk12WAccAyWKlEx0GNQm4J0PM3ykhJ7dK5K78q80yLnO1fajtmQC01XT+NNLDmmC42xDSZLeumKJW+j4TtAf5XY2RzHOf+8v+ksWJmCIg9XCl1NbG7jcxgxZ9vID8BW1n4yPwlygmbuIEDaBm4f7EhnaB2K6RqShmrxQqDqdPHQ= ARC-Authentication-Results: i=1; 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Mon, 02 Mar 2026 10:29:40 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH 2/5] clocksource/drivers/arm_arch_timer: Convert counter accessors to a static key alternative Date: Mon, 2 Mar 2026 10:29:34 +0000 Message-ID: <20260302102937.1516059-3-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302102937.1516059-1-maz@kernel.org> References: <20260302102937.1516059-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" Now that we have a reliable static key to control whether our counter accessors need to be worked around, use it in these accessors and simplify the logic that picks which accessor to use. Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 38 +++++++++++++++------------- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm= _arch_timer.c index c5b42001c9282..723ba698b8c46 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -92,9 +92,12 @@ static int arch_counter_get_width(void) */ static inline bool arch_counter_broken_accessors(void); =20 -static noinstr u64 raw_counter_get_cntpct_stable(void) +static noinstr u64 raw_counter_get_cntpct(void) { - return __arch_counter_get_cntpct_stable(); + if (arch_counter_broken_accessors()) + return __arch_counter_get_cntpct_stable(); + + return __arch_counter_get_cntpct(); } =20 static notrace u64 arch_counter_get_cntpct_stable(void) @@ -108,12 +111,18 @@ static notrace u64 arch_counter_get_cntpct_stable(voi= d) =20 static noinstr u64 arch_counter_get_cntpct(void) { + if (arch_counter_broken_accessors()) + return arch_counter_get_cntpct_stable(); + return __arch_counter_get_cntpct(); } =20 -static noinstr u64 raw_counter_get_cntvct_stable(void) +static noinstr u64 raw_counter_get_cntvct(void) { - return __arch_counter_get_cntvct_stable(); + if (arch_counter_broken_accessors()) + return __arch_counter_get_cntvct_stable(); + + return __arch_counter_get_cntvct(); } =20 static notrace u64 arch_counter_get_cntvct_stable(void) @@ -127,6 +136,9 @@ static notrace u64 arch_counter_get_cntvct_stable(void) =20 static noinstr u64 arch_counter_get_cntvct(void) { + if (arch_counter_broken_accessors()) + return arch_counter_get_cntvct_stable(); + return __arch_counter_get_cntvct(); } =20 @@ -946,21 +958,11 @@ static void __init arch_counter_register(void) =20 if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) || arch_timer_uses_ppi =3D=3D ARCH_TIMER_VIRT_PPI) { - if (arch_timer_counter_has_wa()) { - rd =3D arch_counter_get_cntvct_stable; - scr =3D raw_counter_get_cntvct_stable; - } else { - rd =3D arch_counter_get_cntvct; - scr =3D arch_counter_get_cntvct; - } + rd =3D arch_counter_get_cntvct; + scr =3D raw_counter_get_cntvct; } else { - if (arch_timer_counter_has_wa()) { - rd =3D arch_counter_get_cntpct_stable; - scr =3D raw_counter_get_cntpct_stable; - } else { - rd =3D arch_counter_get_cntpct; - scr =3D arch_counter_get_cntpct; - } + rd =3D arch_counter_get_cntpct; + scr =3D raw_counter_get_cntpct; } =20 arch_timer_read_counter =3D rd; --=20 2.47.3 From nobody Thu Apr 9 14:53:28 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F21F3A0EA6 for ; Mon, 2 Mar 2026 10:29:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772447383; cv=none; b=atVFh5K43zdS4wFege2H9XwC5Yudz2MoSdV3I1ASmmu8CsLsh01zR/QpiRVp5tKpbZg4Vdi5e3Xjl8M6xm5V5fMa7tD1hbExhALJlfHQrGGo6XNqJ9PJJJsBpZso2GlYdFnmewqXGgxcUdnvvUc3K3ZTEwrwoRUilX25a2h28ik= ARC-Message-Signature: i=1; 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SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" Further simplify the counter accessors by eliminating the *_stable() ones, which serve little purpose at this stage. Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 38 +++++++++------------------- 1 file changed, 12 insertions(+), 26 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm= _arch_timer.c index 723ba698b8c46..ee21804d6613c 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -100,19 +100,12 @@ static noinstr u64 raw_counter_get_cntpct(void) return __arch_counter_get_cntpct(); } =20 -static notrace u64 arch_counter_get_cntpct_stable(void) +static notrace u64 arch_counter_get_cntpct(void) { - u64 val; - preempt_disable_notrace(); - val =3D __arch_counter_get_cntpct_stable(); - preempt_enable_notrace(); - return val; -} - -static noinstr u64 arch_counter_get_cntpct(void) -{ - if (arch_counter_broken_accessors()) - return arch_counter_get_cntpct_stable(); + if (arch_counter_broken_accessors()) { + guard(preempt_notrace)(); + return __arch_counter_get_cntpct_stable(); + } =20 return __arch_counter_get_cntpct(); } @@ -125,19 +118,12 @@ static noinstr u64 raw_counter_get_cntvct(void) return __arch_counter_get_cntvct(); } =20 -static notrace u64 arch_counter_get_cntvct_stable(void) +static notrace u64 arch_counter_get_cntvct(void) { - u64 val; - preempt_disable_notrace(); - val =3D __arch_counter_get_cntvct_stable(); - preempt_enable_notrace(); - return val; -} - -static noinstr u64 arch_counter_get_cntvct(void) -{ - if (arch_counter_broken_accessors()) - return arch_counter_get_cntvct_stable(); + if (arch_counter_broken_accessors()) { + guard(preempt_notrace)(); + return __arch_counter_get_cntvct_stable(); + } =20 return __arch_counter_get_cntvct(); } @@ -342,10 +328,10 @@ void erratum_set_next_event_generic(const int access,= unsigned long evt, ctrl &=3D ~ARCH_TIMER_CTRL_IT_MASK; =20 if (access =3D=3D ARCH_TIMER_PHYS_ACCESS) { - cval =3D evt + arch_counter_get_cntpct_stable(); + cval =3D evt + arch_counter_get_cntpct(); write_sysreg(cval, cntp_cval_el0); } else { - cval =3D evt + arch_counter_get_cntvct_stable(); + cval =3D evt + arch_counter_get_cntvct(); write_sysreg(cval, cntv_cval_el0); } =20 --=20 2.47.3 From nobody Thu Apr 9 14:53:28 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32E333A1A26 for ; Mon, 2 Mar 2026 10:29:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772447383; cv=none; b=YSfqvLZu2x9bf/Ayc75ij6BgkReEIlSoXR0jM/oz0aalrVZE9TGOrVrSG0tZ/moGgUC0XpyMICOr4xVzcXQDCel7WpxH4dPWqwc1y9xqLNPmTbdxgJnIbgCX16Zyspcy3wFrb42JzD+h5xkM3c1D0B5jbVRAWCpijDP50vPh0uk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772447383; c=relaxed/simple; bh=Ng7f/Ng6zPtl5KJt5T+b4Vt/9C+9LhrfLa105ysMhuc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Mon, 02 Mar 2026 10:29:41 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH 4/5] clocksource/drivers/arm_arch_timer: Expose a direct accessor for the virtual counter Date: Mon, 2 Mar 2026 10:29:36 +0000 Message-ID: <20260302102937.1516059-5-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302102937.1516059-1-maz@kernel.org> References: <20260302102937.1516059-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" We allow access to the architected counter via arch_timer_read_counter(). However, this accessor can either be the virtual or the physical view of the counter, depending on how the kernel has been booted. At the same time, we have some architectural features (such as WFIT, WFET) that rely on the virtual counter, and nothing else. If implementations were perfect, we'd rely on reading CNTVCT_EL0, and be done with it. However, we have a bunch of broken implementations in the wild, which rely on preemption being disabled and other costly workarounds. In order to provide decent performance on non-broken HW while still supporting the legacy horrors, expose arch_timer_read_vcounter() as a new helper that hides this complexity. Obviously, this is simply a global alias of arch_counter_get_cntvct(). Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 2 ++ include/clocksource/arm_arch_timer.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm= _arch_timer.c index ee21804d6613c..6fcd9afad38c2 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -137,6 +137,8 @@ static notrace u64 arch_counter_get_cntvct(void) u64 (*arch_timer_read_counter)(void) __ro_after_init =3D arch_counter_get_= cntvct; EXPORT_SYMBOL_GPL(arch_timer_read_counter); =20 +u64 arch_timer_read_vcounter(void) __attribute__((alias("arch_counter_get_= cntvct"))); + static u64 arch_counter_read(struct clocksource *cs) { return arch_timer_read_counter(); diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm= _arch_timer.h index 2eda895f19f54..587314e584839 100644 --- a/include/clocksource/arm_arch_timer.h +++ b/include/clocksource/arm_arch_timer.h @@ -88,6 +88,7 @@ struct arch_timer_mem { =20 extern u32 arch_timer_get_rate(void); extern u64 (*arch_timer_read_counter)(void); +extern u64 arch_timer_read_vcounter(void); extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void); extern bool arch_timer_evtstrm_available(void); =20 --=20 2.47.3 From nobody Thu Apr 9 14:53:28 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50CE23A1CF7 for ; Mon, 2 Mar 2026 10:29:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772447383; cv=none; b=KzedtwBoz753nAbC3eRHdqWu+KaRbgBXsFjG9gacy7BCbwDzY/+IjsnLJ4fPeyAIfQKeQ9CciOxShofbUE7hVcYU9ZY3ZZkmwPSunBBFxIKgv9Hy4WIL/SzQ9gyFlHiHqhKma0Y2uo8pysCqFnc250eiNGCiRi9Jeouy1rEYVwg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772447383; c=relaxed/simple; bh=gZfp7AFUDRuKyFzNq7gSRxIUj7Mf0Qt8SSGk362fa3U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PZW6ZGcW0HifwbKTBxGO/M2l364FrA/DXZKvCE8obIsGAnD6ZCRWaLQvsq8aPxmUyCbRlJIjvAISulYusxHEl7yA6MpMa0e1ah9U/OuAT4nN/6CChdXe3CdRtC0C6yzYAlYl+JsKA7COrJiSAyIL04Pm4bMTQxhUDkOFBzuxK7E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cefjFVP5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cefjFVP5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2D83AC2BCB0; Mon, 2 Mar 2026 10:29:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772447383; bh=gZfp7AFUDRuKyFzNq7gSRxIUj7Mf0Qt8SSGk362fa3U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cefjFVP5ZXUU503rm5C3FgR8riQwmG/NgPfnQkXVgBpybjKDBzpEfLroCAdqRgyjR N+jZjca+jNX1UkKmGF0jSVMFdb7ALQOvPrgrFY1/flpVVAlSicegQo7JZHQ5RnnD3I aFPoOQYbz62cChFeNKbkex+VuJs64RIxKvwBhChHzlR5TWMdyiHdabzuE3yPZuAnSf G56G1jlcqNhPSz1bviKiQlZY+p8R8qESSmYksR2jgbuNt837ffQdZMx0jKKAmxdIIR VFl5fDFFcfsjFz6I98fuhfCrXiEhIvyDFlbW19aHYfz74kPDYFnXpTxNLFGz+C2SkH 283CmPe0sdfdg== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vx0Wz-0000000FBCc-0vne; Mon, 02 Mar 2026 10:29:41 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH 5/5] arm64: Convert __delay_cycles() to arch_timer_read_vcounter() Date: Mon, 2 Mar 2026 10:29:37 +0000 Message-ID: <20260302102937.1516059-6-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302102937.1516059-1-maz@kernel.org> References: <20260302102937.1516059-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" Relax the need for disabling preemption in __delay_cycles() by using arch_timer_read_vcounter(), which will disable preemption only when this is actually required. Signed-off-by: Marc Zyngier --- arch/arm64/lib/delay.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/lib/delay.c b/arch/arm64/lib/delay.c index e278e060e78a9..a667df920697d 100644 --- a/arch/arm64/lib/delay.c +++ b/arch/arm64/lib/delay.c @@ -32,10 +32,9 @@ static inline unsigned long xloops_to_cycles(unsigned lo= ng xloops) * Note that userspace cannot change the offset behind our back either, * as the vcpu mutex is held as long as KVM_RUN is in progress. */ -static cycles_t notrace __delay_cycles(void) +static cycles_t __delay_cycles(void) { - guard(preempt_notrace)(); - return __arch_counter_get_cntvct_stable(); + return arch_timer_read_vcounter(); } =20 void __delay(unsigned long cycles) --=20 2.47.3