From nobody Thu Apr 16 06:42:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 127D9392C42 for ; Mon, 2 Mar 2026 09:59:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772445545; cv=none; b=t6GbqXFoUSmqaauzS2lXeb4D3FFhmarVBKOCTIo2FVE03YAinZ/v+UoUyKHBaGfD1F0WI16IcAFqUPz5v+Iwhy0BFneQvFX86b883gE/fI3nBYG3TWTL/gsfkLxFVBC7Ree1RpBDdmyrF9+WuKc4DuDgwybfkopT9WR7sCPuwdY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772445545; c=relaxed/simple; bh=+U/a3l9efdYmCTx9oJhBq4AgxHYZOLO9mX+G/kxf3oc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gXCUfrm4kj6v5b5SdSH6w1StlpJ2rPvtaZQCFCrxLTZN5w33Ng5QxyPM6I5LWUcBPmzytjlzW5lStx4S0Umf0zrnsOd/PuoD+RXyaxYAFfX1NScNUfhq4xVajNetZIQsbGjh/751pCoT+m1SMihSIthWSUvqUoK1JRTqm7RW3kU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lRfLeDGo; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lRfLeDGo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772445544; x=1803981544; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+U/a3l9efdYmCTx9oJhBq4AgxHYZOLO9mX+G/kxf3oc=; b=lRfLeDGoj3MW0J9ARdALVhPFndP1ND6cjImmw8sqQG/6xiBHUoYnIn9P cJS6y25JuKr5MhMVEcrsi3B6zYPWRtj4VTp2jDIcnRoiMm//cY5/KwQgR peutWoC/kEsP7X02W02Kp/Bzk6avsriXZvqQMcAPC0iE9ZKXPnDYmr2mu WGvHNNtONcX2ner/xxSIVs7FkC8YSd8siZK05w26AD+KpIz/HNK5adC2i N83G6sDrL/3mqybiwa53TFXwZZKzJY7OuEiEjWKz8e29OrP07BBPzz0cg Hhr447+k3CkLKk8hrRSCM8bEnJ7BZDz6EW4uUB0SdlkyfBlgpP/IQEGq9 Q==; X-CSE-ConnectionGUID: c2SNTeCJTrWq5LJO8b/z0A== X-CSE-MsgGUID: 7uXfIVrUQ8W2Yo67Rp5INw== X-IronPort-AV: E=McAfee;i="6800,10657,11716"; a="96066027" X-IronPort-AV: E=Sophos;i="6.21,319,1763452800"; d="scan'208";a="96066027" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2026 01:58:52 -0800 X-CSE-ConnectionGUID: z4WytTbeSEestykCDzTCqg== X-CSE-MsgGUID: GEizdR+lRxaHwEmvS26MIw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,319,1763452800"; d="scan'208";a="217628235" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa008.jf.intel.com with ESMTP; 02 Mar 2026 01:58:51 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id F195A98; Mon, 02 Mar 2026 10:58:49 +0100 (CET) From: Andy Shevchenko To: Mark Brown , Andy Shevchenko , linux-kernel@vger.kernel.org, driver-core@lists.linux.dev Cc: Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich Subject: [PATCH v4 1/3] regcache: Move HW readback after cache initialisation Date: Mon, 2 Mar 2026 10:56:55 +0100 Message-ID: <20260302095847.2310066-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260302095847.2310066-1-andriy.shevchenko@linux.intel.com> References: <20260302095847.2310066-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make sure that cache is initialised before calling any IO using regmap, this makes sure that we won't access NULL or invalid pointers in the cache which hasn't been initialised. Signed-off-by: Andy Shevchenko --- drivers/base/regmap/regcache.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c index 73cfe8120669..ae60411ea8dc 100644 --- a/drivers/base/regmap/regcache.c +++ b/drivers/base/regmap/regcache.c @@ -67,6 +67,14 @@ static int regcache_hw_init(struct regmap *map, int coun= t) unsigned int reg, val; void *tmp_buf; =20 + /* + * When count is zero, it means there is nothing to cache and hence + * nothing to read back from HW to set up defaults, so skip this phase + * without an error code returned. + */ + if (!count) + return 0; + map->num_reg_defaults =3D count; map->reg_defaults =3D kmalloc_objs(struct reg_default, count); if (!map->reg_defaults) @@ -202,14 +210,6 @@ int regcache_init(struct regmap *map, const struct reg= map_config *config) count =3D regcache_count_cacheable_registers(map); if (map->cache_bypass) return 0; - - /* Some devices such as PMICs don't have cache defaults, - * we cope with this by reading back the HW registers and - * crafting the cache defaults by hand. - */ - ret =3D regcache_hw_init(map, count); - if (ret < 0) - return ret; } =20 if (!map->max_register_is_set && map->num_reg_defaults_raw) { @@ -227,6 +227,15 @@ int regcache_init(struct regmap *map, const struct reg= map_config *config) goto err_free; } =20 + /* + * Some devices such as PMICs don't have cache defaults, + * we cope with this by reading back the HW registers and + * crafting the cache defaults by hand. + */ + ret =3D regcache_hw_init(map, count); + if (ret) + goto err_exit; + if (map->cache_ops->populate && (map->num_reg_defaults || map->reg_default_cb)) { dev_dbg(map->dev, "Populating %s cache\n", map->cache_ops->name); --=20 2.50.1 From nobody Thu Apr 16 06:42:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 345F9392802 for ; Mon, 2 Mar 2026 09:59:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; 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d="scan'208";a="96066035" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2026 01:58:52 -0800 X-CSE-ConnectionGUID: sLO3htK8SKyWBSnKoLOFjg== X-CSE-MsgGUID: aD6qCZrASj+z+InPWa0xfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,319,1763452800"; d="scan'208";a="217628234" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa008.jf.intel.com with ESMTP; 02 Mar 2026 01:58:51 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 01BE399; Mon, 02 Mar 2026 10:58:50 +0100 (CET) From: Andy Shevchenko To: Mark Brown , Andy Shevchenko , linux-kernel@vger.kernel.org, driver-core@lists.linux.dev Cc: Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich Subject: [PATCH v4 2/3] regcache: Define iterator inside for-loop and align their types Date: Mon, 2 Mar 2026 10:56:56 +0100 Message-ID: <20260302095847.2310066-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260302095847.2310066-1-andriy.shevchenko@linux.intel.com> References: <20260302095847.2310066-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some of the iterators may be defined inside the respective for-loop reducing the scope and potential risk of their misuse. While at it, align their types based on the type of the upper or lower limits. Signed-off-by: Andy Shevchenko --- drivers/base/regmap/internal.h | 2 +- drivers/base/regmap/regcache.c | 13 ++++++------- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h index 5bf993165438..c77f3a49a89e 100644 --- a/drivers/base/regmap/internal.h +++ b/drivers/base/regmap/internal.h @@ -162,7 +162,7 @@ struct regmap { bool no_sync_defaults; =20 struct reg_sequence *patch; - int patch_regs; + unsigned int patch_regs; =20 /* if set, the regmap core can sleep */ bool can_sleep; diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c index ae60411ea8dc..2605d0bbf550 100644 --- a/drivers/base/regmap/regcache.c +++ b/drivers/base/regmap/regcache.c @@ -44,11 +44,11 @@ EXPORT_SYMBOL_GPL(regcache_sort_defaults); =20 static int regcache_count_cacheable_registers(struct regmap *map) { - int count; - int i; + unsigned int count; =20 /* calculate the size of reg_defaults */ - for (count =3D 0, i =3D 0; i < map->num_reg_defaults_raw; i++) + count =3D 0; + for (unsigned int i =3D 0; i < map->num_reg_defaults_raw; i++) if (regmap_readable(map, i * map->reg_stride) && !regmap_volatile(map, i * map->reg_stride)) count++; @@ -62,7 +62,6 @@ static int regcache_count_cacheable_registers(struct regm= ap *map) =20 static int regcache_hw_init(struct regmap *map, int count) { - int i, j; int ret; unsigned int reg, val; void *tmp_buf; @@ -103,7 +102,7 @@ static int regcache_hw_init(struct regmap *map, int cou= nt) } =20 /* fill the reg_defaults */ - for (i =3D 0, j =3D 0; i < map->num_reg_defaults_raw; i++) { + for (unsigned int i =3D 0, j =3D 0; i < map->num_reg_defaults_raw; i++) { reg =3D i * map->reg_stride; =20 if (!regmap_readable(map, reg)) @@ -849,13 +848,13 @@ static int regcache_sync_block_raw(struct regmap *map= , void *block, unsigned int block_base, unsigned int start, unsigned int end) { - unsigned int i, val; unsigned int regtmp =3D 0; unsigned int base =3D 0; const void *data =3D NULL; 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d="scan'208";a="217628233" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa008.jf.intel.com with ESMTP; 02 Mar 2026 01:58:51 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 05E1F9B; Mon, 02 Mar 2026 10:58:50 +0100 (CET) From: Andy Shevchenko To: Mark Brown , Andy Shevchenko , linux-kernel@vger.kernel.org, driver-core@lists.linux.dev Cc: Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich Subject: [PATCH v4 3/3] regcache: Amend printf() specifiers when printing registers Date: Mon, 2 Mar 2026 10:56:57 +0100 Message-ID: <20260302095847.2310066-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260302095847.2310066-1-andriy.shevchenko@linux.intel.com> References: <20260302095847.2310066-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In one case the 0x is provided in the formatting string, while the rest use # for that. In a couple of more cases a decimal signed value specifier is used. Amend them to use %#x when register is printed. Note, for the case, when it's related to the read/write, use %x to be in align with the similar messages in regmap core. Signed-off-by: Andy Shevchenko --- drivers/base/regmap/regcache.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c index 2605d0bbf550..6bec435a566b 100644 --- a/drivers/base/regmap/regcache.c +++ b/drivers/base/regmap/regcache.c @@ -120,7 +120,7 @@ static int regcache_hw_init(struct regmap *map, int cou= nt) ret =3D regmap_read(map, reg, &val); map->cache_bypass =3D cache_bypass; if (ret !=3D 0) { - dev_err(map->dev, "Failed to read %d: %d\n", + dev_err(map->dev, "Failed to read %x: %d\n", reg, ret); goto err_free; } @@ -517,7 +517,7 @@ int regcache_sync_region(struct regmap *map, unsigned i= nt min, bypass =3D map->cache_bypass; =20 name =3D map->cache_ops->name; - dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max); + dev_dbg(map->dev, "Syncing %s cache from %#x-%#x\n", name, min, max); =20 trace_regcache_sync(map, name, "start region"); =20 --=20 2.50.1